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ba9339a50d
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fix MPP reset value, PMP inactive in U-mode handling and MRET in U-mode
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2021-09-21 16:52:40 +02:00 |
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65b4db5eca
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remove mcounteren in M-mode only platform
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2021-09-18 11:40:00 +02:00 |
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0fd82f1f3c
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add tgc_d_xrb_mac to SC and C++ ISS
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2021-09-04 13:04:34 +02:00 |
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a3084456fd
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rework core definitions
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2021-09-04 12:47:07 +02:00 |
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09b01af3fa
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fix find_package use and debug access alignment check
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2021-08-26 22:10:27 +02:00 |
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9c8b72693e
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correct trap ids of access faults
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2021-08-20 09:02:56 +02:00 |
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c409e7b7ca
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adapt to fixed handling of SystemCPackage
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2021-08-19 13:38:29 +02:00 |
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2f05083cf0
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fix elf loader and pmp check for debug accesses
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2021-08-19 10:50:25 +02:00 |
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e934049dd4
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fix inconsistency due to PA adaptation
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2021-08-16 17:55:14 +02:00 |
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Eyck Jentzsch
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94f796ebdb
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add install target and PA compatibility
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2021-08-16 17:02:31 +02:00 |
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836ba269e3
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fix clic reset values
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2021-08-16 15:05:05 +02:00 |
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c8681096be
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update vm_tgfs_c to match CoreDSL
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2021-08-14 10:57:36 +02:00 |
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adeffe47ad
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fix behavior of riscv_hart_mu_p to match TGC_D
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2021-08-12 20:34:10 +02:00 |
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d95846a849
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fix trap handling if illegal fetch (PMP) and U-mode CSRs
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2021-08-01 17:23:22 +02:00 |
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af887c286f
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fix for #2
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2021-07-28 09:09:08 +02:00 |
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4ddf50162c
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make library naming consistent
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2021-07-27 15:55:08 +02:00 |
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da819d8890
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fix SystemC lib handling in build system
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2021-07-27 12:25:31 +02:00 |
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5ef5d57d30
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Merge branch 'tmp' into develop
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2021-07-27 10:49:35 +02:00 |
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d7bddd825c
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add clic CSRs
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2021-07-27 10:47:48 +02:00 |
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15f46a87db
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adapt core_complex to use scv-tr (scc commit id a3cde47)
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2021-07-27 09:38:05 +02:00 |
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fc1ae4d57d
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update build system
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2021-07-26 12:03:52 +02:00 |
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d0f3a120fd
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fix naming in MU wrapper
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2021-07-19 16:26:23 +02:00 |
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c592a26346
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fix mepc mask
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2021-07-09 13:01:22 +02:00 |
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e68918c2e8
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fix instruction decode
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2021-07-09 07:37:12 +02:00 |
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473f8a5a17
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fix privilege behavior
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2021-07-07 11:30:00 +02:00 |
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2f4b5bd9b2
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fix detailed behavior of TGC_C
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2021-07-06 21:19:36 +02:00 |
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23b9741adf
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refine and fix TGC_C iss to becoem compliant
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2021-06-29 11:51:30 +02:00 |
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5d8da08ce5
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fix linker issue
the root cuase of the issue is the template paramter deduction which led
to the wrong template parameter.
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2021-06-26 14:30:36 +02:00 |
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a249aea703
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getting rid of the error: reference to 'wait' is ambiguous
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2021-06-25 13:35:42 +02:00 |
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e432dd8208
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fix handling of exceptions while accessing address spaces
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2021-06-07 22:22:36 +02:00 |
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8c385647dd
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remove redundant code from checked in generated sources
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2021-05-26 23:06:31 +02:00 |
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aaceecd5dc
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fix mu_p platform features and CSRs
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2021-05-17 09:20:09 +02:00 |
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4b3f5a6b0c
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add missing change
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2021-05-16 16:44:30 +02:00 |
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d41e1d816a
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add factory for ISS and use it in main.cpp
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2021-05-16 16:44:14 +02:00 |
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a35974c9f5
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make cpu type in core_complex configurable
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2021-05-16 15:06:42 +02:00 |
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9c456ba8f2
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initial version of MU hart
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2021-05-14 13:29:39 +02:00 |
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c57884caee
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small fix
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2021-05-13 16:01:04 +02:00 |
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cf7b62a3f9
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update names
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2021-05-13 15:54:48 +02:00 |
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f2bf6d682a
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fix build setup
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2021-05-13 14:03:10 +02:00 |
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a1fa8877f7
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make core name a cmake option
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2021-05-13 09:32:38 +02:00 |
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391f9bb808
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remove unneeded constants
|
2021-05-08 15:14:19 +02:00 |
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ef02dba8c5
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add read misa callback
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2021-04-09 11:20:51 +02:00 |
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2f4cfb68dc
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update to latest SCC
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2021-04-07 18:56:46 +02:00 |
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7009943106
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fix wait for interrupt. Adapt for new SCC structure
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2021-04-07 17:42:08 +02:00 |
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0a76ccbdac
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make RSP register response independend of register definition
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2021-03-31 07:48:46 +00:00 |
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32e4aa83b8
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use extracted variables
|
2021-03-27 09:36:52 +00:00 |
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78c7064295
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update groovy template to extract used registers
|
2021-03-26 08:24:45 +00:00 |
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412a4bd9bb
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update name
|
2021-03-23 17:13:32 +00:00 |
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ea3ff3c0cd
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build with SCV lib
|
2021-03-23 11:57:47 +01:00 |
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b0bcb7febb
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small fixes for robustness and readability
|
2021-03-22 22:47:30 +00:00 |
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