 Eyck Jentzsch
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720236ec3f
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add generated core registration
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2023-07-14 12:51:51 +02:00 |
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Eyck Jentzsch
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957145ca84
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add SystemC ISS factory
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2023-07-14 11:11:03 +02:00 |
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Eyck Jentzsch
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0b719a4b57
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fixes literal type
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2023-07-10 20:39:02 +02:00 |
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Eyck Jentzsch
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b4b03f7850
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fixes build system to handle TCC properly
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2023-07-09 22:20:50 +02:00 |
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Eyck Jentzsch
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145a0cf68b
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updates registration of cores for sysc
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2023-07-09 20:24:45 +02:00 |
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Eyck Jentzsch
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1cef7de8c7
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fixes missing namespaces
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2023-07-09 20:16:16 +02:00 |
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Eyck Jentzsch
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e95f422aab
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cleans vm implementation up
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2023-07-09 20:13:26 +02:00 |
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Eyck Jentzsch
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250ea3c980
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extends factory to support SystemC core wrapper
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2023-07-09 18:19:59 +02:00 |
 Eyck-Alexander Jentzsch
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7b31b8ca8e
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adds updated generated files
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2023-07-09 16:58:47 +02:00 |
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Eyck-Alexander Jentzsch
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91a23a4a18
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Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop
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2023-07-09 16:55:06 +02:00 |
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Eyck Jentzsch
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a32c83e1be
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fixes CLI handling of plugin paramters in ISS
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2023-07-05 08:32:05 +02:00 |
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Eyck-Alexander Jentzsch
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87b4082633
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Merge branch 'tmp' into develop
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2023-07-03 14:22:50 +02:00 |
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Eyck Jentzsch
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4dbc7433a5
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fixes cause CSR handling
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2023-06-12 17:38:56 +02:00 |
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Eyck Jentzsch
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99a9970ddd
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fixes sysc compile issues
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2023-06-12 09:58:24 +02:00 |
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Eyck Jentzsch
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0b5de90fb1
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changes [m|u]cause rd/wr handling
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2023-06-11 18:29:58 +02:00 |
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Eyck-Alexander Jentzsch
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15cd36dcd4
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adds fix for compressed instructions and reads
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2023-06-05 17:57:38 +02:00 |
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Eyck-Alexander Jentzsch
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2281ec4144
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corrects errors and adds new backend and
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2023-06-05 15:18:27 +02:00 |
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Eyck-Alexander Jentzsch
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11c481cec2
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adds verbosity to error
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2023-06-05 15:17:16 +02:00 |
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Eyck Jentzsch
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60d07f2eb6
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changes default loglevel to info for tgc-sim
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2023-06-01 06:55:21 +02:00 |
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Eyck Jentzsch
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a123beb301
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fixes duplicate variable declaration and templates
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2023-05-27 10:20:49 +02:00 |
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Eyck Jentzsch
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ee6218279e
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adapts to latest code gen changes
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2023-05-25 12:52:30 +02:00 |
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Eyck-Alexander Jentzsch
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6ed7eafc5d
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adds inital version of tcc backend
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2023-05-16 21:51:35 +02:00 |
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Eyck Jentzsch
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32848ec396
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fixes build system and typo in wt_cache
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2023-05-13 16:57:01 +02:00 |
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Eyck Jentzsch
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6789cf4c32
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fixes case of unavailable backend
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2023-05-12 15:45:53 +02:00 |
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Eyck Jentzsch
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afdf8fb97f
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adds missing namespaces
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2023-05-11 23:11:04 +02:00 |
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Eyck Jentzsch
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cfa7b72363
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changes time handling at sockets
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2023-05-06 19:57:29 +02:00 |
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Eyck Jentzsch
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d330307ed5
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splits bus into 2 sockets for i/dbus
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2023-05-04 21:59:31 +02:00 |
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Eyck Jentzsch
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aa70d8a54a
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fixes CLIC to match clicinfo description in CLIC spec 11.04.2023
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2023-05-02 17:22:13 +02:00 |
|
Eyck Jentzsch
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b493745cd7
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sets reset start time to 0
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2023-05-02 11:21:42 +02:00 |
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Eyck Jentzsch
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f9e8e1d857
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fixes core_complex wrt. tlm quantum and DMI
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2023-05-02 11:13:25 +02:00 |
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Eyck Jentzsch
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d990f1cf5d
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fixes reading of 64bit CSR register
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2023-05-01 22:23:35 +02:00 |
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Eyck Jentzsch
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1672b01e62
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adds WT cache functionality as mixin
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2023-04-28 20:38:07 +02:00 |
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Eyck Jentzsch
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00b0f101ac
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adapts to changes of instrumentation interface in dbt-rise-core
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2023-04-28 20:38:07 +02:00 |
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Eyck Jentzsch
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8ff55d7b92
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updates CWR dependent core_complex definition
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2023-04-14 19:34:41 +02:00 |
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Eyck Jentzsch
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f626ee2684
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fixes privilege wrapper for M/U to cope with 64bit
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2023-04-05 15:38:25 +02:00 |
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Eyck Jentzsch
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a8a2782329
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adds changes from latest CoreDSL description
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2023-04-04 16:10:12 +02:00 |
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Eyck Jentzsch
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98dd329833
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fixes CSR access rights
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2023-04-04 09:23:08 +02:00 |
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Eyck Jentzsch
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6213445bc4
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fixes 64bit behavior of CSR regs
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2023-03-27 12:04:43 +02:00 |
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Eyck Jentzsch
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c5465bf9e2
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fixes according to fixed generator
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2023-03-26 14:44:15 +02:00 |
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Eyck Jentzsch
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2e4faa4d50
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fixes mstatus mask
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2023-03-25 09:14:56 +01:00 |
|
Eyck Jentzsch
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8e1951f298
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adds 64bit mstatus
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2023-03-23 07:47:21 +01:00 |
|
Eyck Jentzsch
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7efa924510
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fixes m/uintstatus read
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2023-03-17 10:51:39 +01:00 |
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Eyck Jentzsch
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febbc4fff0
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fixes m/uintstatus read
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2023-03-17 10:23:05 +01:00 |
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Eyck Jentzsch
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39b2788b7e
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implements and fixes CLIC CSR behavior
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2023-03-17 09:09:09 +01:00 |
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Eyck Jentzsch
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a943dd3bdf
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fixes wrong array size which led to unintended CSR definitions
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2023-03-15 14:16:08 +01:00 |
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Eyck Jentzsch
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fedbff5971
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fixes xcause and u-mode clic CSRs
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2023-03-15 12:27:39 +01:00 |
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Eyck Jentzsch
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c2758e8321
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removes mscratchcsw from CLIC feature
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2023-03-15 09:07:00 +01:00 |
|
Eyck Jentzsch
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8be5fe71df
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fixes template name typo
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2023-03-12 07:42:09 +01:00 |
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Eyck Jentzsch
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3f7ce41b9d
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fixes CLIC mtvt register behavior
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2023-03-11 14:03:03 +01:00 |
|
Eyck Jentzsch
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ad1cbedf00
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adds back missing max irq functions
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2023-03-11 12:47:10 +01:00 |