DBT-RISE
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DBT-RISE-TGC
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43 Commits

Author SHA1 Message Date
Eyck Jentzsch 477c530847 extend debug mode handling 2022-04-13 11:41:01 +02:00
Eyck Jentzsch 00d2d06cbd adapt to privileged spec 2022-03-31 20:33:12 +02:00
Eyck Jentzsch 0aea1d0177 remove mcounteren in M-mode only wrapper 2022-03-27 17:21:46 +02:00
Eyck Jentzsch 6ea7721961 add TCM 2022-03-27 15:38:18 +02:00
Eyck Jentzsch 9dfca612b7 add hardware loop CSR access 2022-03-25 11:33:44 +01:00
Eyck Jentzsch b8fa5fbbda adapt to extended instrumentation interface 2022-02-09 21:01:17 +01:00
Eyck Jentzsch 09b0f0d0c8 fix cycle estimation plugin 2022-02-01 21:14:50 +01:00
Eyck-Alexander Jentzsch ecc6091d1e cleans up source code to remove clang compiler warnings 2022-01-19 08:01:15 +01:00
Eyck Jentzsch dd4c19a15c add option to configure number of irq 2021-12-01 12:56:36 +01:00
Eyck Jentzsch d47375a70e fix ebreak CSR update 2021-11-13 12:47:23 +01:00
Eyck Jentzsch 2d7973520b fix mip handling 2021-11-09 19:47:34 +01:00
Eyck Jentzsch c42e336509 fix proper debug mode handling (#267 & #268) 2021-11-07 17:48:44 +01:00
Eyck Jentzsch 49d09a05d7 fix access rights to debug CSR register (#268) 2021-11-07 16:45:10 +01:00
Eyck Jentzsch 039746112b fix exception behavior 2021-11-02 15:10:20 +01:00
Eyck Jentzsch ac6d7ea5d4 add debug feature to platform 2021-11-02 11:13:29 +01:00
Eyck Jentzsch ee6e1d4092 Merge remote-tracking branch 'origin/msvc_compat' into develop 
Conflicts:
	src/sysc/core_complex.cpp
 2021-10-11 09:42:40 +02:00
Eyck Jentzsch f0ada1ba8c add MSVC 16 compatibility 2021-10-10 19:06:41 +02:00
Eyck Jentzsch d78fcc48e5 use marchid in platform 2021-09-30 19:27:03 +02:00
Eyck Jentzsch 174259155d add support for non-compressed ISA 2021-09-23 21:09:52 +02:00
Eyck Jentzsch 65b4db5eca remove mcounteren in M-mode only platform 2021-09-18 11:40:00 +02:00
Eyck Jentzsch 09b01af3fa fix find_package use and debug access alignment check 2021-08-26 22:10:27 +02:00
Eyck Jentzsch 2f05083cf0 fix elf loader and pmp check for debug accesses 2021-08-19 10:50:25 +02:00
Eyck Jentzsch d95846a849 fix trap handling if illegal fetch (PMP) and U-mode CSRs 2021-08-01 17:23:22 +02:00
Eyck Jentzsch af887c286f fix for #2 2021-07-28 09:09:08 +02:00
Eyck Jentzsch c592a26346 fix mepc mask 2021-07-09 13:01:22 +02:00
Eyck Jentzsch e68918c2e8 fix instruction decode 2021-07-09 07:37:12 +02:00
Eyck Jentzsch 473f8a5a17 fix privilege behavior 2021-07-07 11:30:00 +02:00
Eyck Jentzsch 2f4b5bd9b2 fix detailed behavior of TGC_C 2021-07-06 21:19:36 +02:00
Eyck Jentzsch 23b9741adf refine and fix TGC_C iss to becoem compliant 2021-06-29 11:51:30 +02:00
Eyck Jentzsch 5d8da08ce5 fix linker issue 
the root cuase of the issue is the template paramter deduction which led
to the wrong template parameter.
 2021-06-26 14:30:36 +02:00
Eyck Jentzsch a35974c9f5 make cpu type in core_complex configurable 2021-05-16 15:06:42 +02:00
Stanislaw Kaushanski ef02dba8c5 add read misa callback 2021-04-09 11:20:51 +02:00
Stanislaw Kaushanski 7009943106 fix wait for interrupt. Adapt for new SCC structure 2021-04-07 17:42:08 +02:00
Eyck Jentzsch f4ec21007b fix signedness issues 2021-03-11 16:12:28 +00:00
Eyck Jentzsch c251fe15d5 fix desscriptions to conform to ISA spec version 20191213 and TGF-C 2021-03-07 10:51:00 +00:00
Eyck Jentzsch dae8acb8a3 checkpoint before refactor 2021-03-06 07:17:42 +00:00
Eyck Jentzsch 4aa26b85a0 adapt to change in SCC 2021-03-01 06:36:27 +00:00
Eyck Jentzsch 9534d58d01 regenerated sources and and add opcode enum to headers 
Conflicts:
	gen_input/CoreDSL-Instruction-Set-Description
 2021-03-01 06:26:33 +00:00
Stanislaw Kaushanski f3d578f050 Remove 64bit support 2020-09-07 14:30:19 +02:00
Stanislaw Kaushanski 293c396a0d update core wrapper: remove virtual memory support 2020-09-07 13:29:45 +02:00
Stanislaw Kaushanski 6f3963a473 Strip down privileged modes. Only machine mode is supported 2020-09-07 11:54:45 +02:00
Stanislaw Kaushanski 969b408288 Implement MHARTID register 2020-09-04 15:37:21 +02:00
Stanislaw Kaushanski 9754e3953f Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores 2020-08-24 15:01:54 +02:00