Commit Graph

376 Commits

Author SHA1 Message Date
051dd5e2d3 updates templates for decoder in seperate class, adds again generated templates 2024-07-23 13:46:10 +02:00
e3942be776 Introduces decoder in a seperate class 2024-07-23 13:08:53 +02:00
6ee484a771 moves instruction decoder into own class 2024-07-23 11:30:33 +02:00
60808c8649 corrects template since util fns are no longer vm_base members 2024-07-23 11:29:56 +02:00
0432803d82 updates templates and vm impls for better LAST_BRANCH handling 2024-07-22 09:04:17 +02:00
d42d2ce533 corrects illegal instruction for llvm 2024-07-18 14:04:23 +02:00
236d12d7f5 integrates gen_bool for Conditions (was truncation) into llvm 2024-07-18 13:30:42 +02:00
e1b6cab890 removes setting of NEXT_PC to max when trapping in llvm and asmjit, adds default disass to llvm 2024-07-18 12:02:40 +02:00
8361f88718 removes setting of NEXT_PC to max if trap 2024-07-18 11:37:53 +02:00
2ec7ea4b41 removes leftover gen_sync in asmjit 2024-07-17 22:39:12 +02:00
b24965d321 corrects gen_sync update order, improves illegal instruction 2024-07-17 20:52:01 +02:00
244bf6d2f2 corrects gen_sync before trap check, improves illegal_instruction 2024-07-17 20:25:49 +02:00
1a4465a371 changes template: adds correct illegal instruction, reorders gen_sync to allow correct instr id eve when trapping, adds newly generated vm 2024-07-17 19:59:01 +02:00
11a30caae8 integrates generator changes to canPrecompute 2024-07-17 15:14:13 +02:00
ac1a26a10c integrates new tval changes into llvm 2024-07-17 14:17:02 +02:00
7a199e122d integrates new tval changes into asmjit 2024-07-17 09:42:12 +02:00
d8c3d2e19c integrates new tval changes into tcc 2024-07-16 17:35:23 +02:00
375755999a integrates new tval changes 2024-07-16 15:32:35 +02:00
9996fd4833 change cache line size to 64 2024-07-11 14:03:58 +02:00
149b3136d2 updates generated files 2024-07-10 12:55:36 +02:00
ac8f8b0539 updates vms with fixed Zc in tgc5c.core_desc 2024-07-10 12:51:59 +02:00
b2cbf90d0b updates generated files 2024-07-10 12:51:59 +02:00
373145478e updats file because of generator changes 2024-07-10 12:51:59 +02:00
55b0cea94f changes vm_base util API 2024-07-10 12:51:59 +02:00
5b17599aa2 allows usage of std::variants 2024-07-10 12:51:59 +02:00
4cfb15c7cd Asmjit and interp working 2024-07-10 12:51:31 +02:00
63da7f8d57 applies clang-format 2024-07-09 13:57:11 +02:00
fb4012fbd1 moves likely annotation 2024-07-09 13:52:10 +02:00
24449f1c0f fixes some elf load issue 2024-07-05 12:18:36 +02:00
fd303c8343 fixes asmjit deprecation warning 2024-07-05 07:51:37 +02:00
346b177a87 extends finishing conditions 2024-07-05 05:52:29 +02:00
d4ec131fa7 change COUNT_LIMIT to ICOUNT_LIMIT 2024-07-04 10:46:24 +02:00
48370a4555 asmjit passes backend with new CoreDSL 2024-06-22 09:28:26 +02:00
8460f4ab7f updates templates to re-enable interactive debugging of generator 2024-06-21 10:46:11 +02:00
3fd51cc68c fixes templates 2024-06-14 19:54:33 +02:00
551822916c applies clang-format 2024-06-14 17:43:12 +02:00
e2da306eee fixes semihosting cb registration 2024-05-31 10:45:28 +02:00
41051f8f34 fixes tohost handling 2024-05-31 10:43:38 +02:00
gabriel
a6c48ceaac Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2024-05-31 09:42:13 +02:00
gabriel
ed793471bb adding semhosting 2024-05-31 07:27:47 +02:00
58fb815f32 fixes gen_raise in tcc 2024-05-20 10:34:23 +02:00
3cc8bd0854 adds reformat bc of verilog literals 2024-05-18 21:01:05 +02:00
a27850f841 adds verilog literal and illegal_instr to asmjit 2024-05-18 21:00:21 +02:00
fb330cddea llvm passes act 2024-05-18 19:33:57 +02:00
b76c5bf0d6 adds flush to fence_i 2024-05-11 15:25:49 +02:00
001c6349f7 removes tcc sim stop when writing to tohost 2024-05-11 15:16:46 +02:00
ee6a11dae6 fixes typo 2024-05-09 20:54:30 +02:00
2e27b025cc improves dump-ir comments 2024-05-09 13:47:36 +02:00
f0a004be9d adds information for debugging 2024-05-09 13:42:16 +02:00
3422c7cd5c optimizes writebacks 2024-05-08 15:18:38 +02:00
ad79a28705 wip checkin 2024-04-30 19:21:27 +02:00
9fdbc3ff38 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2024-04-26 17:07:00 +02:00
602bc6e06a checking: working 2024-04-26 17:06:26 +02:00
6cb76fc256 updates tgc5c according to latest CoreDSL 2024-04-16 13:09:14 +02:00
fbcd389580 fix log macro 2024-04-15 13:03:47 +02:00
b25b7848c6 fix formatting 2024-03-19 11:47:12 +01:00
6c986d38d8 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2024-03-19 11:02:17 +01:00
a1ebd83d2a adds riscv_hart_common and signature output 2024-03-19 11:02:03 +01:00
8aed551813 Add a new LOG macro in SCC to avoid conflicts with other libraries. 2024-03-14 09:43:08 +01:00
1e6a0086e9 adds disass functionality 2024-03-07 13:58:08 +01:00
119d4a8b43 adds generation if IMEM space 2024-02-21 07:08:24 +01:00
9841b16122 fixes clang-format failures 2024-01-12 11:49:11 +01:00
fe2d5cb2f9 adds semihosting to all backends 2024-01-10 11:47:12 +01:00
3ff59ba45d small refactor, adds baisc functionality 2024-01-10 10:15:05 +01:00
075e04249a adds semihosting skeleton 2024-01-09 12:50:41 +01:00
207f778ee6 adds initial semihosting host capabilities 2024-01-08 17:17:59 +01:00
bc4ea30815 apply clang-format 10 fixes 2023-12-01 14:50:54 +01:00
e921201f7b applies clang-format fixes 2023-11-30 11:51:49 +01:00
e6aa6e5842 adds handling of variable number of clic interrupts 2023-11-22 11:47:31 +01:00
4418fa7e4f fixes include path of asmjit helpers 2023-11-20 16:07:01 +01:00
0eb1db0e7e adds functionality, adds working asmjit 2023-11-20 11:45:52 +01:00
e48597b2b7 adds formatting fixes 2023-11-05 17:19:43 +01:00
b3f40f9b15 build fixes due to dependencies 2023-11-04 13:05:30 +01:00
759061b569 applies clang-format changes 2023-10-29 17:06:56 +01:00
2bea95c1a7 adds option to disable DMI use 2023-10-28 17:06:50 +02:00
7001b693ae updates templates for SystemC registration 2023-10-27 22:14:11 +02:00
e6f11081eb fixes quantum and quantum break handling 2023-10-27 21:12:49 +02:00
09db0cd35d fixes LLVM backend registration for SystemC 2023-10-26 06:50:54 +02:00
980c8031c3 fixes tohost behavior of SC wrapper and cycle-estimate plugin 2023-10-25 20:37:10 +02:00
b86d7a517d adds dynamic cycle estimation 2023-10-25 17:13:52 +02:00
b7478965ab adds asmjit backend registration for SystemC 2023-10-23 10:18:25 +02:00
bf4a6deb86 fixes dump-ir handling 2023-10-22 23:19:09 +02:00
ffe730219d merge commit 2023-10-22 15:13:25 +02:00
60c926c921 adds asmjit 2023-10-22 15:11:20 +02:00
4c3a7386b0 updates generated files 2023-10-22 08:51:08 +02:00
74ff1d455a fixes install routine 2023-10-20 20:38:59 +02:00
ae4322c1b9 „src/main.cpp“ ändern 2023-10-15 09:03:31 +02:00
9180ad1f9c debugger memory accesses should never lead to traps 2023-10-06 21:39:48 +02:00
ee6a068b06 streamlines backends and reporting 2023-10-01 18:33:14 +02:00
b97853ff5a update plugins to read YAML file 2023-09-30 22:10:24 +02:00
b7f023756e fixes constructor calls of derived riscv_hart classes 2023-09-27 07:51:49 +02:00
2095ac985b fixes forgotten removal of pctrace in core_complex 2023-09-27 06:19:59 +02:00
3fb8fe765a aligns riscv_hart_msu_vp with riscv_hart_m_p 2023-09-26 20:17:26 +02:00
5fd226b670 moves pctrace 2023-09-25 09:44:51 +02:00
417076f8e6 stops jit block creation in case of ECALL and EBREAK 2023-09-23 11:30:58 +02:00
70839bbbf2 changes templates for correct plugin callback in case of trap 2023-09-23 10:35:21 +02:00
8db0cc5d05 removes clutter 2023-09-23 10:34:58 +02:00
212fb1c8ff adds tracing functionality 2023-09-22 12:40:35 +02:00
f74f98f361 improves readability 2023-09-22 12:40:12 +02:00
633c0d21a0 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2023-09-20 15:17:43 +02:00