DBT-RISE-TGC/incl/iss/arch/riscv_hart_m_p.h

1083 lines
45 KiB
C
Raw Normal View History

2017-08-27 12:10:38 +02:00
/*******************************************************************************
* Copyright (C) 2021 MINRES Technologies GmbH
2017-08-27 12:10:38 +02:00
* All rights reserved.
2017-09-22 11:23:23 +02:00
*
2017-08-27 12:10:38 +02:00
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
2017-09-22 11:23:23 +02:00
*
2017-08-27 12:10:38 +02:00
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
2017-09-22 11:23:23 +02:00
*
2017-08-27 12:10:38 +02:00
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
2017-09-22 11:23:23 +02:00
*
2017-08-27 12:10:38 +02:00
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
2017-09-22 11:23:23 +02:00
*
2017-08-27 12:10:38 +02:00
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
2017-09-22 11:23:23 +02:00
*
2017-08-27 12:10:38 +02:00
* Contributors:
2017-11-27 00:14:41 +01:00
* eyck@minres.com - initial implementation
2017-08-27 12:10:38 +02:00
******************************************************************************/
#ifndef _RISCV_HART_M_P_H
#define _RISCV_HART_M_P_H
2017-08-27 12:10:38 +02:00
#include "riscv_hart_common.h"
#include "iss/arch/traits.h"
2018-11-08 13:31:28 +01:00
#include "iss/instrumentation_if.h"
#include "iss/log_categories.h"
#include "iss/vm_if.h"
2019-07-14 16:51:14 +02:00
#ifndef FMT_HEADER_ONLY
2019-04-11 07:40:02 +02:00
#define FMT_HEADER_ONLY
2019-07-14 16:51:14 +02:00
#endif
2018-11-08 13:31:28 +01:00
#include <array>
2017-08-27 12:10:38 +02:00
#include <elfio/elfio.hpp>
2020-09-04 15:37:21 +02:00
#include <fmt/format.h>
2017-09-22 11:23:23 +02:00
#include <iomanip>
2017-08-27 12:10:38 +02:00
#include <sstream>
2018-11-08 13:31:28 +01:00
#include <type_traits>
#include <unordered_map>
2021-03-06 08:17:42 +01:00
#include <functional>
2018-11-08 13:31:28 +01:00
#include <util/bit_field.h>
2017-09-22 11:23:23 +02:00
#include <util/ities.h>
#include <util/sparse_array.h>
2017-08-27 12:10:38 +02:00
2018-11-08 13:31:28 +01:00
#if defined(__GNUC__)
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)
#else
#define likely(x) x
#define unlikely(x) x
#endif
2017-08-27 12:10:38 +02:00
namespace iss {
namespace arch {
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT=FEAT_NONE> class riscv_hart_m_p : public BASE {
protected:
const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
const std::array<const char *, 16> trap_str = {{""
"Instruction address misaligned", // 0
"Instruction access fault", // 1
"Illegal instruction", // 2
"Breakpoint", // 3
"Load address misaligned", // 4
"Load access fault", // 5
"Store/AMO address misaligned", // 6
"Store/AMO access fault", // 7
"Environment call from U-mode", // 8
"Environment call from S-mode", // 9
"Reserved", // a
"Environment call from M-mode", // b
"Instruction page fault", // c
"Load page fault", // d
"Reserved", // e
"Store/AMO page fault"}};
const std::array<const char *, 12> irq_str = {
{"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
public:
using core = BASE;
2021-11-02 11:13:29 +01:00
using this_class = riscv_hart_m_p<BASE, FEAT>;
using phys_addr_t = typename core::phys_addr_t;
using reg_t = typename core::reg_t;
using addr_t = typename core::addr_t;
2017-08-27 12:10:38 +02:00
2017-09-22 11:23:23 +02:00
using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
2017-08-27 12:10:38 +02:00
using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
// primary template
2018-11-08 13:31:28 +01:00
template <class T, class Enable = void> struct hart_state {};
// specialization 32bit
2018-11-08 13:31:28 +01:00
template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
2017-10-12 22:41:37 +02:00
public:
BEGIN_BF_DECL(mstatus_t, T);
// SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
BF_FIELD(SD, 31, 1);
// Trap SRET
BF_FIELD(TSR, 22, 1);
// Timeout Wait
BF_FIELD(TW, 21, 1);
// Trap Virtual Memory
BF_FIELD(TVM, 20, 1);
// Make eXecutable Readable
BF_FIELD(MXR, 19, 1);
// permit Supervisor User Memory access
BF_FIELD(SUM, 18, 1);
// Modify PRiVilege
BF_FIELD(MPRV, 17, 1);
// status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
BF_FIELD(XS, 15, 2);
// floating-point unit status Off/Initial/Clean/Dirty
BF_FIELD(FS, 13, 2);
// machine previous privilege
BF_FIELD(MPP, 11, 2);
// supervisor previous privilege
BF_FIELD(SPP, 8, 1);
// previous machine interrupt-enable
BF_FIELD(MPIE, 7, 1);
// previous supervisor interrupt-enable
BF_FIELD(SPIE, 5, 1);
// previous user interrupt-enable
BF_FIELD(UPIE, 4, 1);
// machine interrupt-enable
BF_FIELD(MIE, 3, 1);
// supervisor interrupt-enable
BF_FIELD(SIE, 1, 1);
// user interrupt-enable
BF_FIELD(UIE, 0, 1);
END_BF_DECL();
mstatus_t mstatus;
2021-07-09 07:37:12 +02:00
static const reg_t mstatus_reset_val = 0x1800;
void write_mstatus(T val) {
2021-07-09 07:37:12 +02:00
auto mask = get_mask() &0xff; // MPP is hardcode as 0x3
2021-03-01 07:36:27 +01:00
auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
2018-11-08 13:31:28 +01:00
mstatus = new_val;
}
static constexpr uint32_t get_mask() {
2021-07-06 21:19:36 +02:00
//return 0x807ff988UL; // 0b1000 0000 0111 1111 1111 1000 1000 1000 // only machine mode is supported
// +-SD
// | +-TSR
// | |+-TW
// | ||+-TVM
// | |||+-MXR
// | ||||+-SUM
// | |||||+-MPRV
// | |||||| +-XS
// | |||||| | +-FS
// | |||||| | | +-MPP
// | |||||| | | | +-SPP
// | |||||| | | | |+-MPIE
// | ||||||/|/|/| || +-MIE
return 0b00000000000000000001100010001000;
}
};
using hart_state_type = hart_state<reg_t>;
2017-08-27 12:10:38 +02:00
constexpr reg_t get_irq_mask() {
2021-07-06 21:19:36 +02:00
return 0b100010001000; // only machine mode is supported
2017-08-27 12:10:38 +02:00
}
2021-07-07 11:30:00 +02:00
constexpr reg_t get_pc_mask() {
return traits<BASE>::MISA_VAL&0b0100?~1:~3;
}
riscv_hart_m_p();
virtual ~riscv_hart_m_p() = default;
2017-08-27 12:10:38 +02:00
void reset(uint64_t address) override;
2018-11-08 13:31:28 +01:00
std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
2017-08-27 12:10:38 +02:00
iss::status read(const address_type type, const access_type access, const uint32_t space,
const uint64_t addr, const unsigned length, uint8_t *const data) override;
iss::status write(const address_type type, const access_type access, const uint32_t space,
const uint64_t addr, const unsigned length, const uint8_t *const data) override;
2017-08-27 12:10:38 +02:00
virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data, fault_data); }
virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
2017-08-27 12:10:38 +02:00
virtual uint64_t leave_trap(uint64_t flags) override;
2020-09-04 15:37:21 +02:00
const reg_t& get_mhartid() const { return mhartid_reg; }
void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
void disass_output(uint64_t pc, const std::string instr) override {
CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [s:0x{:x};c:{}]",
pc, instr, (reg_t)state.mstatus, this->reg.icount);
2017-08-27 12:10:38 +02:00
};
2018-11-08 13:31:28 +01:00
iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
2021-03-06 08:17:42 +01:00
void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
mem_read_cb = memReadCb;
}
void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
mem_write_cb = memWriteCb;
}
void set_csr(unsigned addr, reg_t val){
csr[addr & csr.page_addr_mask] = val;
}
2021-12-01 12:56:36 +01:00
void set_irq_num(unsigned i) {
mcause_max_irq=1<<util::ilog2(i);
}
2017-08-27 12:10:38 +02:00
protected:
2018-11-08 13:31:28 +01:00
struct riscv_instrumentation_if : public iss::instrumentation_if {
2021-11-02 11:13:29 +01:00
riscv_instrumentation_if(riscv_hart_m_p<BASE, FEAT> &arch)
2018-11-08 13:31:28 +01:00
: arch(arch) {}
/**
* get the name of this architecture
*
* @return the name of this architecture
*/
2018-11-08 13:31:28 +01:00
const std::string core_type_name() const override { return traits<BASE>::core_type; }
uint64_t get_pc() override { return arch.get_pc(); };
uint64_t get_next_pc() override { return arch.get_next_pc(); };
void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
2021-11-02 11:13:29 +01:00
riscv_hart_m_p<BASE, FEAT> &arch;
};
friend struct riscv_instrumentation_if;
2018-11-08 13:31:28 +01:00
addr_t get_pc() { return this->reg.PC; }
addr_t get_next_pc() { return this->reg.NEXT_PC; }
2017-09-22 11:23:23 +02:00
virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
2017-08-27 12:10:38 +02:00
2021-11-02 11:13:29 +01:00
iss::status read_clic(uint64_t addr, unsigned length, uint8_t *const data);
iss::status write_clic(uint64_t addr, unsigned length, const uint8_t *const data);
2017-09-22 11:23:23 +02:00
virtual iss::status read_csr(unsigned addr, reg_t &val);
virtual iss::status write_csr(unsigned addr, reg_t val);
2017-08-27 12:10:38 +02:00
hart_state_type state;
int64_t cycle_offset{0};
uint64_t mcycle_csr{0};
int64_t instret_offset{0};
uint64_t minstret_csr{0};
reg_t fault_data;
2017-08-27 12:10:38 +02:00
uint64_t tohost = tohost_dflt;
uint64_t fromhost = fromhost_dflt;
unsigned to_host_wr_cnt = 0;
riscv_instrumentation_if instr_if;
2017-08-27 12:10:38 +02:00
2017-09-22 11:23:23 +02:00
using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
2017-08-27 12:10:38 +02:00
using csr_page_type = typename csr_type::page_type;
mem_type mem;
csr_type csr;
std::stringstream uart_buf;
std::unordered_map<reg_t, uint64_t> ptw;
std::unordered_map<uint64_t, uint8_t> atomic_reservation;
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
2021-11-02 11:13:29 +01:00
uint8_t clic_cfg_reg{0};
uint32_t clic_info_reg{0};
std::array<uint32_t, 32> clic_inttrig_reg;
union clic_int_reg_t {
struct{
uint8_t ip;
uint8_t ie;
uint8_t attr;
uint8_t ctl;
};
uint32_t raw;
};
std::vector<clic_int_reg_t> clic_int_reg;
2017-08-27 12:10:38 +02:00
2021-11-02 11:13:29 +01:00
iss::status read_csr_reg(unsigned addr, reg_t &val);
iss::status write_csr_reg(unsigned addr, reg_t val);
iss::status read_null(unsigned addr, reg_t &val);
iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;}
2017-09-22 11:23:23 +02:00
iss::status read_cycle(unsigned addr, reg_t &val);
iss::status write_cycle(unsigned addr, reg_t val);
iss::status read_instret(unsigned addr, reg_t &val);
iss::status write_instret(unsigned addr, reg_t val);
iss::status read_tvec(unsigned addr, reg_t &val);
2017-10-25 22:05:31 +02:00
iss::status read_time(unsigned addr, reg_t &val);
2017-09-22 11:23:23 +02:00
iss::status read_status(unsigned addr, reg_t &val);
2017-08-27 12:10:38 +02:00
iss::status write_status(unsigned addr, reg_t val);
2021-07-28 09:09:08 +02:00
iss::status write_cause(unsigned addr, reg_t val);
2017-09-22 11:23:23 +02:00
iss::status read_ie(unsigned addr, reg_t &val);
2017-08-27 12:10:38 +02:00
iss::status write_ie(unsigned addr, reg_t val);
2017-09-22 11:23:23 +02:00
iss::status read_ip(unsigned addr, reg_t &val);
2017-08-27 12:10:38 +02:00
iss::status write_ip(unsigned addr, reg_t val);
2020-09-04 15:37:21 +02:00
iss::status read_hartid(unsigned addr, reg_t &val);
iss::status write_epc(unsigned addr, reg_t val);
iss::status write_intstatus(unsigned addr, reg_t val);
iss::status write_intthresh(unsigned addr, reg_t val);
iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
iss::status read_dcsr_reg(unsigned addr, reg_t &val);
iss::status write_dcsr_reg(unsigned addr, reg_t val);
iss::status read_dpc_reg(unsigned addr, reg_t &val);
iss::status write_dpc_reg(unsigned addr, reg_t val);
2021-03-11 17:12:28 +01:00
reg_t mhartid_reg{0x0};
2021-03-06 08:17:42 +01:00
std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
2018-11-08 13:31:28 +01:00
2017-08-27 12:10:38 +02:00
void check_interrupt();
2021-11-02 11:13:29 +01:00
bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
uint64_t clic_base_addr{0};
unsigned clic_num_irq{0};
unsigned clic_num_trigger{0};
unsigned mcause_max_irq{16};
inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
2017-08-27 12:10:38 +02:00
};
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT>
riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
2018-11-08 13:31:28 +01:00
: state()
, instr_if(*this) {
2021-07-06 21:19:36 +02:00
// reset values
2021-04-09 11:20:51 +02:00
csr[misa] = traits<BASE>::MISA_VAL;
2021-07-06 21:19:36 +02:00
csr[mvendorid] = 0x669;
2021-09-30 19:27:03 +02:00
csr[marchid] = traits<BASE>::MARCHID_VAL;
2021-07-06 21:19:36 +02:00
csr[mimpid] = 1;
2021-11-02 11:13:29 +01:00
csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file
2021-07-06 21:19:36 +02:00
2017-08-27 12:10:38 +02:00
uart_buf.str("");
for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
csr_rd_cb[addr] = &this_class::read_null;
2021-11-02 11:13:29 +01:00
csr_wr_cb[addr] = &this_class::write_csr_reg;
}
for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
csr_rd_cb[addr] = &this_class::read_null;
2021-11-02 11:13:29 +01:00
csr_wr_cb[addr] = &this_class::write_csr_reg;
}
for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){
csr_rd_cb[addr] = &this_class::read_null;
2021-11-02 11:13:29 +01:00
csr_wr_cb[addr] = &this_class::write_csr_reg;
}
2021-07-07 11:30:00 +02:00
for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
csr_rd_cb[addr] = &this_class::read_null;
}
2021-07-07 11:30:00 +02:00
for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
csr_rd_cb[addr] = &this_class::read_null;
2021-11-02 11:13:29 +01:00
//csr_wr_cb[addr] = &this_class::write_csr_reg;
}
// common regs
2021-07-06 21:19:36 +02:00
const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
for(auto addr: addrs) {
2021-11-02 11:13:29 +01:00
csr_rd_cb[addr] = &this_class::read_csr_reg;
csr_wr_cb[addr] = &this_class::write_csr_reg;
}
// special handling & overrides
csr_rd_cb[time] = &this_class::read_time;
csr_rd_cb[timeh] = &this_class::read_time;
2021-07-07 11:30:00 +02:00
csr_rd_cb[cycle] = &this_class::read_cycle;
csr_rd_cb[cycleh] = &this_class::read_cycle;
csr_rd_cb[instret] = &this_class::read_instret;
csr_rd_cb[instreth] = &this_class::read_instret;
csr_rd_cb[mcycle] = &this_class::read_cycle;
csr_wr_cb[mcycle] = &this_class::write_cycle;
csr_rd_cb[mcycleh] = &this_class::read_cycle;
csr_wr_cb[mcycleh] = &this_class::write_cycle;
csr_rd_cb[minstret] = &this_class::read_instret;
csr_wr_cb[minstret] = &this_class::write_instret;
csr_rd_cb[minstreth] = &this_class::read_instret;
csr_wr_cb[minstreth] = &this_class::write_instret;
csr_rd_cb[mstatus] = &this_class::read_status;
csr_wr_cb[mstatus] = &this_class::write_status;
2021-07-28 09:09:08 +02:00
csr_wr_cb[mcause] = &this_class::write_cause;
csr_rd_cb[mtvec] = &this_class::read_tvec;
csr_wr_cb[mepc] = &this_class::write_epc;
csr_rd_cb[mip] = &this_class::read_ip;
csr_wr_cb[mip] = &this_class::write_ip;
csr_rd_cb[mie] = &this_class::read_ie;
csr_wr_cb[mie] = &this_class::write_ie;
csr_rd_cb[mhartid] = &this_class::read_hartid;
csr_wr_cb[misa] = &this_class::write_null;
2021-07-06 21:19:36 +02:00
csr_wr_cb[mvendorid] = &this_class::write_null;
csr_wr_cb[marchid] = &this_class::write_null;
csr_wr_cb[mimpid] = &this_class::write_null;
2021-11-02 11:13:29 +01:00
if(FEAT & FEAT_DEBUG){
csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg;
csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg;
csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg;
csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg;
csr_wr_cb[dpc] = &this_class::write_dpc_reg;
csr_rd_cb[dpc] = &this_class::read_dpc_reg;
csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
2021-11-02 11:13:29 +01:00
}
2017-08-27 12:10:38 +02:00
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT>::load_file(std::string name, int type) {
2017-09-22 11:23:23 +02:00
FILE *fp = fopen(name.c_str(), "r");
if (fp) {
2018-11-08 13:31:28 +01:00
std::array<char, 5> buf;
auto n = fread(buf.data(), 1, 4, fp);
2017-09-22 11:23:23 +02:00
if (n != 4) throw std::runtime_error("input file has insufficient size");
buf[4] = 0;
2018-11-08 13:31:28 +01:00
if (strcmp(buf.data() + 1, "ELF") == 0) {
2017-08-27 12:10:38 +02:00
fclose(fp);
2017-09-22 11:23:23 +02:00
// Create elfio reader
2017-08-27 12:10:38 +02:00
ELFIO::elfio reader;
// Load ELF data
2017-09-22 11:23:23 +02:00
if (!reader.load(name)) throw std::runtime_error("could not process elf file");
2017-08-27 12:10:38 +02:00
// check elf properties
2018-11-08 13:31:28 +01:00
if (reader.get_class() != ELFCLASS32)
if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
2017-09-22 11:23:23 +02:00
if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
2018-11-08 13:31:28 +01:00
if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
auto entry = reader.get_entry();
2017-09-22 11:23:23 +02:00
for (const auto pseg : reader.segments) {
const auto fsize = pseg->get_file_size(); // 0x42c/0x0
const auto seg_data = pseg->get_data();
if (fsize > 0) {
auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE,
traits<BASE>::MEM, pseg->get_physical_address(),
fsize, reinterpret_cast<const uint8_t *const>(seg_data));
2017-10-04 10:31:11 +02:00
if (res != iss::Ok)
2021-10-10 19:06:41 +02:00
LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
2017-10-04 10:31:11 +02:00
<< pseg->get_physical_address();
2017-08-27 12:10:38 +02:00
}
}
for(const auto sec : reader.sections) {
if(sec->get_name() == ".symtab") {
if ( SHT_SYMTAB == sec->get_type() ||
SHT_DYNSYM == sec->get_type() ) {
ELFIO::symbol_section_accessor symbols( reader, sec );
auto sym_no = symbols.get_symbols_num();
std::string name;
ELFIO::Elf64_Addr value = 0;
ELFIO::Elf_Xword size = 0;
unsigned char bind = 0;
unsigned char type = 0;
ELFIO::Elf_Half section = 0;
unsigned char other = 0;
for ( auto i = 0U; i < sym_no; ++i ) {
symbols.get_symbol( i, name, value, size, bind, type, section, other );
if(name=="tohost") {
tohost = value;
} else if(name=="fromhost") {
fromhost = value;
}
}
}
} else if (sec->get_name() == ".tohost") {
2017-09-22 11:23:23 +02:00
tohost = sec->get_address();
fromhost = tohost + 0x40;
2017-08-27 12:10:38 +02:00
}
}
return std::make_pair(entry, true);
2017-08-27 12:10:38 +02:00
}
throw std::runtime_error("memory load file is not a valid elf file");
2017-08-27 12:10:38 +02:00
}
throw std::runtime_error("memory load file not found");
2017-08-27 12:10:38 +02:00
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space,
const uint64_t addr, const unsigned length, uint8_t *const data) {
2017-08-27 12:10:38 +02:00
#ifndef NDEBUG
if (access && iss::access_type::DEBUG) {
2020-05-29 08:52:55 +02:00
LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
} else if(access && iss::access_type::FETCH){
LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr;
2017-08-27 12:10:38 +02:00
} else {
2020-01-12 18:19:48 +01:00
LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr;
2020-05-29 08:52:55 +02:00
}
2017-08-27 12:10:38 +02:00
#endif
try {
switch (space) {
case traits<BASE>::MEM: {
if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
fault_data = addr;
if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
this->reg.trap_state = (1 << 31); // issue trap 0
return iss::Err;
2017-08-27 12:10:38 +02:00
}
try {
2021-07-06 21:19:36 +02:00
auto alignment = access == iss::access_type::FETCH? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
if(alignment>1 && (addr&(alignment-1))){
this->reg.trap_state = 1<<31 | 4<<16;
fault_data=addr;
return iss::Err;
}
auto res = type==iss::address_type::PHYSICAL?
read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
2021-07-06 21:19:36 +02:00
if (unlikely(res != iss::Ok)){
this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
fault_data=addr;
}
return res;
} catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id;
2021-07-06 21:19:36 +02:00
fault_data=ta.addr;
2017-08-27 12:10:38 +02:00
return iss::Err;
}
} break;
case traits<BASE>::CSR: {
if (length != sizeof(reg_t)) return iss::Err;
return read_csr(addr, *reinterpret_cast<reg_t *const>(data));
} break;
case traits<BASE>::FENCE: {
if ((addr + length) > mem.size()) return iss::Err;
return iss::Ok;
} break;
case traits<BASE>::RES: {
auto it = atomic_reservation.find(addr);
if (it != atomic_reservation.end() && it->second != 0) {
memset(data, 0xff, length);
atomic_reservation.erase(addr);
} else
memset(data, 0, length);
} break;
default:
return iss::Err; // assert("Not supported");
2017-08-27 12:10:38 +02:00
}
return iss::Ok;
} catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id;
2021-07-06 21:19:36 +02:00
fault_data=ta.addr;
return iss::Err;
2017-08-27 12:10:38 +02:00
}
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space,
const uint64_t addr, const unsigned length, const uint8_t *const data) {
2017-08-27 12:10:38 +02:00
#ifndef NDEBUG
const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
2017-09-22 11:23:23 +02:00
switch (length) {
2017-08-27 12:10:38 +02:00
case 8:
2018-11-08 13:31:28 +01:00
LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec
2020-01-12 18:19:48 +01:00
<< ") @addr 0x" << std::hex << addr;
2017-08-27 12:10:38 +02:00
break;
case 4:
2018-11-08 13:31:28 +01:00
LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec
2020-01-12 18:19:48 +01:00
<< ") @addr 0x" << std::hex << addr;
2017-08-27 12:10:38 +02:00
break;
case 2:
2018-11-08 13:31:28 +01:00
LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec
2020-01-12 18:19:48 +01:00
<< ") @addr 0x" << std::hex << addr;
2017-08-27 12:10:38 +02:00
break;
case 1:
2018-11-08 13:31:28 +01:00
LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec
2020-01-12 18:19:48 +01:00
<< ") @addr 0x" << std::hex << addr;
2017-08-27 12:10:38 +02:00
break;
default:
2018-11-08 13:31:28 +01:00
LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
2017-08-27 12:10:38 +02:00
}
#endif
try {
switch (space) {
2017-09-22 11:23:23 +02:00
case traits<BASE>::MEM: {
if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
fault_data = addr;
if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
2017-10-04 10:31:11 +02:00
this->reg.trap_state = (1 << 31); // issue trap 0
return iss::Err;
}
try {
if(!(access && iss::access_type::DEBUG) && length>1 && (addr&(length-1))){
2021-07-06 21:19:36 +02:00
this->reg.trap_state = 1<<31 | 6<<16;
fault_data=addr;
return iss::Err;
}
auto res = type==iss::address_type::PHYSICAL?
write_mem(phys_addr_t{access, space, addr}, length, data):
write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
2021-07-06 21:19:36 +02:00
if (unlikely(res != iss::Ok)) {
this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
fault_data=addr;
}
2017-10-04 10:31:11 +02:00
return res;
} catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id;
2021-07-06 21:19:36 +02:00
fault_data=ta.addr;
2017-10-04 10:31:11 +02:00
return iss::Err;
}
phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
2017-09-22 11:23:23 +02:00
if ((paddr.val + length) > mem.size()) return iss::Err;
switch (paddr.val) {
2017-08-27 12:10:38 +02:00
case 0x10013000: // UART0 base, TXFIFO reg
case 0x10023000: // UART1 base, TXFIFO reg
2017-09-22 11:23:23 +02:00
uart_buf << (char)data[0];
if (((char)data[0]) == '\n' || data[0] == 0) {
// LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
// '"<<uart_buf.str()<<"'";
std::cout << uart_buf.str();
2017-08-27 12:10:38 +02:00
uart_buf.str("");
}
return iss::Ok;
2017-09-22 11:23:23 +02:00
case 0x10008000: { // HFROSC base, hfrosccfg reg
2017-10-04 10:31:11 +02:00
auto &p = mem(paddr.val / mem.page_size);
auto offs = paddr.val & mem.page_addr_mask;
2017-09-22 11:23:23 +02:00
std::copy(data, data + length, p.data() + offs);
2017-10-04 10:31:11 +02:00
auto &x = *(p.data() + offs + 3);
2017-09-22 11:23:23 +02:00
if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
2017-08-27 12:10:38 +02:00
return iss::Ok;
}
2017-09-22 11:23:23 +02:00
case 0x10008008: { // HFROSC base, pllcfg reg
2017-10-04 10:31:11 +02:00
auto &p = mem(paddr.val / mem.page_size);
auto offs = paddr.val & mem.page_addr_mask;
2017-09-22 11:23:23 +02:00
std::copy(data, data + length, p.data() + offs);
2017-10-04 10:31:11 +02:00
auto &x = *(p.data() + offs + 3);
2017-09-22 11:23:23 +02:00
x |= 0x80; // set pll lock upon writing
2017-08-27 12:10:38 +02:00
return iss::Ok;
2017-09-22 11:23:23 +02:00
} break;
2017-10-04 10:31:11 +02:00
default: {}
2017-08-27 12:10:38 +02:00
}
2017-09-22 11:23:23 +02:00
} break;
case traits<BASE>::CSR: {
if (length != sizeof(reg_t)) return iss::Err;
return write_csr(addr, *reinterpret_cast<const reg_t *>(data));
2017-09-22 11:23:23 +02:00
} break;
case traits<BASE>::FENCE: {
if ((addr + length) > mem.size()) return iss::Err;
switch (addr) {
2017-08-27 12:10:38 +02:00
case 2:
2017-09-22 11:23:23 +02:00
case 3: {
2017-08-27 12:10:38 +02:00
ptw.clear();
auto tvm = state.mstatus.TVM;
2017-08-27 12:10:38 +02:00
return iss::Ok;
}
}
2017-09-22 11:23:23 +02:00
} break;
case traits<BASE>::RES: {
atomic_reservation[addr] = data[0];
2017-09-22 11:23:23 +02:00
} break;
2017-08-27 12:10:38 +02:00
default:
return iss::Err;
}
return iss::Ok;
2017-09-22 11:23:23 +02:00
} catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id;
2021-07-06 21:19:36 +02:00
fault_data=ta.addr;
2017-08-27 12:10:38 +02:00
return iss::Err;
}
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_csr(unsigned addr, reg_t &val) {
2017-09-22 11:23:23 +02:00
if (addr >= csr.size()) return iss::Err;
2020-05-31 16:41:04 +02:00
auto req_priv_lvl = (addr >> 8) & 0x3;
if (this->reg.PRIV < req_priv_lvl) // not having required privileges
throw illegal_instruction_fault(this->fault_data);
2017-08-27 12:10:38 +02:00
auto it = csr_rd_cb.find(addr);
if (it == csr_rd_cb.end() || !it->second) // non existent register
throw illegal_instruction_fault(this->fault_data);
return (this->*(it->second))(addr, val);
2017-08-27 12:10:38 +02:00
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_csr(unsigned addr, reg_t val) {
2017-09-22 11:23:23 +02:00
if (addr >= csr.size()) return iss::Err;
2020-05-31 16:41:04 +02:00
auto req_priv_lvl = (addr >> 8) & 0x3;
if (this->reg.PRIV < req_priv_lvl) // not having required privileges
2020-05-31 16:41:04 +02:00
throw illegal_instruction_fault(this->fault_data);
if((addr&0xc00)==0xc00) // writing to read-only region
2020-05-31 16:41:04 +02:00
throw illegal_instruction_fault(this->fault_data);
2017-08-27 12:10:38 +02:00
auto it = csr_wr_cb.find(addr);
if (it == csr_wr_cb.end() || !it->second) // non existent register
throw illegal_instruction_fault(this->fault_data);
return (this->*(it->second))(addr, val);
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_csr_reg(unsigned addr, reg_t &val) {
val = csr[addr];
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_null(unsigned addr, reg_t &val) {
val = 0;
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_csr_reg(unsigned addr, reg_t val) {
csr[addr] = val;
return iss::Ok;
2017-08-27 12:10:38 +02:00
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_cycle(unsigned addr, reg_t &val) {
2018-11-08 13:31:28 +01:00
auto cycle_val = this->reg.icount + cycle_offset;
2017-09-22 11:23:23 +02:00
if (addr == mcycle) {
val = static_cast<reg_t>(cycle_val);
2017-09-22 11:23:23 +02:00
} else if (addr == mcycleh) {
if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
val = static_cast<reg_t>(cycle_val >> 32);
2017-08-27 12:10:38 +02:00
}
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cycle(unsigned addr, reg_t val) {
if (sizeof(typename traits<BASE>::reg_t) != 4) {
if (addr == mcycleh)
return iss::Err;
mcycle_csr = static_cast<uint64_t>(val);
} else {
if (addr == mcycle) {
mcycle_csr = (mcycle_csr & 0xffffffff00000000) + val;
} else {
mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff);
}
}
cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_instret(unsigned addr, reg_t &val) {
2021-07-07 11:30:00 +02:00
if ((addr&0xff) == (minstret&0xff)) {
val = static_cast<reg_t>(this->reg.instret);
2021-07-07 11:30:00 +02:00
} else if ((addr&0xff) == (minstreth&0xff)) {
if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
val = static_cast<reg_t>(this->reg.instret >> 32);
}
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_instret(unsigned addr, reg_t val) {
if (sizeof(typename traits<BASE>::reg_t) != 4) {
2021-07-07 11:30:00 +02:00
if ((addr&0xff) == (minstreth&0xff))
return iss::Err;
this->reg.instret = static_cast<uint64_t>(val);
} else {
2021-07-07 11:30:00 +02:00
if ((addr&0xff) == (minstret&0xff)) {
this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val;
} else {
this->reg.instret = (static_cast<uint64_t>(val)<<32) + (this->reg.instret & 0xffffffff);
}
}
this->reg.instret--;
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_time(unsigned addr, reg_t &val) {
uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
2017-10-25 22:05:31 +02:00
if (addr == time) {
val = static_cast<reg_t>(time_val);
} else if (addr == timeh) {
if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
val = static_cast<reg_t>(time_val >> 32);
}
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_tvec(unsigned addr, reg_t &val) {
val = csr[mtvec] & ~2;
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_status(unsigned addr, reg_t &val) {
val = state.mstatus & hart_state_type::get_mask();
2017-08-27 12:10:38 +02:00
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_status(unsigned addr, reg_t val) {
state.write_mstatus(val);
2017-08-27 12:10:38 +02:00
check_interrupt();
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
2021-12-01 12:56:36 +01:00
csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))| (mcause_max_irq-1));
2021-07-28 09:09:08 +02:00
return iss::Ok;
}
2021-11-09 19:47:34 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_hartid(unsigned addr, reg_t &val) {
val = mhartid_reg;
2017-08-27 12:10:38 +02:00
return iss::Ok;
}
2021-11-09 19:47:34 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) {
auto mask = get_irq_mask();
val = csr[mie] & mask;
2020-09-04 15:37:21 +02:00
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
auto mask = get_irq_mask();
2017-08-27 12:10:38 +02:00
csr[mie] = (csr[mie] & ~mask) | (val & mask);
check_interrupt();
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_ip(unsigned addr, reg_t &val) {
2021-11-09 19:47:34 +01:00
auto mask = get_irq_mask();
val = csr[mip] & mask;
2017-08-27 12:10:38 +02:00
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) {
auto mask = get_irq_mask();
2021-11-09 19:47:34 +01:00
mask &= 0xf; // only xSIP is writable
2017-08-27 12:10:38 +02:00
csr[mip] = (csr[mip] & ~mask) | (val & mask);
check_interrupt();
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_epc(unsigned addr, reg_t val) {
2021-07-09 13:01:22 +02:00
csr[addr] = val & get_pc_mask();
2021-07-07 11:30:00 +02:00
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_dcsr(unsigned addr, reg_t val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
2021-11-02 11:13:29 +01:00
// +-------------- ebreakm
// | +---------- stepi
// | | +++----- cause
// | | ||| +- step
csr[addr] = val & 0b1000100111000100U;
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dcsr_reg(unsigned addr, reg_t &val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
val = csr[addr];
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_reg(unsigned addr, reg_t val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
csr[addr] = val;
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dpc_reg(unsigned addr, reg_t &val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
val = this->reg.DPC;
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dpc_reg(unsigned addr, reg_t val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
this->reg.DPC = val;
return iss::Ok;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
2021-03-06 08:17:42 +01:00
if(mem_read_cb) return mem_read_cb(paddr, length, data);
2017-10-04 10:31:11 +02:00
switch (paddr.val) {
case 0x0200BFF8: { // CLINT base, mtime reg
2018-11-08 13:31:28 +01:00
if (sizeof(reg_t) < length) return iss::Err;
reg_t time_val;
this->read_csr(time, time_val);
2017-10-25 22:05:31 +02:00
std::copy((uint8_t *)&time_val, ((uint8_t *)&time_val) + length, data);
2017-10-04 10:31:11 +02:00
} break;
case 0x10008000: {
const mem_type::page_type &p = mem(paddr.val / mem.page_size);
uint64_t offs = paddr.val & mem.page_addr_mask;
std::copy(p.data() + offs, p.data() + offs + length, data);
if (this->reg.icount > 30000) data[3] |= 0x80;
} break;
default: {
for(auto offs=0U; offs<length; ++offs) {
*(data + offs)=mem[(paddr.val+offs)%mem.size()];
}
2017-10-04 10:31:11 +02:00
}
}
return iss::Ok;
2017-08-27 12:10:38 +02:00
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
2021-03-06 08:17:42 +01:00
if(mem_write_cb) return mem_write_cb(paddr, length, data);
2017-10-04 10:31:11 +02:00
switch (paddr.val) {
case 0x10013000: // UART0 base, TXFIFO reg
case 0x10023000: // UART1 base, TXFIFO reg
uart_buf << (char)data[0];
if (((char)data[0]) == '\n' || data[0] == 0) {
// LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
// '"<<uart_buf.str()<<"'";
std::cout << uart_buf.str();
uart_buf.str("");
2017-08-27 12:10:38 +02:00
}
break;
2017-10-04 10:31:11 +02:00
case 0x10008000: { // HFROSC base, hfrosccfg reg
mem_type::page_type &p = mem(paddr.val / mem.page_size);
size_t offs = paddr.val & mem.page_addr_mask;
std::copy(data, data + length, p.data() + offs);
uint8_t &x = *(p.data() + offs + 3);
if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
} break;
2017-10-04 10:31:11 +02:00
case 0x10008008: { // HFROSC base, pllcfg reg
mem_type::page_type &p = mem(paddr.val / mem.page_size);
size_t offs = paddr.val & mem.page_addr_mask;
std::copy(data, data + length, p.data() + offs);
uint8_t &x = *(p.data() + offs + 3);
x |= 0x80; // set pll lock upon writing
} break;
default: {
mem_type::page_type &p = mem(paddr.val / mem.page_size);
std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
// tohost handling in case of riscv-test
if (paddr.access && iss::access_type::FUNC) {
2021-07-07 11:30:00 +02:00
auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) ||
(traits<BASE>::XLEN == 64 && paddr.val == tohost);
2017-10-04 10:31:11 +02:00
auto tohost_lower =
2021-07-07 11:30:00 +02:00
(traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
2017-10-04 10:31:11 +02:00
if (tohost_lower || tohost_upper) {
uint64_t hostvar = *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask));
if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
switch (hostvar >> 48) {
case 0:
2018-11-08 13:31:28 +01:00
if (hostvar != 0x1) {
2017-10-04 10:31:11 +02:00
LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
<< "), stopping simulation";
2018-11-08 13:31:28 +01:00
} else {
2017-10-04 10:31:11 +02:00
LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
<< "), stopping simulation";
2017-11-23 14:48:18 +01:00
}
2020-04-17 19:23:43 +02:00
this->reg.trap_state=std::numeric_limits<uint32_t>::max();
this->interrupt_sim=hostvar;
break;
//throw(iss::simulation_stopped(hostvar));
2017-10-04 10:31:11 +02:00
case 0x0101: {
char c = static_cast<char>(hostvar & 0xff);
if (c == '\n' || c == 0) {
LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
uart_buf.str("");
} else
uart_buf << c;
to_host_wr_cnt = 0;
} break;
default:
break;
}
} else if (tohost_lower)
to_host_wr_cnt++;
2021-07-07 11:30:00 +02:00
} else if ((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) ||
(traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
2017-10-04 10:31:11 +02:00
uint64_t fhostvar = *reinterpret_cast<uint64_t *>(p.data() + (fromhost & mem.page_addr_mask));
*reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
}
}
}
2017-08-27 12:10:38 +02:00
}
return iss::Ok;
2017-08-27 12:10:38 +02:00
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> inline void riscv_hart_m_p<BASE, FEAT>::reset(uint64_t address) {
BASE::reset(address);
state.mstatus = hart_state_type::mstatus_reset_val;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check_interrupt() {
2021-07-06 21:19:36 +02:00
//auto ideleg = csr[mideleg];
2017-09-22 11:23:23 +02:00
// Multiple simultaneous interrupts and traps at the same privilege level are
// handled in the following decreasing priority order:
// external interrupts, software interrupts, timer interrupts, then finally
// any synchronous traps.
auto ena_irq = csr[mip] & csr[mie];
2017-08-27 12:10:38 +02:00
2018-11-08 13:31:28 +01:00
bool mie = state.mstatus.MIE;
2021-03-06 08:17:42 +01:00
auto m_enabled = this->reg.PRIV < PRIV_M || (this->reg.PRIV == PRIV_M && mie);
2021-07-07 11:30:00 +02:00
auto enabled_interrupts = m_enabled ? ena_irq : 0;
2017-08-27 12:10:38 +02:00
2017-09-22 11:23:23 +02:00
if (enabled_interrupts != 0) {
2017-08-27 12:10:38 +02:00
int res = 0;
while ((enabled_interrupts & 1) == 0) {
enabled_interrupts >>= 1;
res++;
}
this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
2017-08-27 12:10:38 +02:00
}
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
// flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
2017-08-27 12:10:38 +02:00
// calculate and write mcause val
auto trap_id = bit_sub<0, 16>(flags);
auto cause = bit_sub<16, 15>(flags);
2017-08-27 12:10:38 +02:00
// calculate effective privilege level
2017-09-22 11:23:23 +02:00
if (trap_id == 0) { // exception
2021-11-02 11:13:29 +01:00
if (cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
2017-08-27 12:10:38 +02:00
// store ret addr in xepc register
2021-07-09 13:01:22 +02:00
csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
2021-11-02 15:10:20 +01:00
/*
* write mtval if new_priv=M_MODE, spec says:
* When a hardware breakpoint is triggered, or an instruction-fetch, load,
* or store address-misaligned,
* access, or page-fault exception occurs, mtval is written with the
* faulting effective address.
*/
2021-09-23 21:09:36 +02:00
switch(cause){
case 0:
2021-11-02 15:10:20 +01:00
csr[mtval] = static_cast<reg_t>(addr);
2021-09-23 21:09:36 +02:00
break;
case 2:
csr[mtval] = (instr & 0x3)==3?instr:instr&0xffff;
break;
2021-11-02 11:13:29 +01:00
case 3:
//TODO: implement debug mode behavior
// csr[dpc] = addr;
// csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
2021-11-13 12:47:23 +01:00
csr[mtval] = addr;
2021-11-02 11:13:29 +01:00
break;
2021-11-02 15:10:20 +01:00
case 4:
case 6:
2021-09-23 21:09:36 +02:00
csr[mtval] = fault_data;
2021-11-02 15:10:20 +01:00
break;
default:
csr[mtval] = 0;
2021-09-23 21:09:36 +02:00
}
2017-09-22 11:23:23 +02:00
fault_data = 0;
} else {
2021-07-09 13:01:22 +02:00
csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt
2017-09-22 11:23:23 +02:00
this->reg.pending_trap = 0;
2017-08-27 12:10:38 +02:00
}
2021-12-01 12:56:36 +01:00
csr[mcause] = (trap_id << (traits<BASE>::XLEN-1)) + cause;
2017-08-27 12:10:38 +02:00
// update mstatus
2017-09-22 11:23:23 +02:00
// xPP field of mstatus is written with the active privilege mode at the time
// of the trap; the x PIE field of mstatus
// is written with the value of the active interrupt-enable bit at the time of
// the trap; and the x IE field of mstatus
2017-08-27 12:10:38 +02:00
// is cleared
// store the actual privilege level in yPP and store interrupt enable flags
state.mstatus.MPP = PRIV_M;
state.mstatus.MPIE = state.mstatus.MIE;
state.mstatus.MIE = false;
2017-08-27 12:10:38 +02:00
// get trap vector
auto ivec = csr[mtvec];
2017-09-22 11:23:23 +02:00
// calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
// bits in mtvec
this->reg.NEXT_PC = ivec & ~0x3UL;
2017-09-22 11:23:23 +02:00
if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
2017-08-27 12:10:38 +02:00
// reset trap state
2021-03-06 08:17:42 +01:00
this->reg.PRIV = PRIV_M;
2017-09-22 11:23:23 +02:00
this->reg.trap_state = 0;
2018-11-08 13:31:28 +01:00
std::array<char, 32> buffer;
2021-10-10 19:06:41 +02:00
#if defined(_MSC_VER)
sprintf(buffer.data(), "0x%016llx", addr);
#else
2018-11-08 13:31:28 +01:00
sprintf(buffer.data(), "0x%016lx", addr);
2021-10-10 19:06:41 +02:00
#endif
2020-04-17 19:23:43 +02:00
if((flags&0xffffffff) != 0xffffffff)
2018-11-08 13:31:28 +01:00
CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
2020-05-29 08:52:55 +02:00
<< (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
<< " at address " << buffer.data() << " occurred";
2017-08-27 12:10:38 +02:00
return this->reg.NEXT_PC;
}
2021-11-02 11:13:29 +01:00
template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::leave_trap(uint64_t flags) {
state.mstatus.MIE = state.mstatus.MPIE;
2021-07-06 21:19:36 +02:00
state.mstatus.MPIE = 1;
2017-08-27 12:10:38 +02:00
// sets the pc to the value stored in the x epc register.
2021-07-07 11:30:00 +02:00
this->reg.NEXT_PC = csr[mepc] & get_pc_mask();
CLOG(INFO, disass) << "Executing xRET";
2021-07-06 21:19:36 +02:00
check_interrupt();
2017-08-27 12:10:38 +02:00
return this->reg.NEXT_PC;
}
2020-09-04 15:37:21 +02:00
} // namespace arch
} // namespace iss
2017-08-27 12:10:38 +02:00
#endif /* _RISCV_HART_M_P_H */