Refactored arch_if to save unneeded constructor calls
This commit is contained in:
parent
8092326437
commit
d160a34c5d
2
dbt-core
2
dbt-core
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@ -1 +1 @@
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Subproject commit 54cf894c3f3897a57f366905345514f5e94a5166
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Subproject commit d73fee68dd164c016721ae76d1538136513e6b37
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@ -467,8 +467,10 @@ public:
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virtual phys_addr_t virt2phys(const iss::addr_t &addr) override;
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iss::status read(const iss::addr_t &addr, unsigned length, uint8_t *const data) override;
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iss::status write(const iss::addr_t &addr, unsigned length, const uint8_t *const data) override;
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iss::status read(const address_type type, const access_type access, const uint32_t space,
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const uint64_t addr, const unsigned length, uint8_t *const data) override;
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iss::status write(const address_type type, const access_type access, const uint32_t space,
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const uint64_t addr, const unsigned length, const uint8_t *const data) override;
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virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data); }
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virtual uint64_t enter_trap(uint64_t flags, uint64_t addr) override;
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@ -624,9 +626,9 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
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const auto fsize = pseg->get_file_size(); // 0x42c/0x0
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const auto seg_data = pseg->get_data();
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if (fsize > 0) {
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auto res = this->write(
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phys_addr_t(iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, pseg->get_physical_address()),
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fsize, reinterpret_cast<const uint8_t *const>(seg_data));
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auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE,
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traits<BASE>::MEM, pseg->get_physical_address(),
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fsize, reinterpret_cast<const uint8_t *const>(seg_data));
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if (res != iss::Ok)
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LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex
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<< pseg->get_physical_address();
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@ -647,36 +649,39 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
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}
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template <typename BASE>
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iss::status riscv_hart_msu_vp<BASE>::read(const iss::addr_t &addr, unsigned length, uint8_t *const data) {
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iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_type access, const uint32_t space,
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const uint64_t addr, const unsigned length, uint8_t *const data) {
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#ifndef NDEBUG
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if (addr.access && iss::access_type::DEBUG) {
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if (access && iss::access_type::DEBUG) {
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LOG(TRACE) << "debug read of " << length << " bytes @addr " << addr;
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} else {
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LOG(TRACE) << "read of " << length << " bytes @addr " << addr;
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}
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#endif
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try {
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switch (addr.space) {
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switch (space) {
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case traits<BASE>::MEM: {
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if (unlikely((addr.access == iss::access_type::FETCH || addr.access == iss::access_type::DEBUG_FETCH) && (addr.val & 0x1) == 1)) {
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fault_data = addr.val;
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if (addr.access && iss::access_type::DEBUG) throw trap_access(0, addr.val);
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if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
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fault_data = addr;
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if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
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this->reg.trap_state = (1 << 31); // issue trap 0
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return iss::Err;
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}
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try {
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if (unlikely((addr.val & ~PGMASK) != ((addr.val + length - 1) & ~PGMASK))) { // we may cross a page boundary
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if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
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vm_info vm = hart_state<reg_t>::decode_vm_info(this->reg.machine_state, state.satp);
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if (vm.levels != 0) { // VM is active
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auto split_addr = (addr.val + length) & ~PGMASK;
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auto len1 = split_addr - addr.val;
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auto res = read(addr, len1, data);
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auto split_addr = (addr + length) & ~PGMASK;
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auto len1 = split_addr - addr;
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auto res = read(type, access, space, addr, len1, data);
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if (res == iss::Ok)
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res = read(iss::addr_t{addr.access, addr.type, addr.space, split_addr}, length - len1, data + len1);
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res = read(type, access, space, split_addr, length - len1, data + len1);
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return res;
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}
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}
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auto res = read_mem( BASE::v2p(addr), length, data);
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auto res = type==iss::address_type::PHYSICAL?
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read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
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read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
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if (unlikely(res != iss::Ok)) this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
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return res;
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} catch (trap_access &ta) {
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@ -686,11 +691,11 @@ iss::status riscv_hart_msu_vp<BASE>::read(const iss::addr_t &addr, unsigned leng
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} break;
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case traits<BASE>::CSR: {
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if (length != sizeof(reg_t)) return iss::Err;
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return read_csr(addr.val, *reinterpret_cast<reg_t *const>(data));
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return read_csr(addr, *reinterpret_cast<reg_t *const>(data));
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} break;
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case traits<BASE>::FENCE: {
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if ((addr.val + length) > mem.size()) return iss::Err;
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switch (addr.val) {
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if ((addr + length) > mem.size()) return iss::Err;
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switch (addr) {
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case 2: // SFENCE:VMA lower
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case 3: { // SFENCE:VMA upper
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auto tvm = state.mstatus.TVM;
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@ -704,10 +709,10 @@ iss::status riscv_hart_msu_vp<BASE>::read(const iss::addr_t &addr, unsigned leng
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}
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} break;
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case traits<BASE>::RES: {
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auto it = atomic_reservation.find(addr.val);
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auto it = atomic_reservation.find(addr);
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if (it != atomic_reservation.end() && it->second != 0) {
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memset(data, 0xff, length);
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atomic_reservation.erase(addr.val);
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atomic_reservation.erase(addr);
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} else
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memset(data, 0, length);
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} break;
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@ -722,9 +727,10 @@ iss::status riscv_hart_msu_vp<BASE>::read(const iss::addr_t &addr, unsigned leng
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}
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template <typename BASE>
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iss::status riscv_hart_msu_vp<BASE>::write(const iss::addr_t &addr, unsigned length, const uint8_t *const data) {
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iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access_type access, const uint32_t space,
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const uint64_t addr, const unsigned length, const uint8_t *const data) {
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#ifndef NDEBUG
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const char *prefix = (addr.access && iss::access_type::DEBUG) ? "debug " : "";
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const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
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switch (length) {
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case 8:
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LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec
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@ -747,27 +753,29 @@ iss::status riscv_hart_msu_vp<BASE>::write(const iss::addr_t &addr, unsigned len
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}
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#endif
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try {
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switch (addr.space) {
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switch (space) {
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case traits<BASE>::MEM: {
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if (unlikely((addr.access && iss::access_type::FETCH) && (addr.val & 0x1) == 1)) {
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fault_data = addr.val;
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if (addr.access && iss::access_type::DEBUG) throw trap_access(0, addr.val);
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if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
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fault_data = addr;
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if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
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this->reg.trap_state = (1 << 31); // issue trap 0
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return iss::Err;
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}
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try {
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if (unlikely((addr.val & ~PGMASK) != ((addr.val + length - 1) & ~PGMASK))) { // we may cross a page boundary
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if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
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vm_info vm = hart_state<reg_t>::decode_vm_info(this->reg.machine_state, state.satp);
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if (vm.levels != 0) { // VM is active
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auto split_addr = (addr.val + length) & ~PGMASK;
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auto len1 = split_addr - addr.val;
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auto res = write(addr, len1, data);
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auto split_addr = (addr + length) & ~PGMASK;
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auto len1 = split_addr - addr;
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auto res = write(type, access, space, addr, len1, data);
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if (res == iss::Ok)
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res = write(iss::addr_t{addr.access, addr.type, addr.space, split_addr}, length - len1, data + len1);
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res = write(type, access, space, split_addr, length - len1, data + len1);
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return res;
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}
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}
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auto res = write_mem(BASE::v2p(addr), length, data);
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auto res = type==iss::address_type::PHYSICAL?
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write_mem(phys_addr_t{access, space, addr}, length, data):
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write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
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if (unlikely(res != iss::Ok))
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this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 7 (Store/AMO access fault)
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return res;
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@ -776,7 +784,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const iss::addr_t &addr, unsigned len
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return iss::Err;
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}
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phys_addr_t paddr = BASE::v2p(addr);
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phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
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if ((paddr.val + length) > mem.size()) return iss::Err;
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switch (paddr.val) {
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case 0x10013000: // UART0 base, TXFIFO reg
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@ -810,11 +818,11 @@ iss::status riscv_hart_msu_vp<BASE>::write(const iss::addr_t &addr, unsigned len
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} break;
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case traits<BASE>::CSR: {
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if (length != sizeof(reg_t)) return iss::Err;
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return write_csr(addr.val, *reinterpret_cast<const reg_t *>(data));
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return write_csr(addr, *reinterpret_cast<const reg_t *>(data));
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} break;
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case traits<BASE>::FENCE: {
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if ((addr.val + length) > mem.size()) return iss::Err;
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switch (addr.val) {
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if ((addr + length) > mem.size()) return iss::Err;
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switch (addr) {
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case 2:
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case 3: {
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ptw.clear();
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@ -829,7 +837,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const iss::addr_t &addr, unsigned len
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}
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} break;
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case traits<BASE>::RES: {
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atomic_reservation[addr.val] = data[0];
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atomic_reservation[addr] = data[0];
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} break;
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default:
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return iss::Err;
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@ -1182,8 +1190,8 @@ typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_hart_msu_vp<BASE>::virt2phys
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// check that physical address of PTE is legal
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reg_t pte = 0;
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const uint8_t res = this->read(phys_addr_t{addr.access, traits<BASE>::MEM, base + idx * vm.ptesize},
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vm.ptesize, (uint8_t *)&pte);
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const uint8_t res = this->read(iss::address_type::PHYSICAL, addr.access,
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traits<BASE>::MEM, base + idx * vm.ptesize, vm.ptesize, (uint8_t *)&pte);
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if (res != 0) throw trap_load_access_fault(addr.val);
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const reg_t ppn = pte >> PTE_PPN_SHIFT;
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@ -269,7 +269,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t ad
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template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t> &data) {
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auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
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return srv->execute_syncronized(&arch_if::write, core, a, data.size(), data.data());
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auto f = [&]() -> status { return core->write(a, data.size(), data.data()); };
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return srv->execute_syncronized(f);
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}
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template <typename ARCH>
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