fixes cause CSR handling

fixes sysc compile issues
changes [m|u]cause rd/wr handling
2023-06-12 17:38:56 +02:00 · 2023-06-12 09:58:24 +02:00 · 2023-06-11 18:29:58 +02:00 · 2023-06-01 06:55:21 +02:00 · 2023-05-27 10:20:49 +02:00 · 2023-05-25 12:52:30 +02:00
38 changed files with 5184 additions and 2778 deletions
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@ -29,19 +29,24 @@ endif()

 add_subdirectory(softfloat)

-# library files
-FILE(GLOB GEN_SOURCES
-    ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
-	${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
-)
-
 set(LIB_SOURCES 
    src/iss/plugin/instruction_count.cpp
 	src/iss/arch/tgc_c.cpp
 	src/vm/interp/vm_tgc_c.cpp
 	src/vm/fp_functions.cpp
-    ${GEN_SOURCES}
 )
+
+# library files
+if(TARGET ${CORE_NAME}_cpp)
+    list(APPEND LIB_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
+else()
+    FILE(GLOB GEN_SOURCES
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
+    )
+    list(APPEND LIB_SOURCES ${GEN_SOURCES})
+endif()
+
 if(TARGET RapidJSON OR TARGET RapidJSON::RapidJSON)
    list(APPEND LIB_SOURCES src/iss/plugin/cycle_estimate.cpp src/iss/plugin/pctrace.cpp)
 endif()
@ -126,17 +131,31 @@ project(tgc-sim)
 find_package(Boost COMPONENTS program_options thread REQUIRED)

 add_executable(${PROJECT_NAME} src/main.cpp)
-FILE(GLOB TGC_SOURCES  ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp) 
+if(TARGET ${CORE_NAME}_cpp)
+    list(APPEND TGC_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
+else()
+    FILE(GLOB TGC_SOURCES
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
+    )
+    list(APPEND TGC_SOURCES ${GEN_SOURCES})
+endif()
+
 foreach(F IN LISTS TGC_SOURCES)
-    string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
-    string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
-    target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    if (${F} MATCHES ".*/arch/([^/]*)\.cpp")
+        string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
+        string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    endif()
 endforeach()

 if(WITH_LLVM)
    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
    target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
 endif()
+if(WITH_TCC)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
+endif()
 # Links the target exe against the libraries
 target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc)
 if(TARGET Boost::program_options)
@ -161,19 +180,19 @@ install(TARGETS tgc-sim
 ###############################################################################
 #
 ###############################################################################
-project(dbt-rise-tgc_sc VERSION 1.0.0)
-
-include(SystemCPackage)
-if(SystemC_FOUND)
+if(TARGET scc-sysc)
+	project(dbt-rise-tgc_sc VERSION 1.0.0)
    add_library(${PROJECT_NAME} src/sysc/core_complex.cpp)
    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
    target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
    foreach(F IN LISTS TGC_SOURCES)
-        string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
-        string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+        if (${F} MATCHES ".*/arch/([^/]*)\.cpp")
+            string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
+            string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
+            target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+        endif()
    endforeach()
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
    if(WITH_LLVM)
        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
    endif()
--- a/contrib/.gitignore
+++ b/contrib/.gitignore
@ -0,0 +1,3 @@
+/results
+/cwr
+/*.xml
--- a/contrib/README.md
+++ b/contrib/README.md
@ -0,0 +1,43 @@
+# Notes
+
+* requires conan version 1.59
+* requires decent cmake version 3.23
+
+Setup for tcsh:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+setenv TGFS_INSTALL_ROOT `pwd`/install
+setenv COWAREHOME <your SNPS PA installation>
+setenv SNPSLMD_LICENSE_FILE <your SNPS PA license file>
+source $COWAREHOME/SLS/linux/setup.csh pae
+setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
+setenv PATH $COWAREHOME/common/bin/:${PATH}
+setenv CC  $COWAREHOME/SLS/linux/common/bin/gcc
+setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```
+
+Setup for bash:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+export TGFS_INSTALL_ROOT `pwd`/install
+module load tools/pa/T-2022.06
+export SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM=1
+export CC=$COWAREHOME/SLS/linux/common/bin/gcc
+export CXX=$COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```
--- a/contrib/build.tcl
+++ b/contrib/build.tcl
@ -16,7 +16,7 @@ namespace eval Specification {
                set libdir "${install_dir}/lib64"
                set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
                # Set the Linker paths.
-                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc"]
+                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc -lscc-sysc"]
            }
            default {
               puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"
--- a/contrib/hello.dis
+++ b/contrib/hello.dis
--- a/contrib/hello.elf
+++ b/contrib/hello.elf
--- a/contrib/minres.png
+++ b/contrib/minres.png
--- a/contrib/tgc_import.tcl
+++ b/contrib/tgc_import.tcl
@ -6,14 +6,11 @@ proc getScriptDirectory {} {
    set scriptFolder [file dirname $dispScriptFile]
    return $scriptFolder
 }
-if { $::env(SNPS_VP_PRODUCT) == "PAULTRA" } {
    set hardware /HARDWARE/HW/HW
-} else {
-    set hardware /HARDWARE
-}

 set scriptDir [getScriptDirectory]
 set top_design_name core_complex
+set encap_name sysc::tgfs::${top_design_name}
 set clocks clk_i
 set resets rst_i
 set model_prefix "i_"
@ -28,7 +25,8 @@ set model_postfix ""
 ::pct::set_update_existing_encaps_flag true
 ::pct::set_dynamic_port_arrays_flag true
 ::pct::set_import_scml_properties_flag true
-::pct::load_modules --set-category modules tgc_import.cc
+::pct::set_import_encap_prop_as_extra_prop_flag true
+::pct::load_modules --set-category modules ${scriptDir}/tgc_import.cc

 # Set Port Protocols correctly
 set block ${top_design_name}
@ -38,13 +36,15 @@ foreach clock ${clocks} {
 foreach reset ${resets} {
    ::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
 }
-::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
+#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16

 # Set compile settings and look
 set block SYSTEM_LIBRARY:${top_design_name}
-::pct::set_encap_build_script $block/${top_design_name} $scriptDir/build.tcl
+::pct::set_encap_build_script $block/${encap_name} $scriptDir/build.tcl
 ::pct::set_background_color_rgb $block 255 255 255 255
-::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${top_design_name} 
+::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${encap_name} ${encap_name}() 
+::pct::set_bounds i_${top_design_name} 200 300 100 400
+::pct::set_image i_${top_design_name} "$scriptDir/minres.png" center center false true

 # export the result as component
 ::pct::export_system_library ${top_design_name}  ${top_design_name}.xml
--- a/contrib/tgc_import_tb.tcl
+++ b/contrib/tgc_import_tb.tcl
@ -0,0 +1,71 @@
+source tgc_import.tcl
+set hardware /HARDWARE/HW/HW
+set FW_name ${scriptDir}/hello.elf
+
+puts "instantiate testbench elements"
+::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
+::pct::set_param_value i_Memory_Generic/MEM:protocol {Protocol Common Parameters} address_width 30
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
+::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
+::pct::set_bounds i_Memory_Generic 1000 300 100 100
+
+::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
+::BLWizard::generateFramework i_Bus SBLTLM2FT  * {} \
+						{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
+::pct::set_bounds i_Bus 700 300 100 400
+::pct::create_connection C_ibus i_core_complex/ibus i_Bus/i_core_complex_ibus
+::pct::set_location_on_owner i_Bus/i_core_complex_ibus 10
+::pct::create_connection C_dbus i_core_complex/dbus i_Bus/i_core_complex_dbus
+::pct::set_location_on_owner i_Bus/i_core_complex_dbus 10
+::pct::create_connection C_mem i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
+
+puts "instantiating clock manager"
+set clock "Clk"
+::hw::create_hw_instance "" GenericIPlib:ClockGenerator ${clock}_clock
+::pct::set_bounds ${clock}_clock 100 100 100 100
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period 1000
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period_unit sc_core::SC_PS
+
+puts "instantiating reset manager"
+set reset "Rst"
+ ::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 0
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
+::pct::set_bounds ${reset}_reset 300 100 100 100
+
+puts "connecting reset/clock"
+::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
+::pct::add_ports_to_connection C_clk i_Bus/Clk
+::pct::add_ports_to_connection C_clk i_Memory_Generic/CLK
+::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
+::pct::add_ports_to_connection C_rst i_Bus/Rst
+
+puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
+::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name}
+::pct::set_address $hardware/i_${top_design_name}/ibus:i_Memory_Generic/MEM 0x0
+::pct::set_address $hardware/i_${top_design_name}/dbus:i_Memory_Generic/MEM 0x0
+::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 }
+
+::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::create_simulation_build_config Debug
+::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
+# add build settings and save design for next steps
+#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
+#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
+
+#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
+#::simulation::run_simulation Simulation
+
+#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
+#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
+#::pct::export_system "export"
+#::cd "export"
+#::scsh::open-project
+#::scsh::build
+#::scsh::elab sim
+::pct::save_system testbench.xml
--- a/gen_input/TGC_C.core_desc
+++ b/gen_input/TGC_C.core_desc
@ -1,13 +1,13 @@
-import "RV32I.core_desc"
-import "RVM.core_desc"
-import "RVC.core_desc"
+import "ISA/RV32I.core_desc"
+import "ISA/RVM.core_desc"
+import "ISA/RVC.core_desc"

 Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
    architectural_state {
        XLEN=32;
        // definitions for the architecture wrapper
        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
-        unsigned MARCHID_VAL = 0x80000003;
+        unsigned int MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned int MARCHID_VAL = 0x80000003;
    }
 }
--- a/gen_input/templates/CORENAME.cpp.gtl
+++ b/gen_input/templates/CORENAME.cpp.gtl
@ -33,7 +33,7 @@
 def getRegisterSizes(){
 	def regs = registers.collect{it.size}
 	regs[-1]=64 // correct for NEXT_PC
-	//regs+=[32, 32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
+	regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
    return regs
 }
 %>
@ -62,8 +62,8 @@ void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
    reg.PC=address;
    reg.NEXT_PC=reg.PC;
    reg.PRIV=0x3;
-    trap_state=0;
-    icount=0;
+    reg.trap_state=0;
+    reg.icount=0;
 }

 uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
--- a/gen_input/templates/CORENAME.h.gtl
+++ b/gen_input/templates/CORENAME.h.gtl
@ -37,7 +37,7 @@ def nativeTypeSize(int size){
 }
 def getRegisterSizes(){
    def regs = registers.collect{nativeTypeSize(it.size)}
-    // regs+=[32,32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
+    regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
    return regs
 }
 def getRegisterOffsets(){
@ -91,7 +91,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
    constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};

    enum reg_e {
-        ${registers.collect{it.name}.join(', ')}, NUM_REGS
+        ${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
    };

    using reg_t = uint${addrDataWidth}_t;
@ -136,7 +136,7 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {

    uint8_t* get_regs_base_ptr() override;

-    inline uint64_t get_icount() { return icount; }
+    inline uint64_t get_icount() { return reg.icount; }

    inline bool should_stop() { return interrupt_sim; }

@ -154,7 +154,7 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {

    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }

-    inline uint32_t get_last_branch() { return last_branch; }
+    inline uint32_t get_last_branch() { return reg.last_branch; }


 #pragma pack(push, 1)
@ -162,14 +162,14 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
        registers.each { reg -> if(reg.size>0) {%> 
        uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
        }}%>
+        uint32_t trap_state = 0, pending_trap = 0;
+        uint64_t icount = 0;
+        uint64_t cycle = 0;
+        uint64_t instret = 0;
+        uint32_t instruction = 0;
+        uint32_t last_branch = 0;
    } reg;
 #pragma pack(pop)
-    uint32_t trap_state = 0, pending_trap = 0;
-    uint64_t icount = 0;
-    uint64_t cycle = 0;
-    uint64_t instret = 0;
-    uint32_t instruction = 0;
-    uint32_t last_branch = 0;
    std::array<address_type, 4> addr_mode;
    
    uint64_t interrupt_sim=0;
--- a/gen_input/templates/CORENAME_instr.yaml.gtl
+++ b/gen_input/templates/CORENAME_instr.yaml.gtl
@ -13,5 +13,8 @@ ${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %>
  - ${it.instruction.name}:
    encoding: ${it.encoding}
    mask: ${it.mask}<%if(it.attributes.size) {%>
-    attributes: ${it.attributes}<%}}}%>
+    attributes: ${it.attributes}<%}%>
+    size:   ${it.length}
+    branch:   ${it.modifiesPC}
+    delay:   ${it.isConditional?"[1,1]":"1"}<%}}%>

--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@ -121,8 +121,8 @@ protected:

    inline void raise(uint16_t trap_id, uint16_t cause){
        auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
-        this->core.trap_state = trap_val;
-        this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
+        this->core.reg.trap_state = trap_val;
+        this->template get_reg<uint${addrDataWidth}_t>(traits::NEXT_PC) = std::numeric_limits<uint${addrDataWidth}_t>::max();
    }

    inline void leave(unsigned lvl){
@ -146,18 +146,17 @@ protected:
    
    inline void process_spawn_blocks() {
        if(spawn_blocks.size()==0) return;
-        std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
        for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
             if(*it){
                 (*it)();
                 ++it;
             } else
                 spawn_blocks.erase(it);
-        std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
    }
 <%functions.each{ it.eachLine { %>
    ${it}<%}%>
 <%}%>
+
 private:
    /****************************************************************************
     * start opcode definitions
@ -243,18 +242,18 @@ typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t
 template <typename ARCH>
 typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
    auto pc=start;
-    auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-    auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-    auto& trap_state = this->core.trap_state;
-    auto& icount = this->core.icount;
-    auto& cycle = this->core.cycle;
-    auto& instret = this->core.instret;
-    auto& instr = this->core.instruction;
+    auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+    auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+    auto& trap_state = this->core.reg.trap_state;
+    auto& icount =  this->core.reg.icount;
+    auto& cycle =  this->core.reg.cycle;
+    auto& instret =  this->core.reg.instret;
+    auto& instr =  this->core.reg.instruction;
    // we fetch at max 4 byte, alignment is 2
    auto *const data = reinterpret_cast<uint8_t*>(&instr);

    while(!this->core.should_stop() &&
-            !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
+            !(is_count_limit_enabled(cond) && icount >= icount_limit)){
        if(fetch_ins(pc, data)!=iss::Ok){
            this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
            pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
@ -263,6 +262,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                    (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
            auto inst_id = decode_inst_id(instr);
            // pre execution stuff
+             this->core.reg.last_branch = 0;
            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
            switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
            case arch::traits<ARCH>::opcode_e::${instr.name}: {
@ -289,8 +289,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
            // post execution stuff
            process_spawn_blocks();
            if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
-            // if(!this->core.trap_state) // update trap state if there is a pending interrupt
-            //    this->core.trap_state = this->core.pending_trap;
+            // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt
+            //    this->core.reg.trap_state =  this->core.reg.pending_trap;
            // trap check
            if(trap_state!=0){
                super::core.enter_trap(trap_state, pc.val, instr);
@ -301,7 +301,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
            cycle++;
            pc.val=*NEXT_PC;
            this->core.reg.PC = this->core.reg.NEXT_PC;
-            this->core.trap_state = this->core.pending_trap;
+            this->core.reg.trap_state =  this->core.reg.pending_trap;
        }
    }
    return pc;
--- a/gen_input/templates/tcc/vm-vm_CORENAME.cpp.gtl
+++ b/gen_input/templates/tcc/vm-vm_CORENAME.cpp.gtl
@ -55,10 +55,12 @@ using namespace iss::debugger;

 template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
 public:
+    using traits = arch::traits<ARCH>;
    using super       = typename iss::tcc::vm_base<ARCH>;
    using virt_addr_t = typename super::virt_addr_t;
    using phys_addr_t = typename super::phys_addr_t;
    using code_word_t = typename super::code_word_t;
+    using mem_type_e  = typename traits::mem_type_e;    
    using addr_t      = typename super::addr_t;
    using tu_builder  = typename super::tu_builder;

@ -82,7 +84,7 @@ protected:
    using compile_ret_t = std::tuple<continuation_e>;
    using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);

-    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}

    void setup_module(std::string m) override {
        super::setup_module(m);
@ -104,10 +106,10 @@ protected:

    inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
        switch(reg_num){
-        case traits<ARCH>::NEXT_PC:
+        case traits::NEXT_PC:
            tu("*next_pc = {:#x};", pc.val);
            break;
-        case traits<ARCH>::PC:
+        case traits::PC:
            tu("*pc = {:#x};", pc.val);
            break;
        default:
@ -123,7 +125,7 @@ protected:
    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
+    enum { LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)), LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16)) };

    std::array<compile_func, LUT_SIZE> lut;

@ -170,6 +172,12 @@ protected:
        }
        return lut_val;
    }
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
+    }    

 private:
    /****************************************************************************
@ -185,13 +193,28 @@ private:
    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
-        {${instr.length}, 0b${instr.value}, 0b${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
    }};
 
    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
    /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){<%instr.code.eachLine{%>
+    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
+        tu("${instr.name}_{:#010x}:", pc.val);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate console output when executing the command */<%instr.disass.eachLine{%>
+            ${it}<%}%>
+        }
+        auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
+        pc=pc+4;
+        gen_set_pc(tu, pc, traits::NEXT_PC);
+        tu.open_scope();<%instr.behavior.eachLine{%>
        ${it}<%}%>
+        tu.close_scope();
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
+        gen_trap_check(tu);
+        return returnValue;
    }
    <%}%>
    /****************************************************************************
@ -233,20 +256,20 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
    // we fetch at max 4 byte, alignment is 2
    enum {TRAP_ID=1<<16};
    code_word_t insn = 0;
-    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
    phys_addr_t paddr(pc);
    auto *const data = (uint8_t *)&insn;
    paddr = this->core.v2p(pc);
-    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-        auto res = this->core.read(paddr, 2, data);
-        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
-            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-        }
-    } else {
+//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+//        auto res = this->core.read(paddr, 2, data);
+//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
+//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+//        }
+//    } else {
        auto res = this->core.read(paddr, 4, data);
        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-    }
+//    }
    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
    // curr pc on stack
    ++inst_cnt;
@ -260,13 +283,13 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,

 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
    tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
+    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
 }

 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
    tu("leave_trap(core_ptr, {});", lvl);
-    tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
+    tu.store(traits::NEXT_PC, tu.read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN));
+    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
 }

 template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
@ -274,8 +297,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t

 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
    tu("trap_entry:");
-    tu("enter_trap(core_ptr, *trap_state, *pc);");
-    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
+    tu("enter_trap(core_ptr, *trap_state, *pc, 0);");
+    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(),32));
    tu("return *next_pc;");
 }

--- a/gen_input/templates/tcc/CORENAME_cyles.txt.gtl
+++ b/gen_input/templates/tcc/CORENAME_cyles.txt.gtl
@ -1,9 +0,0 @@
-{ 
-	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
-		{
-			"name"  : "${instr.name}",
-			"size"  : ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
-		}<%}%>
-	]
-}
--- a/gen_input/templates/tcc/incl-CORENAME.h.gtl
+++ b/gen_input/templates/tcc/incl-CORENAME.h.gtl
@ -1,223 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-<% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getTypeSize(size){
-	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
-}
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#ifndef _${coreDef.name.toUpperCase()}_H_
-#define _${coreDef.name.toUpperCase()}_H_
-
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct ${coreDef.name.toLowerCase()};
-
-template <> struct traits<${coreDef.name.toLowerCase()}> {
-
-	constexpr static char const* const core_type = "${coreDef.name}";
-    
-  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
- 		{"${getRegisterNames().join("\", \"")}"}};
- 
-  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
- 		{"${getRegisterAliasNames().join("\", \"")}"}};
-
-    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
-
-    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
-
-    enum reg_e {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        ${reg.name}${it},<%
-                }
-            } else if(reg instanceof Register){ %>
-        ${reg.name},<%  
-            }
-        }%>
-        NUM_REGS,
-        NEXT_${pc.name}=NUM_REGS,
-        TRAP_STATE,
-        PENDING_TRAP,
-        MACHINE_STATE,
-        LAST_BRANCH,
-        ICOUNT<% 
-     	allRegs.each { reg -> 
-    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
-        ${reg.name} = ${aliasname}<%
-            }
-        }%>
-    };
-
-    using reg_t = uint${regDataWidth}_t;
-
-    using addr_t = uint${addrDataWidth}_t;
-
-    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
- 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
- 		{${regSizes.join(",")}}};
-
-    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
-    	{${regOffsets.join(",")}}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
-};
-
-struct ${coreDef.name.toLowerCase()}: public arch_if {
-
-    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
-    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
-    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
-    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
-
-    ${coreDef.name.toLowerCase()}();
-    ~${coreDef.name.toLowerCase()}();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-    /// deprecated
-    void get_reg(short idx, std::vector<uint8_t>& value) override {}
-    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
-    /// deprecated
-    bool get_flag(int flag) override {return false;}
-    void set_flag(int, bool value) override {};
-    /// deprecated
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    inline phys_addr_t v2p(const iss::addr_t& addr){
-        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
-        } else
-            return virt2phys(addr);
-    }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-protected:
-    struct ${coreDef.name}_regs {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
-                }
-            } else if(reg instanceof Register){ %>
-        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
-            }
-        }%>
-        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
-        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
-        uint64_t icount = 0;
-    } reg;
-
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-<%
-def fcsr = allRegs.find {it.name=='FCSR'}
-if(fcsr != null) {%>
-	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
-	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
-<%} else { %>
-	uint32_t get_fcsr(){return 0;}
-	void set_fcsr(uint32_t val){}
-<%}%>
-};
-
-}
-}            
-#endif /* _${coreDef.name.toUpperCase()}_H_ */
--- a/gen_input/templates/tcc/src-CORENAME.cpp.gtl
+++ b/gen_input/templates/tcc/src-CORENAME.cpp.gtl
@ -1,107 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
- <% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
-#include "util/ities.h"
-#include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <cstdio>
-#include <cstring>
-#include <fstream>
-
-using namespace iss::arch;
-
-constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
-
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
-    reg.icount = 0;
-}
-
-${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
-
-void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
-    reg.PC=address;
-    reg.NEXT_PC=reg.PC;
-    reg.trap_state=0;
-    reg.machine_state=0x3;
-    reg.icount=0;
-}
-
-uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
-	return reinterpret_cast<uint8_t*>(&reg);
-}
-
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
-    return phys_addr_t(pc); // change logical address to physical address
-}
-
--- a/softfloat/CMakeLists.txt
+++ b/softfloat/CMakeLists.txt
@ -8,7 +8,7 @@ project("sotfloat" VERSION 3.0.0)
 # Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0)
 set(VERSION "3e")

-include(Common)
+#include(Common)
 include(GNUInstallDirs)

 set(SPECIALIZATION RISCV)
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@ -51,12 +51,18 @@ enum riscv_csr {
    ustatus = 0x000,
    uie = 0x004,
    utvec = 0x005,
+    utvt = 0x007, //CLIC
    // User Trap Handling
    uscratch = 0x040,
    uepc = 0x041,
    ucause = 0x042,
    utval = 0x043,
    uip = 0x044,
+    uxnti = 0x045, //CLIC
+    uintstatus   = 0xCB1, // MRW Current interrupt levels (CLIC) - addr subject to change
+    uintthresh   = 0x047, // MRW Interrupt-level threshold (CLIC) - addr subject to change
+    uscratchcsw  = 0x048, // MRW Conditional scratch swap on priv mode change (CLIC)
+    uscratchcswl = 0x049, // MRW Conditional scratch swap on level change (CLIC)
    // User Floating-Point CSRs
    fflags = 0x001,
    frm = 0x002,
@ -114,7 +120,7 @@ enum riscv_csr {
    mtval = 0x343,
    mip = 0x344,
    mxnti = 0x345, //CLIC
-    mintstatus   = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
+    mintstatus   = 0xFB1, // MRW Current interrupt levels (CLIC) - addr subject to change
    mintthresh   = 0x347, // MRW Interrupt-level threshold (CLIC) - addr subject to change
    mscratchcsw  = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
    mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
@ -215,6 +221,7 @@ struct vm_info {

 struct feature_config {
    uint64_t clic_base{0xc0000000};
+    unsigned clic_int_ctl_bits{4};
    unsigned clic_num_irq{16};
    unsigned clic_num_trigger{0};
    uint64_t tcm_base{0x10000000};
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2021 MINRES Technologies GmbH
+ * Copyright (C) 2019 - 2023 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -172,14 +172,91 @@ public:
            return 0b00000000000000000001100010001000;
        }
    };
+
+    // specialization 64bit
+    template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint64_t>::value>::type> {
+    public:
+        BEGIN_BF_DECL(mstatus_t, T);
+        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
+        BF_FIELD(SD, 63, 1);
+        // value of XLEN for S-mode
+        BF_FIELD(SXL, 34, 2);
+        // value of XLEN for U-mode
+        BF_FIELD(UXL, 32, 2);
+        // Trap SRET
+        BF_FIELD(TSR, 22, 1);
+        // Timeout Wait
+        BF_FIELD(TW, 21, 1);
+        // Trap Virtual Memory
+        BF_FIELD(TVM, 20, 1);
+        // Make eXecutable Readable
+        BF_FIELD(MXR, 19, 1);
+        // permit Supervisor User Memory access
+        BF_FIELD(SUM, 18, 1);
+        // Modify PRiVilege
+        BF_FIELD(MPRV, 17, 1);
+        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
+        BF_FIELD(XS, 15, 2);
+        // floating-point unit status Off/Initial/Clean/Dirty
+        BF_FIELD(FS, 13, 2);
+        // machine previous privilege
+        BF_FIELD(MPP, 11, 2);
+        // supervisor previous privilege
+        BF_FIELD(SPP, 8, 1);
+        // previous machine interrupt-enable
+        BF_FIELD(MPIE, 7, 1);
+        // previous supervisor interrupt-enable
+        BF_FIELD(SPIE, 5, 1);
+        // previous user interrupt-enable
+        BF_FIELD(UPIE, 4, 1);
+        // machine interrupt-enable
+        BF_FIELD(MIE, 3, 1);
+        // supervisor interrupt-enable
+        BF_FIELD(SIE, 1, 1);
+        // user interrupt-enable
+        BF_FIELD(UIE, 0, 1);
+        END_BF_DECL();
+
+        mstatus_t mstatus;
+
+        static const reg_t mstatus_reset_val = 0x1800;
+
+        void write_mstatus(T val) {
+            auto mask = get_mask() &0xff; // MPP is hardcode as 0x3
+            auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
+            mstatus = new_val;
+        }
+
+        static constexpr T get_mask() {
+            //return 0x8000000f007ff9ddULL; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
+            //
+            //                +-TSR
+            //                |+-TW
+            //                ||+-TVM
+            //                |||+-MXR
+            //                ||||+-SUM
+            //                |||||+-MPRV
+            //                |||||| +-XS
+            //                |||||| | +-FS
+            //                |||||| | | +-MPP
+            //                |||||| | | |  +-SPP
+            //                |||||| | | |  |+-MPIE
+            //                ||||||/|/|/|  ||   +-MIE
+            return 0b00000000000000000001100010001000;
+        }
+    };
+
    using hart_state_type = hart_state<reg_t>;

    constexpr reg_t get_irq_mask() {
        return 0b100010001000; // only machine mode is supported
    }

+    constexpr bool has_compressed() {
+        return traits<BASE>::MISA_VAL&0b0100;
+    }
    constexpr reg_t get_pc_mask() {
-        return traits<BASE>::MISA_VAL&0b0100?~1:~3;
+        return has_compressed()?(reg_t)~1:(reg_t)~3;
    }

    riscv_hart_m_p(feature_config cfg = feature_config{});
@ -203,7 +280,7 @@ public:

    void disass_output(uint64_t pc, const std::string instr) override {
        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [s:0x{:x};c:{}]",
-                pc, instr, (reg_t)state.mstatus, this->icount + cycle_offset);
+                pc, instr, (reg_t)state.mstatus, this->reg.icount + cycle_offset);
    };

    iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
@ -231,15 +308,17 @@ protected:

        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };

-        uint64_t get_instr_word() override { return arch.instruction; }
+        uint64_t get_instr_word() override { return arch.reg.instruction; }

-        uint64_t get_instr_count() override { return arch.icount; }
+        uint64_t get_instr_count() override { return arch.reg.icount; }

-        uint64_t get_pendig_traps() override { return arch.trap_state; }
+        uint64_t get_pendig_traps() override { return arch.reg.trap_state; }

-        uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }
+        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }

-        void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+
+        bool is_branch_taken() override { return arch.reg.last_branch; };

        riscv_hart_m_p<BASE, FEAT> &arch;
    };
@ -277,7 +356,6 @@ protected:
    std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
    std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
    uint8_t clic_cfg_reg{0};
-    uint32_t clic_info_reg{0};
    std::array<uint32_t, 32> clic_inttrig_reg;
    union clic_int_reg_t {
        struct{
@ -289,6 +367,8 @@ protected:
        uint32_t raw;
    };
    std::vector<clic_int_reg_t> clic_int_reg;
+    uint8_t clic_mprev_lvl{0};
+    uint8_t clic_mact_lvl{0};

    std::vector<uint8_t> tcm;

@ -304,14 +384,16 @@ protected:
    iss::status read_time(unsigned addr, reg_t &val);
    iss::status read_status(unsigned addr, reg_t &val);
    iss::status write_status(unsigned addr, reg_t val);
+    iss::status read_cause(unsigned addr, reg_t &val);
    iss::status write_cause(unsigned addr, reg_t val);
    iss::status read_ie(unsigned addr, reg_t &val);
    iss::status write_ie(unsigned addr, reg_t val);
    iss::status read_ip(unsigned addr, reg_t &val);
    iss::status read_hartid(unsigned addr, reg_t &val);
    iss::status write_epc(unsigned addr, reg_t val);
-    iss::status write_intstatus(unsigned addr, reg_t val);
+    iss::status read_intstatus(unsigned addr, reg_t& val);
    iss::status write_intthresh(unsigned addr, reg_t val);
+    iss::status write_xtvt(unsigned addr, reg_t val);
    iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
    iss::status read_dcsr_reg(unsigned addr, reg_t &val);
    iss::status write_dcsr_reg(unsigned addr, reg_t val);
@ -337,8 +419,17 @@ protected:
    std::vector<std::function<mem_write_f>> memfn_write;
    void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
    feature_config cfg;
-    unsigned mcause_max_irq{16};
+    uint64_t mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
    inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
+    std::pair<std::function<mem_read_f>, std::function<mem_write_f>>
+    replace_mem_access(std::function<mem_read_f> rd, std::function<mem_write_f> wr){
+        std::pair<std::function<mem_read_f>, std::function<mem_write_f>> ret{hart_mem_rd_delegate, hart_mem_wr_delegate};
+        hart_mem_rd_delegate = rd;
+        hart_mem_wr_delegate = wr;
+        return ret;
+    }
+    std::function<mem_read_f> hart_mem_rd_delegate;
+    std::function<mem_write_f> hart_mem_wr_delegate;
 };

 template <typename BASE, features_e FEAT>
@ -357,7 +448,7 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
        csr_rd_cb[addr] = &this_class::read_null;
        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
-    for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
+    if(traits<BASE>::XLEN==32) for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
@ -368,37 +459,40 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
    for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
    }
-    for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
+    if(traits<BASE>::XLEN==32) for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
        //csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    // common regs
-    const std::array<unsigned, 9> addrs{{
-    	misa, mvendorid, marchid, mimpid,
-    	mepc, mtvec, mscratch, mcause, mtval
-    }};
-    for(auto addr: addrs) {
+    const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
+    for(auto addr: roaddrs) {
+        csr_rd_cb[addr] = &this_class::read_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_null;
+    }
+    const std::array<unsigned, 4> rwaddrs{{mepc, mtvec, mscratch, mtval}};
+    for(auto addr: rwaddrs) {
        csr_rd_cb[addr] = &this_class::read_csr_reg;
        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    // special handling & overrides
    csr_rd_cb[time] = &this_class::read_time;
-    csr_rd_cb[timeh] = &this_class::read_time;
+    if(traits<BASE>::XLEN==32)  csr_rd_cb[timeh] = &this_class::read_time;
    csr_rd_cb[cycle] = &this_class::read_cycle;
-    csr_rd_cb[cycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle;
    csr_rd_cb[instret] = &this_class::read_instret;
-    csr_rd_cb[instreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret;

    csr_rd_cb[mcycle] = &this_class::read_cycle;
    csr_wr_cb[mcycle] = &this_class::write_cycle;
-    csr_rd_cb[mcycleh] = &this_class::read_cycle;
-    csr_wr_cb[mcycleh] = &this_class::write_cycle;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle;
    csr_rd_cb[minstret] = &this_class::read_instret;
    csr_wr_cb[minstret] = &this_class::write_instret;
-    csr_rd_cb[minstreth] = &this_class::read_instret;
-    csr_wr_cb[minstreth] = &this_class::write_instret;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret;
    csr_rd_cb[mstatus] = &this_class::read_status;
    csr_wr_cb[mstatus] = &this_class::write_status;
+    csr_rd_cb[mcause] = &this_class::read_cause;
    csr_wr_cb[mcause] = &this_class::write_cause;
    csr_rd_cb[mtvec] = &this_class::read_tvec;
    csr_wr_cb[mepc] = &this_class::write_epc;
@ -413,22 +507,21 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
    csr_wr_cb[mimpid] = &this_class::write_null;
    if(FEAT & FEAT_CLIC) {
        csr_rd_cb[mtvt] = &this_class::read_csr_reg;
-        csr_wr_cb[mtvt] = &this_class::write_csr_reg;
-        csr_rd_cb[mxnti] = &this_class::read_csr_reg;
-        csr_wr_cb[mxnti] = &this_class::write_csr_reg;
-        csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
+        csr_wr_cb[mtvt] = &this_class::write_xtvt;
+//        csr_rd_cb[mxnti] = &this_class::read_csr_reg;
+//        csr_wr_cb[mxnti] = &this_class::write_csr_reg;
+        csr_rd_cb[mintstatus] = &this_class::read_intstatus;
        csr_wr_cb[mintstatus] = &this_class::write_null;
-        csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
-        csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
-        csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg;
-        csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
+//        csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
+//        csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
+//        csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg;
+//        csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
        csr_rd_cb[mintthresh] = &this_class::read_csr_reg;
        csr_wr_cb[mintthresh] = &this_class::write_intthresh;
-
        clic_int_reg.resize(cfg.clic_num_irq,  clic_int_reg_t{.raw=0});
        clic_cfg_reg=0x20;
-        clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq;
-        mcause_max_irq=cfg.clic_num_irq+16;
+        clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
+        csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
        insert_mem_range(cfg.clic_base, 0x5000UL,
                [this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
                [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);});
@ -457,6 +550,12 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
        csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
        csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
    }
+    hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status {
+        return this->read_mem(a, l, d);
+    };
+    hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status {
+        return this->write_mem(a, l, d);
+    };
 }

 template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT>::load_file(std::string name, int type) {
@ -554,16 +653,16 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
    try {
        switch (space) {
        case traits<BASE>::MEM: {
-            auto alignment = is_fetch(access)? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
+            auto alignment = is_fetch(access)? (has_compressed()? 2 : 4) : length;
            if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                fault_data = addr;
                if (is_debug(access)) throw trap_access(0, addr);
-                this->trap_state = (1UL << 31); // issue trap 0
+                this->reg.trap_state = (1UL << 31); // issue trap 0
                return iss::Err;
            }
            try {
                if(!is_debug(access) && (addr&(alignment-1))){
-                    this->trap_state = (1UL << 31) | 4<<16;
+                    this->reg.trap_state = (1UL << 31) | 4<<16;
                    fault_data=addr;
                    return iss::Err;
                }
@ -577,17 +676,17 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
                        auto idx = std::distance(std::begin(memfn_range), it);
                        res = memfn_read[idx](phys_addr, length, data);
                    } else
-                        res = read_mem( phys_addr, length, data);
+                        res = hart_mem_rd_delegate( phys_addr, length, data);
                } else {
-                    res = read_mem( phys_addr, length, data);
+                    res = hart_mem_rd_delegate( phys_addr, length, data);
                }
                if (unlikely(res != iss::Ok)){
-                    this->trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
+                    this->reg.trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                    fault_data=addr;
                }
                return res;
            } catch (trap_access &ta) {
-                this->trap_state = (1UL << 31) | ta.id;
+                this->reg.trap_state = (1UL << 31) | ta.id;
                fault_data=ta.addr;
                return iss::Err;
            }
@ -613,7 +712,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
        }
        return iss::Ok;
    } catch (trap_access &ta) {
-        this->trap_state = (1UL << 31) | ta.id;
+        this->reg.trap_state = (1UL << 31) | ta.id;
        fault_data=ta.addr;
        return iss::Err;
    }
@ -651,12 +750,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
            if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                fault_data = addr;
                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->trap_state = (1UL << 31); // issue trap 0
+                this->reg.trap_state = (1UL << 31); // issue trap 0
                return iss::Err;
            }
            try {
                if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
-                    this->trap_state = (1UL << 31) | 6<<16;
+                    this->reg.trap_state = (1UL << 31) | 6<<16;
                    fault_data=addr;
                    return iss::Err;
                }
@ -675,12 +774,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                    res = write_mem( phys_addr, length, data);
                }
                if (unlikely(res != iss::Ok)) {
-                    this->trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
                    fault_data=addr;
                }
                return res;
            } catch (trap_access &ta) {
-                this->trap_state = (1UL << 31) | ta.id;
+                this->reg.trap_state = (1UL << 31) | ta.id;
                fault_data=ta.addr;
                return iss::Err;
            }
@ -740,7 +839,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
        }
        return iss::Ok;
    } catch (trap_access &ta) {
-        this->trap_state = (1UL << 31) | ta.id;
+        this->reg.trap_state = (1UL << 31) | ta.id;
        fault_data=ta.addr;
        return iss::Err;
    }
@ -786,11 +885,10 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_cycle(unsigned addr, reg_t &val) {
-    auto cycle_val = this->icount + cycle_offset;
+    auto cycle_val = this->reg.icount + cycle_offset;
    if (addr == mcycle) {
        val = static_cast<reg_t>(cycle_val);
    } else if (addr == mcycleh) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
        val = static_cast<reg_t>(cycle_val >> 32);
    }
    return iss::Ok;
@ -798,8 +896,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>

 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cycle(unsigned addr, reg_t val) {
    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if (addr == mcycleh)
-            return iss::Err;
        mcycle_csr = static_cast<uint64_t>(val);
    } else {
        if (addr == mcycle) {
@ -808,38 +904,35 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
            mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff);
        }
    }
-    cycle_offset = mcycle_csr-this->icount; // TODO: relying on wrap-around
+    cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around
    return iss::Ok;
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_instret(unsigned addr, reg_t &val) {
    if ((addr&0xff) == (minstret&0xff)) {
-        val = static_cast<reg_t>(this->instret);
+        val = static_cast<reg_t>(this->reg.instret);
    } else if ((addr&0xff) == (minstreth&0xff)) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-        val = static_cast<reg_t>(this->instret >> 32);
+        val = static_cast<reg_t>(this->reg.instret >> 32);
    }
    return iss::Ok;
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_instret(unsigned addr, reg_t val) {
    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if ((addr&0xff) == (minstreth&0xff))
-            return iss::Err;
-        this->instret = static_cast<uint64_t>(val);
+        this->reg.instret = static_cast<uint64_t>(val);
    } else {
        if ((addr&0xff) == (minstret&0xff)) {
-            this->instret = (this->instret & 0xffffffff00000000) + val;
+            this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val;
        } else  {
-            this->instret = (static_cast<uint64_t>(val)<<32) + (this->instret & 0xffffffff);
+            this->reg.instret = (static_cast<uint64_t>(val)<<32) + (this->reg.instret & 0xffffffff);
        }
    }
-    this->instret--;
+    this->reg.instret--;
    return iss::Ok;
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_time(unsigned addr, reg_t &val) {
-    uint64_t time_val = this->icount / (100000000 / 32768 - 1); //-> ~3052;
+    uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
    if (addr == time) {
        val = static_cast<reg_t>(time_val);
    } else if (addr == timeh) {
@ -850,7 +943,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_tvec(unsigned addr, reg_t &val) {
-    val = csr[addr] & ~2;
+    val = FEAT & features_e::FEAT_CLIC? csr[addr] : csr[addr] & ~2;
    return iss::Ok;
 }

@ -865,8 +958,28 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
    return iss::Ok;
 }

+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_cause(unsigned addr, reg_t &val) {
+    if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) {
+        val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16));
+        val |= clic_mprev_lvl<<16;
+        val |= state.mstatus.MPIE<<27;
+        val |= state.mstatus.MPP<<28;
+    } else
+        val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
+    return iss::Ok;
+}
+
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
-    csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1))| (mcause_max_irq-1));
+    if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) {
+        auto mask = ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16));
+        csr[addr] = (val & mask) | (csr[addr] & ~mask);
+        clic_mprev_lvl = ((val>>16)&0xff) | (1<<(8-cfg. clic_int_ctl_bits)) - 1;
+        state.mstatus.MPIE=(val>>27)&0x1;
+        state.mstatus.MPP=(val>>28)&0x3;
+    } else {
+        auto mask = ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
+        csr[addr] = (val & mask) | (csr[addr] & ~mask);
+    }
    return iss::Ok;
 }

@ -938,27 +1051,27 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
    return iss::Ok;
 }

+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::read_intstatus(unsigned addr, reg_t& val) {
+	val = (clic_mact_lvl&0xff) <<24;
+    return iss::Ok;
+}
+
 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
-    csr[addr]= val &0xff;
+    csr[addr]= (val &0xff) | (1<<(cfg.clic_int_ctl_bits)) - 1;
+    return iss::Ok;
+}
+
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::write_xtvt(unsigned addr, reg_t val) {
+    csr[addr]= val & ~0x3fULL;
    return iss::Ok;
 }

 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
    switch (paddr.val) {
-    case 0x0200BFF8: { // CLINT base, mtime reg
-        if (sizeof(reg_t) < length) return iss::Err;
-        reg_t time_val;
-        this->read_csr(time, time_val);
-        std::copy((uint8_t *)&time_val, ((uint8_t *)&time_val) + length, data);
-    } break;
-    case 0x10008000: {
-        const mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        uint64_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(p.data() + offs, p.data() + offs + length, data);
-        if (this->icount > 30000) data[3] |= 0x80;
-    } break;
    default: {
        for(auto offs=0U; offs<length; ++offs) {
            *(data + offs)=mem[(paddr.val+offs)%mem.size()];
@ -971,29 +1084,13 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned len
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
    switch (paddr.val) {
-    case 0x10013000: // UART0 base, TXFIFO reg
-    case 0x10023000: // UART1 base, TXFIFO reg
-        uart_buf << (char)data[0];
+    case 0xFFFF0000: // UART0 base, TXFIFO reg
        if (((char)data[0]) == '\n' || data[0] == 0) {
-            LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send '"<<uart_buf.str()<<"'";
-            std::cout << uart_buf.str();
+            LOG(INFO)<<"UART"<<((paddr.val>>12)&0x3)<<" send '"<<uart_buf.str()<<"'";
            uart_buf.str("");
-        }
+        } else if(((char)data[0]) != '\r')
+            uart_buf << (char)data[0];
        break;
-    case 0x10008000: { // HFROSC base, hfrosccfg reg
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        size_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(data, data + length, p.data() + offs);
-        uint8_t &x = *(p.data() + offs + 3);
-        if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
-    } break;
-    case 0x10008008: { // HFROSC base, pllcfg reg
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        size_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(data, data + length, p.data() + offs);
-        uint8_t &x = *(p.data() + offs + 3);
-        x |= 0x80; // set pll lock upon writing
-    } break;
    default: {
        mem_type::page_type &p = mem(paddr.val / mem.page_size);
        std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
@ -1015,7 +1112,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
                            LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
                                      << "), stopping simulation";
                        }
-                        this->trap_state=std::numeric_limits<uint32_t>::max();
+                        this->reg.trap_state=std::numeric_limits<uint32_t>::max();
                        this->interrupt_sim=hostvar;
                        break;
                        //throw(iss::simulation_stopped(hostvar));
@ -1049,8 +1146,6 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length
    if(addr==cfg.clic_base) { // cliccfg
        *data=clic_cfg_reg;
        for(auto i=1; i<length; ++i) *(data+i)=0;
-    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+8)){ // clicinfo
-        read_reg_uint32(addr, clic_info_reg, data, length);
    } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
        auto offset = ((addr&0x7fff)-0x40)/4;
        read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
@ -1066,10 +1161,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length
 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
    if(addr==cfg.clic_base) { // cliccfg
-        clic_cfg_reg = *data;
-        clic_cfg_reg&= 0x7e;
-//    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+4)){ // clicinfo
-//        write_uint32(addr, clic_info_reg, data, length);
+        clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e);
    } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
        auto offset = ((addr&0x7fff)-0x40)/4;
        write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
@ -1087,6 +1179,7 @@ template <typename BASE, features_e FEAT> inline void riscv_hart_m_p<BASE, FEAT>
 }

 template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check_interrupt() {
+    //TODO: Implement CLIC functionality
    //auto ideleg = csr[mideleg];
    // Multiple simultaneous interrupts and traps at the same privilege level are
    // handled in the following decreasing priority order:
@ -1104,14 +1197,14 @@ template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check
        	enabled_interrupts >>= 1;
        	res++;
        }
-        this->pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
+        this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
    }
 }

 template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
    // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
    // calculate and write mcause val
-    auto trap_id = bit_sub<0, 16>(flags);
+    auto const trap_id = bit_sub<0, 16>(flags);
    auto cause = bit_sub<16, 15>(flags);
    // calculate effective privilege level
    unsigned new_priv = PRIV_M;
@ -1131,7 +1224,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
            csr[mtval] = static_cast<reg_t>(addr);
            break;
        case 2:
-            csr[mtval] = (instr & 0x3)==3?instr:instr&0xffff;
+            csr[mtval] = (!has_compressed() || (instr & 0x3)==3)?instr:instr&0xffff;
            break;
        case 3:
            if((FEAT & FEAT_DEBUG) && (csr[dcsr] & 0x8000)) {
@ -1152,7 +1245,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
        fault_data = 0;
    } else {
        csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt
-        this->pending_trap = 0;
+        this->reg.pending_trap = 0;
    }
    csr[mcause] = (trap_id << (traits<BASE>::XLEN-1)) + cause;
    // update mstatus
@ -1167,14 +1260,22 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
    state.mstatus.MIE = false;

    // get trap vector
-    auto ivec = csr[mtvec];
-    // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
-    // bits in mtvec
-    this->reg.NEXT_PC = ivec & ~0x3UL;
-    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
+    auto xtvec = csr[mtvec];
+    // calculate adds// set NEXT_PC to trap addressess to jump to based on MODE
+    if((FEAT & features_e::FEAT_CLIC) && trap_id!=0 && (xtvec & 0x3UL)==3UL) {
+        reg_t data;
+        auto ret = read(address_type::LOGICAL, access_type::READ, 0, csr[mtvt], sizeof(reg_t), reinterpret_cast<uint8_t*>(&data));
+        if(ret == iss::Err)
+            return this->reg.PC;
+        this->reg.NEXT_PC = data;
+    } else {
+        // bits in mtvec
+        this->reg.NEXT_PC = xtvec & ~0x3UL;
+        if ((xtvec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
+    }
    // reset trap state
    this->reg.PRIV = new_priv;
-    this->trap_state = 0;
+    this->reg.trap_state = 0;
    std::array<char, 32> buffer;
 #if defined(_MSC_VER)
    sprintf(buffer.data(), "0x%016llx", addr);
@ -1195,7 +1296,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::l
    this->reg.NEXT_PC = csr[mepc] & get_pc_mask();
    CLOG(INFO, disass) << "Executing xRET";
    check_interrupt();
-    this->trap_state = this->pending_trap;
+    this->reg.trap_state = this->reg.pending_trap;
    return this->reg.NEXT_PC;
 }

--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, 2021 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -307,7 +307,7 @@ public:

    void disass_output(uint64_t pc, const std::string instr) override {
        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]",
-                pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->icount + cycle_offset);
+                pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.icount + cycle_offset);
    };

    iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
@ -316,6 +316,9 @@ public:
        csr[addr & csr.page_addr_mask] = val;
    }

+    void set_irq_num(unsigned i) {
+        mcause_max_irq=1<<util::ilog2(i);
+    }
 protected:
    struct riscv_instrumentation_if : public iss::instrumentation_if {

@ -328,19 +331,21 @@ protected:
         */
        const std::string core_type_name() const override { return traits<BASE>::core_type; }

-        virtual uint64_t get_pc() { return arch.get_pc(); };
+        uint64_t get_pc() override { return arch.reg.PC; };

-        virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };

-        uint64_t get_instr_word() override { return arch.instruction; }
+        uint64_t get_instr_word() override { return arch.reg.instruction; }

-        uint64_t get_instr_count() { return arch.icount; }
+        uint64_t get_instr_count() override { return arch.reg.icount; }

-        uint64_t get_pendig_traps() override { return arch.trap_state; }
+        uint64_t get_pendig_traps() override { return arch.reg.trap_state; }

-        uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }
+        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }

-        virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+
+        bool is_branch_taken() override { return arch.reg.last_branch; };

        riscv_hart_msu_vp<BASE> &arch;
    };
@ -379,16 +384,17 @@ protected:
    std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
    std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;

-private:
-    iss::status read_reg(unsigned addr, reg_t &val);
-    iss::status write_reg(unsigned addr, reg_t val);
+    std::vector<uint8_t> tcm;
+
+    iss::status read_csr_reg(unsigned addr, reg_t &val);
+    iss::status write_csr_reg(unsigned addr, reg_t val);
    iss::status read_null(unsigned addr, reg_t &val);
    iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;}
    iss::status read_cycle(unsigned addr, reg_t &val);
    iss::status write_cycle(unsigned addr, reg_t val);
    iss::status read_instret(unsigned addr, reg_t &val);
    iss::status write_instret(unsigned addr, reg_t val);
-    iss::status read_mtvec(unsigned addr, reg_t &val);
+    iss::status read_tvec(unsigned addr, reg_t &val);
    iss::status read_time(unsigned addr, reg_t &val);
    iss::status read_status(unsigned addr, reg_t &val);
    iss::status write_status(unsigned addr, reg_t val);
@ -396,6 +402,8 @@ private:
    iss::status read_ie(unsigned addr, reg_t &val);
    iss::status write_ie(unsigned addr, reg_t val);
    iss::status read_ip(unsigned addr, reg_t &val);
+    iss::status write_ideleg(unsigned addr, reg_t val);
+    iss::status write_edeleg(unsigned addr, reg_t val);
    iss::status read_hartid(unsigned addr, reg_t &val);
    iss::status write_epc(unsigned addr, reg_t val);
    iss::status read_satp(unsigned addr, reg_t &val);
@ -415,7 +423,6 @@ private:

    reg_t mhartid_reg{0x0};

-protected:
    void check_interrupt();
 };

@ -432,22 +439,22 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
    uart_buf.str("");
    for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
+        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
+        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_reg;
+        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
    }
    for (unsigned addr = cycleh; addr <= hpmcounter31h; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
-        //csr_wr_cb[addr] = &this_class::write_reg;
+        //csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    // common regs
    const std::array<unsigned, 22> addrs{{
@ -457,25 +464,25 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
        uepc, utvec, uscratch, ucause, utval, uscratch
    }};
    for(auto addr: addrs) {
-        csr_rd_cb[addr] = &this_class::read_reg;
-        csr_wr_cb[addr] = &this_class::write_reg;
+        csr_rd_cb[addr] = &this_class::read_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    // special handling & overrides
    csr_rd_cb[time] = &this_class::read_time;
-    csr_rd_cb[timeh] = &this_class::read_time;
+    if(traits<BASE>::XLEN==32)  csr_rd_cb[timeh] = &this_class::read_time;
    csr_rd_cb[cycle] = &this_class::read_cycle;
-    csr_rd_cb[cycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle;
    csr_rd_cb[instret] = &this_class::read_instret;
-    csr_rd_cb[instreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret;

    csr_rd_cb[mcycle] = &this_class::read_cycle;
    csr_wr_cb[mcycle] = &this_class::write_cycle;
-    csr_rd_cb[mcycleh] = &this_class::read_cycle;
-    csr_wr_cb[mcycleh] = &this_class::write_cycle;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle;
    csr_rd_cb[minstret] = &this_class::read_instret;
    csr_wr_cb[minstret] = &this_class::write_instret;
-    csr_rd_cb[minstreth] = &this_class::read_instret;
-    csr_wr_cb[minstreth] = &this_class::write_instret;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret;
    csr_rd_cb[mstatus] = &this_class::read_status;
    csr_wr_cb[mstatus] = &this_class::write_status;
    csr_wr_cb[mcause] = &this_class::write_cause;
@ -525,10 +532,10 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
    if (fp) {
        std::array<char, 5> buf;
        auto n = fread(buf.data(), 1, 4, fp);
+        fclose(fp);
        if (n != 4) throw std::runtime_error("input file has insufficient size");
        buf[4] = 0;
        if (strcmp(buf.data() + 1, "ELF") == 0) {
-            fclose(fp);
            // Create elfio reader
            ELFIO::elfio reader;
            // Load ELF data
@ -547,7 +554,7 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
                            traits<BASE>::MEM, pseg->get_physical_address(),
                            fsize, reinterpret_cast<const uint8_t *const>(seg_data));
                    if (res != iss::Ok)
-                        LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex
+                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
                                   << pseg->get_physical_address();
                }
            }
@ -605,12 +612,12 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
            if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                fault_data = addr;
                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->reg.trap_state = (1 << 31); // issue trap 0
                return iss::Err;
            }
            try {
                if(!is_debug(access)  && (addr&(alignment-1))){
-                    this->trap_state = 1<<31 | 4<<16;
+                    this->reg.trap_state = 1<<31 | 4<<16;
                    fault_data=addr;
                    return iss::Err;
                }
@ -629,12 +636,12 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
                        read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
                        read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
                if (unlikely(res != iss::Ok)){
-                	this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                	this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
                    fault_data=addr;
                }
                return res;
            } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->reg.trap_state = (1 << 31) | ta.id;
                fault_data=ta.addr;
                return iss::Err;
            }
@ -650,7 +657,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
            case 3: { // SFENCE:VMA upper
                auto tvm = state.mstatus.TVM;
                if (this->reg.PRIV == PRIV_S & tvm != 0) {
-                    this->trap_state = (1 << 31) | (2 << 16);
+                    this->reg.trap_state = (1 << 31) | (2 << 16);
                    this->fault_data = this->reg.PC;
                    return iss::Err;
                }
@ -671,7 +678,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
        }
        return iss::Ok;
    } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->reg.trap_state = (1UL << 31) | ta.id;
        fault_data=ta.addr;
        return iss::Err;
    }
@ -709,7 +716,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
            if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                fault_data = addr;
                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->reg.trap_state = (1 << 31); // issue trap 0
                return iss::Err;
            }
            try {
@ -728,12 +735,12 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                        write_mem(phys_addr_t{access, space, addr}, length, data):
                        write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
                if (unlikely(res != iss::Ok)) {
-                    this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
                    fault_data=addr;
                }
                return res;
            } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->reg.trap_state = (1UL << 31) | ta.id;
                fault_data=ta.addr;
                return iss::Err;
            }
@ -782,7 +789,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                ptw.clear();
                auto tvm = state.mstatus.TVM;
                if (this->reg.PRIV == PRIV_S & tvm != 0) {
-                    this->trap_state = (1 << 31) | (2 << 16);
+                    this->reg.trap_state = (1 << 31) | (2 << 16);
                    this->fault_data = this->reg.PC;
                    return iss::Err;
                }
@ -798,7 +805,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
        }
        return iss::Ok;
    } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->reg.trap_state = (1UL << 31) | ta.id;
        fault_data=ta.addr;
        return iss::Err;
    }
@ -843,8 +850,8 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_reg(unsigned
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
-    auto cycle_val = this->icount + cycle_offset;
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigned addr, reg_t &val) {
+    auto cycle_val = this->reg.icount + cycle_offset;
    if (addr == mcycle) {
        val = static_cast<reg_t>(cycle_val);
    } else if (addr == mcycleh) {
@ -854,10 +861,8 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned a
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned addr, reg_t val) {
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_cycle(unsigned addr, reg_t val) {
    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if (addr == mcycleh)
-            return iss::Err;
        mcycle_csr = static_cast<uint64_t>(val);
    } else {
        if (addr == mcycle) {
@ -866,24 +871,21 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned
            mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff);
        }
    }
-    cycle_offset = mcycle_csr-this->icount; // TODO: relying on wrap-around
+    cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned addr, reg_t &val) {
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_instret(unsigned addr, reg_t &val) {
    if ((addr&0xff) == (minstret&0xff)) {
        val = static_cast<reg_t>(this->reg.instret);
    } else if ((addr&0xff) == (minstreth&0xff)) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
        val = static_cast<reg_t>(this->reg.instret >> 32);
    }
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigned addr, reg_t val) {
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_instret(unsigned addr, reg_t val) {
    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if ((addr&0xff) == (minstreth&0xff))
-            return iss::Err;
        this->reg.instret = static_cast<uint64_t>(val);
    } else {
        if ((addr&0xff) == (minstret&0xff)) {
@ -896,8 +898,8 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigne
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
-    uint64_t time_val = this->icount / (100000000 / 32768 - 1); //-> ~3052;
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned addr, reg_t &val) {
+    uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
    if (addr == time) {
        val = static_cast<reg_t>(time_val);
    } else if (addr == timeh) {
@ -907,7 +909,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned ad
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_tvec(unsigned addr, reg_t &val) {
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_tvec(unsigned addr, reg_t &val) {
    val = csr[addr] & ~2;
    return iss::Ok;
 }
@ -966,7 +968,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_epc(unsigned
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_satp(unsigned addr, reg_t &val) {
    reg_t tvm = state.mstatus.TVM;
    if (this->reg.PRIV == PRIV_S & tvm != 0) {
-        this->trap_state = (1 << 31) | (2 << 16);
+        this->reg.trap_state = (1 << 31) | (2 << 16);
        this->fault_data = this->reg.PC;
        return iss::Err;
    }
@ -977,7 +979,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_satp(unsigned
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_satp(unsigned addr, reg_t val) {
    reg_t tvm = state.mstatus.TVM;
    if (this->reg.PRIV == PRIV_S & tvm != 0) {
-        this->trap_state = (1 << 31) | (2 << 16);
+        this->reg.trap_state = (1 << 31) | (2 << 16);
        this->fault_data = this->reg.PC;
        return iss::Err;
    }
@ -1022,18 +1024,6 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_fcsr(unsigne
 template <typename BASE>
 iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
    switch (paddr.val) {
-    case 0x0200BFF8: { // CLINT base, mtime reg
-        if (sizeof(reg_t) < length) return iss::Err;
-        reg_t time_val;
-        this->read_csr(time, time_val);
-        std::copy((uint8_t *)&time_val, ((uint8_t *)&time_val) + length, data);
-    } break;
-    case 0x10008000: {
-        const mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        uint64_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(p.data() + offs, p.data() + offs + length, data);
-        if (this->icount > 30000) data[3] |= 0x80;
-    } break;
    default: {
        for(auto offs=0U; offs<length; ++offs) {
            *(data + offs)=mem[(paddr.val+offs)%mem.size()];
@ -1046,30 +1036,13 @@ iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length
 template <typename BASE>
 iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
    switch (paddr.val) {
-    case 0x10013000: // UART0 base, TXFIFO reg
-    case 0x10023000: // UART1 base, TXFIFO reg
-        uart_buf << (char)data[0];
+    case 0xFFFF0000: // UART0 base, TXFIFO reg
        if (((char)data[0]) == '\n' || data[0] == 0) {
-            // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
-            // '"<<uart_buf.str()<<"'";
-            std::cout << uart_buf.str();
+            LOG(INFO)<<"UART"<<((paddr.val>>12)&0x3)<<" send '"<<uart_buf.str()<<"'";
            uart_buf.str("");
-        }
+        } else if(((char)data[0]) != '\r')
+            uart_buf << (char)data[0];
        break;
-    case 0x10008000: { // HFROSC base, hfrosccfg reg
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        size_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(data, data + length, p.data() + offs);
-        uint8_t &x = *(p.data() + offs + 3);
-        if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
-    } break;
-    case 0x10008008: { // HFROSC base, pllcfg reg
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        size_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(data, data + length, p.data() + offs);
-        uint8_t &x = *(p.data() + offs + 3);
-        x |= 0x80; // set pll lock upon writing
-    } break;
    default: {
        mem_type::page_type &p = mem(paddr.val / mem.page_size);
        std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
@ -1091,7 +1064,7 @@ iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned lengt
                            LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
                                      << "), stopping simulation";
                        }
-                        this->trap_state=std::numeric_limits<uint32_t>::max();
+                        this->reg.trap_state=std::numeric_limits<uint32_t>::max();
                        this->interrupt_sim=hostvar;
                        break;
                        //throw(iss::simulation_stopped(hostvar));
@ -1160,7 +1133,7 @@ template <typename BASE> void riscv_hart_msu_vp<BASE>::check_interrupt() {
    if (enabled_interrupts != 0) {
        int res = 0;
        while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++;
-        this->pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
+        this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
    }
 }

@ -1261,6 +1234,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
    auto cur_priv = this->reg.PRIV;
    // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
    // calculate and write mcause val
+    if(flags==std::numeric_limits<uint64_t>::max()) flags=this->reg.trap_state;
    auto trap_id = bit_sub<0, 16>(flags);
    auto cause = bit_sub<16, 15>(flags);
    if (trap_id == 0 && cause == 11) cause = 0x8 + cur_priv; // adjust environment call cause
@ -1304,7 +1278,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
        if (cur_priv != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0)
            new_priv = (csr[sideleg] >> cause) & 0x1 ? PRIV_U : PRIV_S;
        csr[uepc | (new_priv << 8)] = this->reg.NEXT_PC; // store next address if interrupt
-        this->pending_trap = 0;
+        this->reg.pending_trap = 0;
    }
    size_t adr = ucause | (new_priv << 8);
    csr[adr] = (trap_id << 31) + cause;
@ -1349,7 +1323,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
                       << lvl[cur_priv] << " to " << lvl[new_priv];
    // reset trap state
    this->reg.PRIV = new_priv;
-    this->trap_state = 0;
+    this->reg.trap_state = 0;
    update_vm_info();
    return this->reg.NEXT_PC;
 }
@ -1361,7 +1335,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::leave_trap(uint64_t f

    auto tsr = state.mstatus.TSR;
    if (cur_priv == PRIV_S && inst_priv == PRIV_S && tsr != 0) {
-        this->trap_state = (1 << 31) | (2 << 16);
+        this->reg.trap_state = (1 << 31) | (2 << 16);
        this->fault_data = this->reg.PC;
        return this->reg.PC;
    }
@ -1400,7 +1374,7 @@ template <typename BASE> void riscv_hart_msu_vp<BASE>::wait_until(uint64_t flags
    auto status = state.mstatus;
    auto tw = status.TW;
    if (this->reg.PRIV == PRIV_S && tw != 0) {
-        this->trap_state = (1 << 31) | (2 << 16);
+        this->reg.trap_state = (1 << 31) | (2 << 16);
        this->fault_data = this->reg.PC;
    }
 }
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2021 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -181,6 +181,89 @@ public:
 #endif
        }
    };
+
+    // specialization 64bit
+    template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint64_t>::value>::type> {
+    public:
+        BEGIN_BF_DECL(mstatus_t, T);
+        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
+        BF_FIELD(SD, 63, 1);
+        // value of XLEN for S-mode
+        BF_FIELD(SXL, 34, 2);
+        // value of XLEN for U-mode
+        BF_FIELD(UXL, 32, 2);
+        // Trap SRET
+        BF_FIELD(TSR, 22, 1);
+        // Timeout Wait
+        BF_FIELD(TW, 21, 1);
+        // Trap Virtual Memory
+        BF_FIELD(TVM, 20, 1);
+        // Make eXecutable Readable
+        BF_FIELD(MXR, 19, 1);
+        // permit Supervisor User Memory access
+        BF_FIELD(SUM, 18, 1);
+        // Modify PRiVilege
+        BF_FIELD(MPRV, 17, 1);
+        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
+        BF_FIELD(XS, 15, 2);
+        // floating-point unit status Off/Initial/Clean/Dirty
+        BF_FIELD(FS, 13, 2);
+        // machine previous privilege
+        BF_FIELD(MPP, 11, 2);
+        // supervisor previous privilege
+        BF_FIELD(SPP, 8, 1);
+        // previous machine interrupt-enable
+        BF_FIELD(MPIE, 7, 1);
+        // previous supervisor interrupt-enable
+        BF_FIELD(SPIE, 5, 1);
+        // previous user interrupt-enable
+        BF_FIELD(UPIE, 4, 1);
+        // machine interrupt-enable
+        BF_FIELD(MIE, 3, 1);
+        // supervisor interrupt-enable
+        BF_FIELD(SIE, 1, 1);
+        // user interrupt-enable
+        BF_FIELD(UIE, 0, 1);
+        END_BF_DECL();
+
+        mstatus_t mstatus;
+
+        static const reg_t mstatus_reset_val = 0x1800;
+
+        void write_mstatus(T val, unsigned priv_lvl) {
+            auto mask = get_mask(priv_lvl);
+            auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
+            mstatus = new_val;
+        }
+
+        static constexpr uint64_t get_mask(unsigned priv_lvl) {
+#if __cplusplus < 201402L
+            return priv_lvl == PRIV_U ? 0x011ULL : priv_lvl == PRIV_S ? 0x000de133ULL : 0x007ff9ddULL;
+#else
+            switch (priv_lvl) {
+            case PRIV_U: return 0x00000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001
+            default:
+            //       +-SD
+            //       |        +-TSR
+            //       |        |+-TW
+            //       |        ||+-TVM
+            //       |        |||+-MXR
+            //       |        ||||+-SUM
+            //       |        |||||+-MPRV
+            //       |        |||||| +-XS
+            //       |        |||||| | +-FS
+            //       |        |||||| | | +-MPP
+            //       |        |||||| | | |  +-SPP
+            //       |        |||||| | | |  |+-MPIE
+            //       |        |||||| | | |  ||  +-UPIE
+            //       |        ||||||/|/|/|  ||  |+-MIE
+            //       |        ||||||/|/|/|  ||  ||  +-UIE
+            return 0b00000000000000000001100010011001;
+            }
+#endif
+        }
+    };
+
    using hart_state_type = hart_state<reg_t>;

    constexpr reg_t get_irq_mask(size_t mode) {
@ -193,11 +276,15 @@ public:
        return m[mode];
    }

+    constexpr bool has_compressed() {
+        return traits<BASE>::MISA_VAL&0b0100;
+    }
    constexpr reg_t get_pc_mask() {
-        return traits<BASE>::MISA_VAL&0b0100?~1:~3;
+        return has_compressed()?~1:~3;
    }

    riscv_hart_mu_p(feature_config cfg = feature_config{});
+    
    virtual ~riscv_hart_mu_p() = default;

    void reset(uint64_t address) override;
@ -218,7 +305,7 @@ public:

    void disass_output(uint64_t pc, const std::string instr) override {
        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]",
-                pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->icount + cycle_offset);
+                pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.icount + cycle_offset);
    };

    iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
@ -246,15 +333,17 @@ protected:

        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };

-        uint64_t get_instr_word() override { return arch.instruction; }
+        uint64_t get_instr_word() override { return arch.reg.instruction; }

-        uint64_t get_instr_count() override { return arch.icount; }
+        uint64_t get_instr_count() override { return arch.reg.icount; }

-        uint64_t get_pendig_traps() override { return arch.trap_state; }
+        uint64_t get_pendig_traps() override { return arch.reg.trap_state; }

-        uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }
+        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }

-        void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+
+        bool is_branch_taken() override { return arch.reg.last_branch; };

        riscv_hart_mu_p<BASE, FEAT> &arch;
    };
@ -292,7 +381,6 @@ protected:
    std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
    std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
    uint8_t clic_cfg_reg{0};
-    uint32_t clic_info_reg{0};
    std::array<uint32_t, 32> clic_inttrig_reg;
    union clic_int_reg_t {
        struct{
@ -304,6 +392,8 @@ protected:
        uint32_t raw;
    };
    std::vector<clic_int_reg_t> clic_int_reg;
+    uint8_t clic_mprev_lvl{0}, clic_uprev_lvl{0};
+    uint8_t clic_mact_lvl{0}, clic_uact_lvl{0};

    std::vector<uint8_t> tcm;

@ -319,6 +409,7 @@ protected:
    iss::status read_time(unsigned addr, reg_t &val);
    iss::status read_status(unsigned addr, reg_t &val);
    iss::status write_status(unsigned addr, reg_t val);
+    iss::status read_cause(unsigned addr, reg_t &val);
    iss::status write_cause(unsigned addr, reg_t val);
    iss::status read_ie(unsigned addr, reg_t &val);
    iss::status write_ie(unsigned addr, reg_t val);
@ -327,8 +418,9 @@ protected:
    iss::status write_edeleg(unsigned addr, reg_t val);
    iss::status read_hartid(unsigned addr, reg_t &val);
    iss::status write_epc(unsigned addr, reg_t val);
-    iss::status write_intstatus(unsigned addr, reg_t val);
+    iss::status read_intstatus(unsigned addr, reg_t& val);
    iss::status write_intthresh(unsigned addr, reg_t val);
+    iss::status write_xtvt(unsigned addr, reg_t val);
    iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
    iss::status read_dcsr_reg(unsigned addr, reg_t &val);
    iss::status write_dcsr_reg(unsigned addr, reg_t val);
@ -355,8 +447,18 @@ protected:
    std::vector<std::function<mem_write_f>> memfn_write;
    void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
    feature_config cfg;
-    unsigned mcause_max_irq{16};
+    uint64_t mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
    inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
+
+    std::pair<std::function<mem_read_f>, std::function<mem_write_f>>
+    replace_mem_access(std::function<mem_read_f> rd, std::function<mem_write_f> wr){
+        std::pair<std::function<mem_read_f>, std::function<mem_write_f>> ret{hart_mem_rd_delegate, hart_mem_wr_delegate};
+        hart_mem_rd_delegate = rd;
+        hart_mem_wr_delegate = wr;
+        return ret;
+    }
+    std::function<mem_read_f> hart_mem_rd_delegate;
+    std::function<mem_write_f> hart_mem_wr_delegate;
 };

 template <typename BASE, features_e FEAT>
@ -375,7 +477,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
        csr_rd_cb[addr] = &this_class::read_null;
        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
-    for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
+    if(traits<BASE>::XLEN==32) for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
@ -386,38 +488,43 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
    for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
    }
-    for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
+    if(traits<BASE>::XLEN==32) for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
        //csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    // common regs
-    const std::array<unsigned, 14> addrs{{
-        misa, mvendorid, marchid, mimpid,
-        mepc, mtvec, mscratch, mcause, mtval,
-        uepc, utvec, uscratch, ucause, utval,
+    const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
+    for(auto addr: roaddrs) {
+        csr_rd_cb[addr] = &this_class::read_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_null;
+    }
+    const std::array<unsigned, 8> rwaddrs{{
+        mepc, mtvec, mscratch, mtval,
+        uepc, utvec, uscratch, utval,
    }};
-    for(auto addr: addrs) {
+    for(auto addr: rwaddrs) {
        csr_rd_cb[addr] = &this_class::read_csr_reg;
        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    // special handling & overrides
    csr_rd_cb[time] = &this_class::read_time;
-    csr_rd_cb[timeh] = &this_class::read_time;
+    if(traits<BASE>::XLEN==32)  csr_rd_cb[timeh] = &this_class::read_time;
    csr_rd_cb[cycle] = &this_class::read_cycle;
-    csr_rd_cb[cycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle;
    csr_rd_cb[instret] = &this_class::read_instret;
-    csr_rd_cb[instreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret;

    csr_rd_cb[mcycle] = &this_class::read_cycle;
    csr_wr_cb[mcycle] = &this_class::write_cycle;
-    csr_rd_cb[mcycleh] = &this_class::read_cycle;
-    csr_wr_cb[mcycleh] = &this_class::write_cycle;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle;
    csr_rd_cb[minstret] = &this_class::read_instret;
    csr_wr_cb[minstret] = &this_class::write_instret;
-    csr_rd_cb[minstreth] = &this_class::read_instret;
-    csr_wr_cb[minstreth] = &this_class::write_instret;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret;
    csr_rd_cb[mstatus] = &this_class::read_status;
    csr_wr_cb[mstatus] = &this_class::write_status;
+    csr_rd_cb[mcause] = &this_class::read_cause;
    csr_wr_cb[mcause] = &this_class::write_cause;
    csr_rd_cb[mtvec] = &this_class::read_tvec;
    csr_wr_cb[mepc] = &this_class::write_epc;
@ -438,7 +545,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
            csr_rd_cb[i] = &this_class::read_csr_reg;
            csr_wr_cb[i] = &this_class::write_csr_reg;
        }
-        for(size_t i=pmpcfg0; i<=pmpcfg3; ++i){
+        for(size_t i=pmpcfg0; i<pmpcfg0+16/sizeof(reg_t); ++i){
            csr_rd_cb[i] = &this_class::read_csr_reg;
            csr_wr_cb[i] = &this_class::write_pmpcfg_reg;
        }
@ -455,27 +562,37 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
        csr_wr_cb[uepc] = &this_class::write_epc;
        csr_rd_cb[ustatus] = &this_class::read_status;
        csr_wr_cb[ustatus] = &this_class::write_status;
+        csr_rd_cb[ucause] = &this_class::read_cause;
        csr_wr_cb[ucause] = &this_class::write_cause;
        csr_rd_cb[utvec] = &this_class::read_tvec;
    }
    if(FEAT & FEAT_CLIC) {
        csr_rd_cb[mtvt] = &this_class::read_csr_reg;
-        csr_wr_cb[mtvt] = &this_class::write_csr_reg;
-        csr_rd_cb[mxnti] = &this_class::read_csr_reg;
-        csr_wr_cb[mxnti] = &this_class::write_csr_reg;
-        csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
+        csr_wr_cb[mtvt] = &this_class::write_xtvt;
+//        csr_rd_cb[mxnti] = &this_class::read_csr_reg;
+//        csr_wr_cb[mxnti] = &this_class::write_csr_reg;
+        csr_rd_cb[mintstatus] = &this_class::read_intstatus;
        csr_wr_cb[mintstatus] = &this_class::write_null;
-        csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
-        csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
-        csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg;
-        csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
+//        csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
+//        csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
+//        csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg;
+//        csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
        csr_rd_cb[mintthresh] = &this_class::read_csr_reg;
        csr_wr_cb[mintthresh] = &this_class::write_intthresh;
-
+        if(FEAT & FEAT_EXT_N){
+            csr_rd_cb[utvt] = &this_class::read_csr_reg;
+            csr_wr_cb[utvt] = &this_class::write_xtvt;
+            csr_rd_cb[uintstatus] = &this_class::read_intstatus;
+            csr_wr_cb[uintstatus] = &this_class::write_null;
+            csr_rd_cb[uintthresh] = &this_class::read_csr_reg;
+            csr_wr_cb[uintthresh] = &this_class::write_intthresh;
+        }
        clic_int_reg.resize(cfg.clic_num_irq,  clic_int_reg_t{.raw=0});
-        clic_cfg_reg=0x20;
-        clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq;
-        mcause_max_irq=cfg.clic_num_irq+16;
+        clic_cfg_reg=0x30;
+        clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
+        clic_uact_lvl = clic_uprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
+        csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
+        csr[uintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
        insert_mem_range(cfg.clic_base, 0x5000UL,
                [this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
                [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);});
@ -504,6 +621,12 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
        csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
        csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
    }
+    hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status {
+        return this->read_mem(a, l, d);
+    };
+    hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status {
+        return this->write_mem(a, l, d);
+    };
 }

 template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT>::load_file(std::string name, int type) {
@ -604,9 +727,10 @@ template <typename BASE, features_e FEAT> bool riscv_hart_mu_p<BASE, FEAT>::pmp_
    constexpr auto PMP_NAPOT =0x3U;
    reg_t base = 0;
    auto any_active = false;
+    auto const cfg_reg_size=sizeof(reg_t);
    for (size_t i = 0; i < 16; i++) {
        reg_t tor = csr[pmpaddr0+i] << PMP_SHIFT;
-        uint8_t cfg = csr[pmpcfg0+(i/4)]>>(i%4);
+        uint8_t cfg = csr[pmpcfg0+(i/cfg_reg_size)]>>(i%cfg_reg_size);
        if (cfg & PMP_A) {
            any_active=true;
            auto pmp_a = (cfg & PMP_A) >> 3;
@ -680,7 +804,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
 #ifndef NDEBUG
    if (access && iss::access_type::DEBUG) {
        LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
-    } else if(access && iss::access_type::FETCH){
+    } else if(is_fetch(access)){
        LOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
    } else {
        LOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
@ -693,26 +817,26 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                if(!pmp_check(access, addr, length) && !is_debug(access)) {
                    fault_data = addr;
                    if (is_debug(access)) throw trap_access(0, addr);
-                    this->trap_state = (1UL << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1
+                    this->reg.trap_state = (1UL << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1
                    return iss::Err;
                }
            }
-            auto alignment = is_fetch(access)? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
+            auto alignment = is_fetch(access)? (has_compressed()? 2 : 4) : length;
            if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                fault_data = addr;
                if (is_debug(access)) throw trap_access(0, addr);
-                this->trap_state = (1UL << 31); // issue trap 0
+                this->reg.trap_state = (1UL << 31); // issue trap 0
                return iss::Err;
            }
            try {
-                if(!is_debug(access)  && (addr&(alignment-1))){
-                    this->trap_state = (1UL << 31) | 4<<16;
+                if(!is_debug(access) && (addr&(alignment-1))){
+                    this->reg.trap_state = (1UL << 31) | 4<<16;
                    fault_data=addr;
                    return iss::Err;
                }
                auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
                auto res = iss::Err;
-                if(access != access_type::FETCH && memfn_range.size()){
+                if(!is_fetch(access) && memfn_range.size()){
                    auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
                        return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
                    });
@ -720,17 +844,17 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                        auto idx = std::distance(std::begin(memfn_range), it);
                        res = memfn_read[idx](phys_addr, length, data);
                    } else
-                        res = read_mem( phys_addr, length, data);
+                        res = hart_mem_rd_delegate( phys_addr, length, data);
                } else {
-                    res = read_mem( phys_addr, length, data);
+                    res = hart_mem_rd_delegate( phys_addr, length, data);
                }
                if (unlikely(res != iss::Ok)){
-                    this->trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
+                    this->reg.trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                    fault_data=addr;
                }
                return res;
            } catch (trap_access &ta) {
-                this->trap_state = (1UL << 31) | ta.id;
+                this->reg.trap_state = (1UL << 31) | ta.id;
                fault_data=ta.addr;
                return iss::Err;
            }
@ -756,7 +880,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
        }
        return iss::Ok;
    } catch (trap_access &ta) {
-        this->trap_state = (1UL << 31) | ta.id;
+        this->reg.trap_state = (1UL << 31) | ta.id;
        fault_data=ta.addr;
        return iss::Err;
    }
@ -795,25 +919,25 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) {
                    fault_data = addr;
                    if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                    this->trap_state = (1UL << 31) | (7 << 16); // issue trap 1
+                    this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 1
                    return iss::Err;
                }
            }
-            if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
+            if (unlikely(is_fetch(access) && (addr & 0x1) == 1)) {
                fault_data = addr;
                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->trap_state = (1UL << 31); // issue trap 0
+                this->reg.trap_state = (1UL << 31); // issue trap 0
                return iss::Err;
            }
            try {
                if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
-                    this->trap_state = (1UL << 31) | 6<<16;
+                    this->reg.trap_state = (1UL << 31) | 6<<16;
                    fault_data=addr;
                    return iss::Err;
                }
                auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
                auto res = iss::Err;
-                if(access != access_type::FETCH && memfn_range.size()){
+                if(!is_fetch(access) && memfn_range.size()){
                    auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
                        return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
                    });
@ -821,17 +945,17 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                        auto idx = std::distance(std::begin(memfn_range), it);
                        res = memfn_write[idx]( phys_addr, length, data);
                    } else
-                        res = write_mem( phys_addr, length, data);
+                        res = hart_mem_wr_delegate( phys_addr, length, data);
                } else {
-                    res = write_mem( phys_addr, length, data);
+                    res = hart_mem_wr_delegate( phys_addr, length, data);
                }
                if (unlikely(res != iss::Ok)) {
-                    this->trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
                    fault_data=addr;
                }
                return res;
            } catch (trap_access &ta) {
-                this->trap_state = (1UL << 31) | ta.id;
+                this->reg.trap_state = (1UL << 31) | ta.id;
                fault_data=ta.addr;
                return iss::Err;
            }
@ -891,7 +1015,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
        }
        return iss::Ok;
    } catch (trap_access &ta) {
-        this->trap_state = (1UL << 31) | ta.id;
+        this->reg.trap_state = (1UL << 31) | ta.id;
        fault_data=ta.addr;
        return iss::Err;
    }
@ -937,11 +1061,10 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_cycle(unsigned addr, reg_t &val) {
-    auto cycle_val = this->icount + cycle_offset;
+    auto cycle_val = this->reg.icount + cycle_offset;
    if (addr == mcycle) {
        val = static_cast<reg_t>(cycle_val);
    } else if (addr == mcycleh) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
        val = static_cast<reg_t>(cycle_val >> 32);
    }
    return iss::Ok;
@ -949,8 +1072,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT

 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_cycle(unsigned addr, reg_t val) {
    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if (addr == mcycleh)
-            return iss::Err;
        mcycle_csr = static_cast<uint64_t>(val);
    } else {
        if (addr == mcycle) {
@ -959,38 +1080,35 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
            mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff);
        }
    }
-    cycle_offset = mcycle_csr-this->icount; // TODO: relying on wrap-around
+    cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around
    return iss::Ok;
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_instret(unsigned addr, reg_t &val) {
    if ((addr&0xff) == (minstret&0xff)) {
-        val = static_cast<reg_t>(this->instret);
+        val = static_cast<reg_t>(this->reg.instret);
    } else if ((addr&0xff) == (minstreth&0xff)) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-        val = static_cast<reg_t>(this->instret >> 32);
+        val = static_cast<reg_t>(this->reg.instret >> 32);
    }
    return iss::Ok;
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_instret(unsigned addr, reg_t val) {
    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if ((addr&0xff) == (minstreth&0xff))
-            return iss::Err;
-        this->instret = static_cast<uint64_t>(val);
+        this->reg.instret = static_cast<uint64_t>(val);
    } else {
        if ((addr&0xff) == (minstret&0xff)) {
-            this->instret = (this->instret & 0xffffffff00000000) + val;
+            this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val;
        } else  {
-            this->instret = (static_cast<uint64_t>(val)<<32) + (this->instret & 0xffffffff);
+            this->reg.instret = (static_cast<uint64_t>(val)<<32) + (this->reg.instret & 0xffffffff);
        }
    }
-    this->instret--;
+    this->reg.instret--;
    return iss::Ok;
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_time(unsigned addr, reg_t &val) {
-    uint64_t time_val = this->icount / (100000000 / 32768 - 1); //-> ~3052;
+    uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
    if (addr == time) {
        val = static_cast<reg_t>(time_val);
    } else if (addr == timeh) {
@ -1001,7 +1119,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_tvec(unsigned addr, reg_t &val) {
-    val = csr[addr] & ~2;
+    val = FEAT & features_e::FEAT_CLIC? csr[addr] : csr[addr] & ~2;
    return iss::Ok;
 }
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_status(unsigned addr, reg_t &val) {
@ -1015,8 +1133,46 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
    return iss::Ok;
 }

+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_cause(unsigned addr, reg_t &val) {
+    if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) {
+        val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16));
+        auto mode = (addr >> 8) & 0x3;
+        switch(mode) {
+        case 0:
+            val |= clic_uprev_lvl<<16;
+            val |= state.mstatus.UPIE<<27;
+            break;
+        default:
+            val |= clic_mprev_lvl<<16;
+            val |= state.mstatus.MPIE<<27;
+            val |= state.mstatus.MPP<<28;
+            break;
+        }
+    } else
+        val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
+    return iss::Ok;
+}
+
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
-    csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1))|(mcause_max_irq-1));
+    if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) {
+        auto mask = ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16));
+        csr[addr] = (val & mask) | (csr[addr] & ~mask);
+        auto mode = (addr >> 8) & 0x3;
+        switch(mode) {
+        case 0:
+            clic_uprev_lvl = ((val>>16)&0xff) | (1<<(8-cfg. clic_int_ctl_bits)) - 1;
+            state.mstatus.UPIE=(val>>27)&0x1;
+            break;
+        default:
+            clic_mprev_lvl = ((val>>16)&0xff) | (1<<(8-cfg. clic_int_ctl_bits)) - 1;
+            state.mstatus.MPIE=(val>>27)&0x1;
+            state.mstatus.MPP=(val>>28)&0x3;
+            break;
+        }
+    } else {
+        auto mask = ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
+        csr[addr] = (val & mask) | (csr[addr] & ~mask);
+    }
    return iss::Ok;
 }

@ -1104,27 +1260,30 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
    return iss::Ok;
 }

+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::read_intstatus(unsigned addr, reg_t& val) {
+    auto mode = (addr >> 8) & 0x3;
+    val = clic_uact_lvl&0xff;
+    if(mode==0x3)
+        val += (clic_mact_lvl&0xff) <<24;
+    return iss::Ok;
+}
+
 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
-    csr[addr]= val &0xff;
+    csr[addr]= (val &0xff) | (1<<(cfg.clic_int_ctl_bits)) - 1;
+    return iss::Ok;
+}
+
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::write_xtvt(unsigned addr, reg_t val) {
+    csr[addr]= val & ~0x3fULL;
    return iss::Ok;
 }

 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
    switch (paddr.val) {
-    case 0x0200BFF8: { // CLINT base, mtime reg
-        if (sizeof(reg_t) < length) return iss::Err;
-        reg_t time_val;
-        this->read_csr(time, time_val);
-        std::copy((uint8_t *)&time_val, ((uint8_t *)&time_val) + length, data);
-    } break;
-    case 0x10008000: {
-        const mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        uint64_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(p.data() + offs, p.data() + offs + length, data);
-        if (this->icount > 30000) data[3] |= 0x80;
-    } break;
    default: {
        for(auto offs=0U; offs<length; ++offs) {
            *(data + offs)=mem[(paddr.val+offs)%mem.size()];
@ -1137,29 +1296,13 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned le
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
    switch (paddr.val) {
-    case 0x10013000: // UART0 base, TXFIFO reg
-    case 0x10023000: // UART1 base, TXFIFO reg
-        uart_buf << (char)data[0];
+    case 0xFFFF0000: // UART0 base, TXFIFO reg
        if (((char)data[0]) == '\n' || data[0] == 0) {
-            LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send '"<<uart_buf.str()<<"'";
-            std::cout << uart_buf.str();
+            LOG(INFO)<<"UART"<<((paddr.val>>12)&0x3)<<" send '"<<uart_buf.str()<<"'";
            uart_buf.str("");
-        }
+        } else if(((char)data[0]) != '\r')
+            uart_buf << (char)data[0];
        break;
-    case 0x10008000: { // HFROSC base, hfrosccfg reg
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        size_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(data, data + length, p.data() + offs);
-        uint8_t &x = *(p.data() + offs + 3);
-        if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
-    } break;
-    case 0x10008008: { // HFROSC base, pllcfg reg
-        mem_type::page_type &p = mem(paddr.val / mem.page_size);
-        size_t offs = paddr.val & mem.page_addr_mask;
-        std::copy(data, data + length, p.data() + offs);
-        uint8_t &x = *(p.data() + offs + 3);
-        x |= 0x80; // set pll lock upon writing
-    } break;
    default: {
        mem_type::page_type &p = mem(paddr.val / mem.page_size);
        std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
@ -1181,7 +1324,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned l
                            LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
                                      << "), stopping simulation";
                        }
-                        this->trap_state=std::numeric_limits<uint32_t>::max();
+                        this->reg.trap_state=std::numeric_limits<uint32_t>::max();
                        this->interrupt_sim=hostvar;
                        break;
                        //throw(iss::simulation_stopped(hostvar));
@ -1215,8 +1358,6 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned lengt
    if(addr==cfg.clic_base) { // cliccfg
        *data=clic_cfg_reg;
        for(auto i=1; i<length; ++i) *(data+i)=0;
-    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+8)){ // clicinfo
-        read_reg_uint32(addr, clic_info_reg, data, length);
    } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
        auto offset = ((addr&0x7fff)-0x40)/4;
        read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
@ -1232,10 +1373,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned lengt
 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
    if(addr==cfg.clic_base) { // cliccfg
-        clic_cfg_reg = *data;
-        clic_cfg_reg&= 0x7e;
-//    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+4)){ // clicinfo
-//        write_uint32(addr, clic_info_reg, data, length);
+        clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e);
    } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
        auto offset = ((addr&0x7fff)-0x40)/4;
        write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
@ -1253,6 +1391,7 @@ template <typename BASE, features_e FEAT> inline void riscv_hart_mu_p<BASE, FEAT
 }

 template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::check_interrupt() {
+    //TODO: Implement CLIC functionality
    auto ideleg = csr[mideleg];
    // Multiple simultaneous interrupts and traps at the same privilege level are
    // handled in the following decreasing priority order:
@ -1270,14 +1409,14 @@ template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::chec
        	enabled_interrupts >>= 1;
        	res++;
        }
-        this->pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
+        this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
    }
 }

 template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
    // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
    // calculate and write mcause val
-    if(flags==std::numeric_limits<uint64_t>::max()) flags=this->trap_state;
+    if(flags==std::numeric_limits<uint64_t>::max()) flags=this->reg.trap_state;
    auto trap_id = bit_sub<0, 16>(flags);
    auto cause = bit_sub<16, 15>(flags);
    if (trap_id == 0 && cause == 11) cause = 0x8 + this->reg.PRIV; // adjust environment call cause
@ -1300,7 +1439,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
            csr[utval | (new_priv << 8)] = static_cast<reg_t>(addr);
            break;
        case 2:
-            csr[utval | (new_priv << 8)] = (instr & 0x3)==3?instr:instr&0xffff;
+            csr[utval | (new_priv << 8)] = (!has_compressed() || (instr & 0x3)==3)?instr:instr&0xffff;
            break;
        case 3:
            if((FEAT & FEAT_DEBUG) && (csr[dcsr] & 0x8000)) {
@ -1324,7 +1463,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
        if (this->reg.PRIV != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0)
            new_priv = PRIV_U;
        csr[uepc | (new_priv << 8)] = this->reg.NEXT_PC; // store next address if interrupt
-        this->pending_trap = 0;
+        this->reg.pending_trap = 0;
    }
    size_t adr = ucause | (new_priv << 8);
    csr[adr] = (trap_id << (traits<BASE>::XLEN-1)) + cause;
@ -1350,13 +1489,26 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
    }

    // get trap vector
-    auto ivec = csr[utvec | (new_priv << 8)];
+    auto xtvec = csr[utvec | (new_priv << 8)];
    // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
    // bits in mtvec
-    this->reg.NEXT_PC = ivec & ~0x3UL;
-    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
+    if((FEAT & features_e::FEAT_CLIC) && trap_id!=0 &&  (xtvec & 0x3UL)==3UL) {
+        reg_t data;
+        auto ret = read(address_type::LOGICAL, access_type::READ, 0, csr[mtvt], sizeof(reg_t), reinterpret_cast<uint8_t*>(&data));
+        if(ret == iss::Err)
+            return this->reg.PC;
+        this->reg.NEXT_PC = data;
+    } else {
+        this->reg.NEXT_PC = xtvec & ~0x3UL;
+        if ((xtvec & 0x1) == 1 && trap_id != 0)
+            this->reg.NEXT_PC += 4 * cause;
+    }
    std::array<char, 32> buffer;
+#if defined(_MSC_VER)
+    sprintf(buffer.data(), "0x%016llx", addr);
+#else
    sprintf(buffer.data(), "0x%016lx", addr);
+#endif
    if((flags&0xffffffff) != 0xffffffff)
    CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
@ -1364,7 +1516,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
                       << lvl[this->reg.PRIV] << " to " << lvl[new_priv];
    // reset trap state
    this->reg.PRIV = new_priv;
-    this->trap_state = 0;
+    this->reg.trap_state = 0;
    return this->reg.NEXT_PC;
 }

@ -1373,7 +1525,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
    auto inst_priv = (flags & 0x3)? 3:0;
    if(inst_priv>cur_priv){
        auto trap_val =  0x80ULL << 24 | (2 << 16); // illegal instruction
-        this->trap_state = trap_val;
+        this->reg.trap_state = trap_val;
        this->reg.NEXT_PC = std::numeric_limits<uint32_t>::max();
    } else {
        auto status = state.mstatus;
--- a/src/iss/arch/tgc_c.cpp
+++ b/src/iss/arch/tgc_c.cpp
@ -41,8 +41,8 @@ using namespace iss::arch;

 constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
 constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
-constexpr std::array<const uint32_t, 36> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 36> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;

 tgc_c::tgc_c()  = default;

@ -55,8 +55,8 @@ void tgc_c::reset(uint64_t address) {
    reg.PC=address;
    reg.NEXT_PC=reg.PC;
    reg.PRIV=0x3;
-    trap_state=0;
-    icount=0;
+    reg.trap_state=0;
+    reg.icount=0;
 }

 uint8_t *tgc_c::get_regs_base_ptr() {
--- a/src/iss/arch/tgc_c.h
+++ b/src/iss/arch/tgc_c.h
@ -58,7 +58,7 @@ template <> struct traits<tgc_c> {
    constexpr static unsigned FP_REGS_SIZE = 0;

    enum reg_e {
-        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS
+        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
    };

    using reg_t = uint32_t;
@ -71,11 +71,11 @@ template <> struct traits<tgc_c> {

    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;

-    static constexpr std::array<const uint32_t, 36> reg_bit_widths{
-        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32}};
+    static constexpr std::array<const uint32_t, 43> reg_bit_widths{
+        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};

-    static constexpr std::array<const uint32_t, 36> reg_byte_offsets{
-        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137}};
+    static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
+        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}};

    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);

@ -189,7 +189,7 @@ struct tgc_c: public arch_if {

    uint8_t* get_regs_base_ptr() override;

-    inline uint64_t get_icount() { return icount; }
+    inline uint64_t get_icount() { return reg.icount; }

    inline bool should_stop() { return interrupt_sim; }

@ -207,7 +207,7 @@ struct tgc_c: public arch_if {

    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }

-    inline uint32_t get_last_branch() { return last_branch; }
+    inline uint32_t get_last_branch() { return reg.last_branch; }


 #pragma pack(push, 1)
@ -248,14 +248,14 @@ struct tgc_c: public arch_if {
        uint32_t NEXT_PC = 0; 
        uint8_t PRIV = 0; 
        uint32_t DPC = 0;
+        uint32_t trap_state = 0, pending_trap = 0;
+        uint64_t icount = 0;
+        uint64_t cycle = 0;
+        uint64_t instret = 0;
+        uint32_t instruction = 0;
+        uint32_t last_branch = 0;
    } reg;
 #pragma pack(pop)
-    uint32_t trap_state = 0, pending_trap = 0;
-    uint64_t icount = 0;
-    uint64_t cycle = 0;
-    uint64_t instret = 0;
-    uint32_t instruction = 0;
-    uint32_t last_branch = 0;
    std::array<address_type, 4> addr_mode;
    
    uint64_t interrupt_sim=0;
--- a/src/iss/arch/wt_cache.h
+++ b/src/iss/arch/wt_cache.h
@ -0,0 +1,172 @@
+/*******************************************************************************
+ * Copyright (C) 2023 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial implementation
+ ******************************************************************************/
+
+#ifndef _RISCV_HART_M_P_WT_CACHE_H
+#define _RISCV_HART_M_P_WT_CACHE_H
+
+#include <iss/vm_types.h>
+#include <util/ities.h>
+#include <vector>
+#include <map>
+#include <memory>
+
+namespace iss {
+namespace arch {
+namespace cache {
+
+enum class state { INVALID, VALID};
+struct line {
+    uint64_t tag_addr{0};
+    state st{state::INVALID};
+    std::vector<uint8_t> data;
+    line(unsigned line_sz):  data(line_sz) {}
+};
+struct set {
+    std::vector<line> ways;
+    set(unsigned ways_count, line const& l): ways(ways_count, l) {}
+};
+struct cache {
+    std::vector<set> sets;
+
+    cache(unsigned size, unsigned line_sz, unsigned ways) {
+        line const ref_line{line_sz};
+        set const ref_set{ways, ref_line};
+        sets.resize(size/(ways*line_sz), ref_set);
+    }
+};
+
+struct wt_policy {
+    bool is_cacheline_hit(cache& c );
+};
+}
+
+// write thru, allocate on read, direct mapped or set-associative with round-robin replacement policy
+template <typename BASE> class wt_cache : public BASE {
+public:
+    using base_class = BASE;
+    using this_class = wt_cache<BASE>;
+    using reg_t = typename BASE::reg_t;
+    using mem_read_f = typename BASE::mem_read_f;
+    using mem_write_f = typename BASE::mem_write_f;
+    using phys_addr_t = typename BASE::phys_addr_t;
+
+    wt_cache();
+    virtual ~wt_cache() = default;
+
+    unsigned size{4096};
+    unsigned line_sz{32};
+    unsigned ways{1};
+    uint64_t io_address{0xf0000000};
+    uint64_t io_addr_mask{0xf0000000};
+protected:
+    iss::status read_cache(phys_addr_t addr, unsigned, uint8_t *const);
+    iss::status write_cache(phys_addr_t addr, unsigned, uint8_t const *const);
+    std::function<mem_read_f> cache_mem_rd_delegate;
+    std::function<mem_write_f> cache_mem_wr_delegate;
+    std::unique_ptr<cache::cache> dcache_ptr;
+    std::unique_ptr<cache::cache> icache_ptr;
+    size_t get_way_select() {
+        return 0;
+    }
+};
+
+
+template<typename BASE>
+inline wt_cache<BASE>::wt_cache() {
+    auto cb = base_class::replace_mem_access(
+            [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l,d);},
+            [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l,d);});
+    cache_mem_rd_delegate = cb.first;
+    cache_mem_wr_delegate = cb.second;
+}
+
+template<typename BASE>
+iss::status iss::arch::wt_cache<BASE>::read_cache(phys_addr_t a, unsigned l, uint8_t* const d) {
+    if(!icache_ptr) {
+        icache_ptr.reset(new cache::cache(size, line_sz, ways));
+        dcache_ptr.reset(new cache::cache(size, line_sz, ways));
+    }
+    if((a.val&io_addr_mask) != io_address) {
+        auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways);
+        auto tag_addr=a.val>>util::ilog2(line_sz);
+        auto& set = (is_fetch(a.access)?icache_ptr:dcache_ptr)->sets[set_addr];
+        for(auto& cl: set.ways) {
+            if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
+                auto start_addr = a.val&(line_sz-1);
+                for(auto i = 0U; i<l; ++i)
+                    d[i] = cl.data[start_addr+i];
+                return iss::Ok;
+            }
+        }
+        auto& cl = set.ways[get_way_select()];
+        phys_addr_t cl_addr{a};
+        cl_addr.val=tag_addr<<util::ilog2(line_sz);
+        cache_mem_rd_delegate(cl_addr, line_sz, cl.data.data());
+        cl.tag_addr=tag_addr;
+        cl.st=cache::state::VALID;
+        auto start_addr = a.val&(line_sz-1);
+        for(auto i = 0U; i<l; ++i)
+            d[i] = cl.data[start_addr+i];
+        return iss::Ok;
+    } else
+        return cache_mem_rd_delegate(a, l, d);
+}
+
+template<typename BASE>
+iss::status iss::arch::wt_cache<BASE>::write_cache(phys_addr_t a, unsigned l, const uint8_t* const d) {
+    if(!dcache_ptr)
+        dcache_ptr.reset(new cache::cache(size, line_sz, ways));
+    auto res = cache_mem_wr_delegate(a, l, d);
+    if(res == iss::Ok && ((a.val&io_addr_mask) != io_address)) {
+        auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways);
+        auto tag_addr=a.val>>util::ilog2(line_sz);
+        auto& set = dcache_ptr->sets[set_addr];
+        for(auto& cl: set.ways) {
+            if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
+                auto start_addr = a.val&(line_sz-1);
+                for(auto i = 0U; i<l; ++i)
+                    cl.data[start_addr+i] = d[i];
+                break;
+            }
+        }
+    }
+    return res;
+}
+
+
+
+} // namespace arch
+} // namespace iss
+
+#endif /* _RISCV_HART_M_P_H */
--- a/src/iss/factory.h
+++ b/src/iss/factory.h
@ -50,7 +50,7 @@ std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_
    if(backend == "llvm")
        return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
 #endif
-#ifdef WITH_LLVM
+#ifdef WITH_TCC
    if(backend == "tcc")
        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
 #endif
--- a/src/iss/plugin/cycle_estimate.cpp
+++ b/src/iss/plugin/cycle_estimate.cpp
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -107,12 +107,12 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&

 }

-void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const& exc_info) {
+void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
    assert(instr_if && "No instrumentation interface available but callback executed");
    auto entry = delays[instr_info.instr_id];
-    bool taken = exc_info.branch_taken;
-    if (exc_info.branch_taken && (entry.taken > 1))
-        instr_if->set_curr_instr_cycles(entry.taken);
+    bool taken = instr_if->is_branch_taken();
+    if (taken && (entry.taken > 1))
+        instr_if->update_last_instr_cycles(entry.taken);
    else if (entry.not_taken > 1)
-        instr_if->set_curr_instr_cycles(entry.not_taken);
+        instr_if->update_last_instr_cycles(entry.not_taken);
 }
--- a/src/iss/plugin/cycle_estimate.h
+++ b/src/iss/plugin/cycle_estimate.h
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -78,7 +78,7 @@ public:

    sync_type get_sync() override { return POST_SYNC; };

-    void callback(instr_info_t instr_info, exec_info const&) override;
+    void callback(instr_info_t instr_info) override;

 private:
    iss::instrumentation_if *instr_if;
--- a/src/iss/plugin/instruction_count.cpp
+++ b/src/iss/plugin/instruction_count.cpp
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -90,6 +90,6 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
 	return true;
 }

-void iss::plugin::instruction_count::callback(instr_info_t instr_info, exec_info const&) {
+void iss::plugin::instruction_count::callback(instr_info_t instr_info) {
 	rep_counts[instr_info.instr_id]++;
 }
--- a/src/iss/plugin/instruction_count.h
+++ b/src/iss/plugin/instruction_count.h
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -69,7 +69,7 @@ public:

    sync_type get_sync() override { return POST_SYNC; };

-    void callback(instr_info_t, exec_info const&) override;
+    void callback(instr_info_t) override;

 private:
    Json::Value root;
--- a/src/iss/plugin/pctrace.cpp
+++ b/src/iss/plugin/pctrace.cpp
@ -1,3 +1,37 @@
+/*******************************************************************************
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       alex.com - initial implementation
+ ******************************************************************************/
+
 #include <iss/arch_if.h>
 #include <iss/plugin/pctrace.h>
 #include <util/logging.h>
@ -152,22 +186,22 @@ bool pctrace::registration(const char *const version, vm_if& vm) {
    return true;
 }

-void pctrace::callback(instr_info_t iinfo, const exec_info& einfo) {
+void pctrace::callback(instr_info_t iinfo) {
    auto delay = 0;
    size_t id = iinfo.instr_id;
    auto entry = delays[id];
    auto instr = instr_if->get_instr_word();
    auto call = id==65 || id ==86 || ((id==2 || id==3) && bit_sub<7,5>(instr)!=0) ;//not taking care of tail calls (jalr with loading x6)
-    bool taken = einfo.branch_taken;
+    bool taken = instr_if->is_branch_taken();
    bool compressed = (instr&0x3)!=0x3;
-    if (einfo.branch_taken) {
+    if (taken) {
        delay = entry.taken;
        if(entry.taken > 1)
-            instr_if->set_curr_instr_cycles(entry.taken);
+            instr_if->update_last_instr_cycles(entry.taken);
    } else {
        delay = entry.not_taken;
        if (entry.not_taken > 1)
-            instr_if->set_curr_instr_cycles(entry.not_taken);
+            instr_if->update_last_instr_cycles(entry.not_taken);
    }
 #ifndef WITH_LZ4
    output<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
--- a/src/iss/plugin/pctrace.h
+++ b/src/iss/plugin/pctrace.h
@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@ -83,7 +83,7 @@ public:

    sync_type get_sync() override { return POST_SYNC; };

-    void callback(instr_info_t, exec_info const&) override;
+    void callback(instr_info_t) override;

 private:
    iss::instrumentation_if *instr_if  {nullptr};
--- a/src/main.cpp
+++ b/src/main.cpp
@ -61,7 +61,7 @@ int main(int argc, char *argv[]) {
    // clang-format off
    desc.add_options()
        ("help,h", "Print help message")
-        ("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
+        ("verbose,v", po::value<int>()->default_value(4), "Sets logging verbosity")
        ("logfile,l", po::value<std::string>(), "Sets default log file.")
        ("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
        ("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
@ -71,7 +71,7 @@ int main(int argc, char *argv[]) {
        ("elf,f", po::value<std::vector<std::string>>(), "ELF file(s) to load")
        ("mem,m", po::value<std::string>(), "the memory input file")
        ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
-        ("backend", po::value<std::string>()->default_value("interp"), "the memory input file")
+        ("backend", po::value<std::string>()->default_value("interp"), "the ISS backend to use, options are: interp, tcc")
        ("isa", po::value<std::string>()->default_value("tgc_c"), "isa to use for simulation");
    // clang-format on
    auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
@ -93,11 +93,9 @@ int main(int argc, char *argv[]) {

    LOGGER(DEFAULT)::print_time() = false;
    LOGGER(connection)::print_time() = false;
-    if (clim.count("verbose")) {
-        auto l = logging::as_log_level(clim["verbose"].as<int>());
-        LOGGER(DEFAULT)::reporting_level() = l;
-        LOGGER(connection)::reporting_level() = l;
-    }
+    auto l = logging::as_log_level(clim["verbose"].as<int>());
+    LOGGER(DEFAULT)::reporting_level() = l;
+    LOGGER(connection)::reporting_level() = l;
    if (clim.count("logfile")) {
        // configure the connection logger
        auto f = fopen(clim["logfile"].as<std::string>().c_str(), "w");
@ -161,6 +159,14 @@ int main(int argc, char *argv[]) {
            LOG(ERR) << "Illegal argument value for '--isa': " << isa_opt << std::endl;
            return 127;
        }
+        if(!cpu ){
+            LOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " <<clim["backend"].as<std::string>()<< std::endl;
+            return 127;
+        }
+        if(!vm ){
+            LOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " <<clim["backend"].as<std::string>()<< std::endl;
+            return 127;
+        }
        if (clim.count("plugin")) {
            for (std::string const& opt_val : clim["plugin"].as<std::vector<std::string>>()) {
                std::string plugin_name=opt_val;
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@ -107,7 +107,8 @@ public:
    heart_state_t &get_state() { return this->state; }

    void notify_phase(iss::arch_if::exec_phase p) override {
-        if (p == iss::arch_if::ISTART) owner->sync(this->icount);
+        if (p == iss::arch_if::ISTART)
+            owner->sync(this->instr_if.get_total_cycles());
    }

    sync_type needed_sync() const override { return PRE_SYNC; }
@ -117,7 +118,7 @@ public:
            std::stringstream s;
            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
-              << this->icount + this->cycle_offset << "]";
+              << this->reg.icount + this->cycle_offset << "]";
            SCCDEBUG(owner->name())<<"disass: "
                << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
                << std::setfill(' ') << std::left << instr << s.str();
@ -128,7 +129,7 @@ public:
        if (addr.access && access_type::DEBUG)
            return owner->read_mem_dbg(addr.val, length, data) ? Ok : Err;
        else {
-            return owner->read_mem(addr.val, length, data, addr.access && access_type::FETCH) ? Ok : Err;
+            return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? Ok : Err;
        }
    }

@ -177,7 +178,7 @@ public:

    void wait_until(uint64_t flags) override {
        SCCDEBUG(owner->name()) << "Sleeping until interrupt";
-        while(this->pending_trap == 0 && (this->csr[arch::mip] & this->csr[arch::mie]) == 0) {
+        while(this->reg.pending_trap == 0 && (this->csr[arch::mip] & this->csr[arch::mie]) == 0) {
            sc_core::wait(wfi_evt);
        }
        PLAT::wait_until(flags);
@ -206,7 +207,7 @@ public:
            this->csr[arch::mip] &= ~mask;
        this->check_interrupt();
        if(value)
-            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->pending_trap;
+            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
    }

 private:
@ -330,6 +331,7 @@ SC_HAS_PROCESS(core_complex);// NOLINT
 #ifndef CWR_SYSTEMC
 core_complex::core_complex(sc_module_name const& name)
 : sc_module(name)
+, fetch_lut(tlm_dmi_ext())
 , read_lut(tlm_dmi_ext())
 , write_lut(tlm_dmi_ext())
 {
@ -339,7 +341,13 @@ core_complex::core_complex(sc_module_name const& name)

 void core_complex::init(){
 	trc=new core_trace();
-    initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
+    ibus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
+        auto lut_entry = fetch_lut.getEntry(start);
+        if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
+            fetch_lut.removeEntry(lut_entry);
+        }
+    });
+    dbus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
        auto lut_entry = read_lut.getEntry(start);
        if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
            read_lut.removeEntry(lut_entry);
@ -431,7 +439,7 @@ void core_complex::before_end_of_elaboration() {
 }

 void core_complex::start_of_simulation() {
-    quantum_keeper.reset();
+    // quantum_keeper.reset();
    if (GET_PROP_VALUE(elf_file).size() > 0) {
        istringstream is(GET_PROP_VALUE(elf_file));
        string s;
@ -500,6 +508,7 @@ void core_complex::local_irq_cb() {
 void core_complex::run() {
    wait(SC_ZERO_TIME); // separate from elaboration phase
    do {
+        wait(SC_ZERO_TIME);
        if (rst_i.read()) {
            cpu->reset(GET_PROP_VALUE(reset_address));
            wait(rst_i.negedge_event());
@ -507,6 +516,7 @@ void core_complex::run() {
        while (curr_clk.read() == SC_ZERO_TIME) {
            wait(curr_clk.value_changed_event());
        }
+        quantum_keeper.reset();
        cpu->set_interrupt_execution(false);
        cpu->start();
    } while (cpu->get_interrupt_execution());
@ -514,14 +524,15 @@ void core_complex::run() {
 }

 bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch) {
-    auto lut_entry = read_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
+    auto& dmi_lut = is_fetch?fetch_lut:read_lut;
+    auto lut_entry = dmi_lut.getEntry(addr);
+    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
        auto offset = addr - lut_entry.get_start_address();
        std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
        quantum_keeper.inc(lut_entry.get_read_latency());
        return true;
    } else {
+        auto& sckt = is_fetch? ibus : dbus;
        tlm::tlm_generic_payload gp;
        gp.set_command(tlm::TLM_READ_COMMAND);
        gp.set_address(addr);
@ -536,8 +547,13 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
            gp.set_extension(preExt);
        }
-        initiator->b_transport(gp, delay);
-        SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : " << data;
+        sckt->b_transport(gp, delay);
+        auto incr = delay-quantum_keeper.get_local_time();
+        if(is_fetch)
+            ibus_inc+=incr;
+        else
+            dbus_inc+=incr;
+        SCCTRACE(this->name()) << "[local time: "<<delay<<"]: finish read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
        if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
            return false;
        }
@ -545,13 +561,10 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
            gp.set_command(tlm::TLM_READ_COMMAND);
            gp.set_address(addr);
            tlm_dmi_ext dmi_data;
-            if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
+            if (sckt->get_direct_mem_ptr(gp, dmi_data)) {
                if (dmi_data.is_read_allowed())
-                    read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
+                    dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(),
                                      dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
-                if (dmi_data.is_write_allowed())
-                    write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
-                                       dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
            }
        }
        return true;
@ -580,9 +593,9 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
            gp.set_extension(preExt);
        }
-        initiator->b_transport(gp, delay);
-        quantum_keeper.set(delay);
-        SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : " << data;
+        dbus->b_transport(gp, delay);
+        dbus_inc+=delay-quantum_keeper.get_local_time();
+        SCCTRACE() << "[local time: "<<delay<<"]: finish write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
        if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
            return false;
        }
@ -590,10 +603,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
            gp.set_command(tlm::TLM_READ_COMMAND);
            gp.set_address(addr);
            tlm_dmi_ext dmi_data;
-            if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
-                if (dmi_data.is_read_allowed())
-                    read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
-                                      dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
+            if (dbus->get_direct_mem_ptr(gp, dmi_data)) {
                if (dmi_data.is_write_allowed())
                    write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
                                       dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
@ -604,43 +614,25 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
 }

 bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data) {
-    auto lut_entry = read_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
-        auto offset = addr - lut_entry.get_start_address();
-        std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
-        quantum_keeper.inc(lut_entry.get_read_latency());
-        return true;
-    } else {
-        tlm::tlm_generic_payload gp;
-        gp.set_command(tlm::TLM_READ_COMMAND);
-        gp.set_address(addr);
-        gp.set_data_ptr(data);
-        gp.set_data_length(length);
-        gp.set_streaming_width(length);
-        return initiator->transport_dbg(gp) == length;
-    }
+    tlm::tlm_generic_payload gp;
+    gp.set_command(tlm::TLM_READ_COMMAND);
+    gp.set_address(addr);
+    gp.set_data_ptr(data);
+    gp.set_data_length(length);
+    gp.set_streaming_width(length);
+    return dbus->transport_dbg(gp) == length;
 }

 bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data) {
-    auto lut_entry = write_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
-        auto offset = addr - lut_entry.get_start_address();
-        std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
-        quantum_keeper.inc(lut_entry.get_read_latency());
-        return true;
-    } else {
-        write_buf.resize(length);
-        std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
-        tlm::tlm_generic_payload gp;
-        gp.set_command(tlm::TLM_WRITE_COMMAND);
-        gp.set_address(addr);
-        gp.set_data_ptr(write_buf.data());
-        gp.set_data_length(length);
-        gp.set_streaming_width(length);
-        return initiator->transport_dbg(gp) == length;
-    }
+    write_buf.resize(length);
+    std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
+    tlm::tlm_generic_payload gp;
+    gp.set_command(tlm::TLM_WRITE_COMMAND);
+    gp.set_address(addr);
+    gp.set_data_ptr(write_buf.data());
+    gp.set_data_length(length);
+    gp.set_streaming_width(length);
+    return dbus->transport_dbg(gp) == length;
 }
 } /* namespace SiFive */
 } /* namespace sysc */
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@ -40,8 +40,10 @@
 #include <tlm/scc/scv/tlm_rec_initiator_socket.h>
 #ifdef CWR_SYSTEMC
 #include <scmlinc/scml_property.h>
+#define SOCKET_WIDTH 32
 #else
 #include <cci_configuration>
+#define SOCKET_WIDTH scc::LT
 #endif
 #include <tlm>
 #include <tlm_utils/tlm_quantumkeeper.h>
@ -69,7 +71,9 @@ struct core_trace;

 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
-    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<32>> initiator{"intor"};
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> ibus{"ibus"};
+
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> dbus{"dbus"};

    sc_core::sc_in<bool> rst_i{"rst_i"};

@ -140,6 +144,8 @@ public:
    , gdb_server_port{"gdb_server_port", 0}
    , dump_ir{"dump_ir", false}
    , mhartid{"mhartid", 0}
+    , plugins{"plugins", ""}
+    , fetch_lut(tlm_dmi_ext())
    , read_lut(tlm_dmi_ext())
    , write_lut(tlm_dmi_ext())
    {
@ -151,13 +157,16 @@ public:
    ~core_complex();

    inline void sync(uint64_t cycle) {
-        auto time = curr_clk * (cycle - last_sync_cycle);
-        quantum_keeper.inc(time);
+        auto core_inc = curr_clk * (cycle - last_sync_cycle);
+        auto incr = std::max(core_inc, std::max(ibus_inc, dbus_inc));
+        quantum_keeper.inc(incr);
        if (quantum_keeper.need_sync()) {
            wait(quantum_keeper.get_local_time());
            quantum_keeper.reset();
        }
        last_sync_cycle = cycle;
+        ibus_inc = sc_core::SC_ZERO_TIME;
+        dbus_inc = sc_core::SC_ZERO_TIME;
    }

    bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
@ -184,11 +193,12 @@ protected:
    void ext_irq_cb();
    void local_irq_cb();
    uint64_t last_sync_cycle = 0;
-    util::range_lut<tlm_dmi_ext> read_lut, write_lut;
+    util::range_lut<tlm_dmi_ext> fetch_lut, read_lut, write_lut;
    tlm_utils::tlm_quantumkeeper quantum_keeper;
    std::vector<uint8_t> write_buf;
    core_wrapper* cpu{nullptr};
    sc_core::sc_signal<sc_core::sc_time> curr_clk;
+    sc_core::sc_time ibus_inc, dbus_inc;
    core_trace* trc{nullptr};
    std::unique_ptr<scc::tick2time> t2t;
 private:
@ -196,7 +206,7 @@ private:
    std::vector<iss::vm_plugin *> plugin_list;

 };
-} /* namespace SiFive */
+} /* namespace tgfs */
 } /* namespace sysc */

 #endif /* _SYSC_CORE_COMPLEX_H_ */
--- a/src/vm/interp/vm_tgc_c.cpp
+++ b/src/vm/interp/vm_tgc_c.cpp
--- a/src/vm/tcc/vm_tgc_c.cpp
+++ b/src/vm/tcc/vm_tgc_c.cpp
Author	SHA1	Message	Date
Eyck Jentzsch	4dbc7433a5	fixes cause CSR handling	2023-06-12 17:38:56 +02:00
Eyck Jentzsch	99a9970ddd	fixes sysc compile issues	2023-06-12 09:58:24 +02:00
Eyck Jentzsch	0b5de90fb1	changes [m\|u]cause rd/wr handling	2023-06-11 18:29:58 +02:00
Eyck Jentzsch	60d07f2eb6	changes default loglevel to info for tgc-sim	2023-06-01 06:55:21 +02:00
Eyck Jentzsch	a123beb301	fixes duplicate variable declaration and templates	2023-05-27 10:20:49 +02:00
Eyck Jentzsch	ee6218279e	adapts to latest code gen changes	2023-05-25 12:52:30 +02:00
Eyck-Alexander Jentzsch	ce5b2e60b9	amends template to fix branching instructions	2023-05-22 17:00:36 +02:00
Eyck-Alexander Jentzsch	c792f50427	Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop	2023-05-16 21:57:32 +02:00
Eyck-Alexander Jentzsch	6ed7eafc5d	adds inital version of tcc backend	2023-05-16 21:51:35 +02:00
Eyck Jentzsch	8a5fe58d51	adds needed arch state members for TCC to tgc_c	2023-05-16 08:56:18 +02:00
Eyck Jentzsch	16cd6d5ff5	fixes core name deduction in cmake build script	2023-05-16 08:54:08 +02:00
Eyck-Alexander Jentzsch	ee2ded931d	adds remaining register offsets	2023-05-14 17:16:42 +02:00
Eyck Jentzsch	95ba5c901a	re-introduces last_branch register	2023-05-14 17:00:37 +02:00
Eyck Jentzsch	32848ec396	fixes build system and typo in wt_cache	2023-05-13 16:57:01 +02:00
Eyck Jentzsch	6789cf4c32	fixes case of unavailable backend	2023-05-12 15:45:53 +02:00
Eyck Jentzsch	3bc4884a9d	remove unneeded cmake include	2023-05-12 09:28:43 +02:00
Eyck Jentzsch	fd6b738168	changes compile dependencies	2023-05-11 23:43:12 +02:00
Eyck Jentzsch	afdf8fb97f	adds missing namespaces	2023-05-11 23:11:04 +02:00
Eyck Jentzsch	cfa7b72363	changes time handling at sockets	2023-05-06 19:57:29 +02:00
Eyck Jentzsch	d330307ed5	splits bus into 2 sockets for i/dbus	2023-05-04 21:59:31 +02:00
Eyck Jentzsch	916de2a26d	changes build setup to compile specific files if a core is specified	2023-05-04 16:08:33 +02:00
Eyck Jentzsch	aa70d8a54a	fixes CLIC to match clicinfo description in CLIC spec 11.04.2023	2023-05-02 17:22:13 +02:00
Eyck Jentzsch	b493745cd7	sets reset start time to 0	2023-05-02 11:21:42 +02:00
Eyck Jentzsch	f9e8e1d857	fixes core_complex wrt. tlm quantum and DMI	2023-05-02 11:13:25 +02:00
Eyck Jentzsch	974d64a627	adds logo to imported instance	2023-05-02 08:17:17 +02:00
Eyck Jentzsch	d70489cbb8	update import script to initialize broker	2023-05-02 07:58:48 +02:00
Eyck Jentzsch	d990f1cf5d	fixes reading of 64bit CSR register	2023-05-01 22:23:35 +02:00
Eyck Jentzsch	1672b01e62	adds WT cache functionality as mixin	2023-04-28 20:38:07 +02:00
Eyck Jentzsch	00b0f101ac	adapts to changes of instrumentation interface in dbt-rise-core	2023-04-28 20:38:07 +02:00
Rocco Jonack	54f75f92ea	improved testbench import; added prebuild FW for testing	2023-04-24 08:44:12 -07:00
Rocco Jonack	0304aac9e5	fixed some issues in import script; added README for reference; added initial testbench script(to be improved)	2023-04-19 05:20:58 -07:00
Eyck Jentzsch	8ff55d7b92	updates CWR dependent core_complex definition	2023-04-14 19:34:41 +02:00
Eyck Jentzsch	f626ee2684	fixes privilege wrapper for M/U to cope with 64bit	2023-04-05 15:38:25 +02:00
Eyck Jentzsch	a8a2782329	adds changes from latest CoreDSL description	2023-04-04 16:10:12 +02:00
Eyck Jentzsch	98dd329833	fixes CSR access rights	2023-04-04 09:23:08 +02:00
Eyck Jentzsch	6213445bc4	fixes 64bit behavior of CSR regs	2023-03-27 12:04:43 +02:00
Eyck Jentzsch	c5465bf9e2	fixes according to fixed generator	2023-03-26 14:44:15 +02:00
Eyck Jentzsch	d881cb6e63	fix data width of generated code	2023-03-26 12:12:34 +02:00
Eyck Jentzsch	2e4faa4d50	fixes mstatus mask	2023-03-25 09:14:56 +01:00
Eyck Jentzsch	8e1951f298	adds 64bit mstatus	2023-03-23 07:47:21 +01:00
Eyck Jentzsch	7efa924510	fixes m/uintstatus read	2023-03-17 10:51:39 +01:00
Eyck Jentzsch	febbc4fff0	fixes m/uintstatus read	2023-03-17 10:23:05 +01:00
Eyck Jentzsch	39b2788b7e	implements and fixes CLIC CSR behavior	2023-03-17 09:09:09 +01:00
Eyck Jentzsch	a943dd3bdf	fixes wrong array size which led to unintended CSR definitions	2023-03-15 14:16:08 +01:00
Eyck Jentzsch	fedbff5971	fixes xcause and u-mode clic CSRs	2023-03-15 12:27:39 +01:00
Eyck Jentzsch	c2758e8321	removes mscratchcsw from CLIC feature	2023-03-15 09:07:00 +01:00
Eyck Jentzsch	8be5fe71df	fixes template name typo	2023-03-12 07:42:09 +01:00
Eyck Jentzsch	3f7ce41b9d	fixes CLIC mtvt register behavior	2023-03-11 14:03:03 +01:00
Eyck Jentzsch	ad1cbedf00	adds back missing max irq functions	2023-03-11 12:47:10 +01:00
Eyck Jentzsch	83f54b5074	fixes CLICCFG settings	2023-03-11 08:48:03 +01:00
Eyck Jentzsch	a83928fd8c	fixes CSR/CLIC implementation	2023-03-10 20:40:21 +01:00