fixes CLIC to match clicinfo description in CLIC spec 11.04.2023

sets reset start time to 0
fixes core_complex wrt. tlm quantum and DMI
2023-05-02 17:22:13 +02:00 · 2023-05-02 11:21:42 +02:00 · 2023-05-02 11:13:25 +02:00 · 2023-05-02 08:17:17 +02:00 · 2023-05-02 07:58:48 +02:00 · 2023-05-01 22:23:35 +02:00
44 changed files with 5955 additions and 7551 deletions
--- a/.gitignore
+++ b/.gitignore
@@ -30,6 +30,5 @@ language.settings.xml
 /.gdbinit
 /*.out
 /dump.json
-/src-gen/
 /*.yaml
 /*.json
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -8,6 +8,7 @@ include(GNUInstallDirs)

 find_package(elfio QUIET)
 find_package(Boost COMPONENTS coroutine)
+find_package(jsoncpp)

 if(WITH_LLVM)
    if(DEFINED ENV{LLVM_HOME})
@@ -29,32 +30,34 @@ endif()
 add_subdirectory(softfloat)

 # library files
-FILE(GLOB TGC_SOURCES    ${CMAKE_CURRENT_SOURCE_DIR}/src/iss/*.cpp) 
-FILE(GLOB TGC_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp)
+FILE(GLOB GEN_SOURCES
+    ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
+	${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
+)

 set(LIB_SOURCES 
+    src/iss/plugin/instruction_count.cpp
+	src/iss/arch/tgc_c.cpp
+	src/vm/interp/vm_tgc_c.cpp
 	src/vm/fp_functions.cpp
-    src/plugin/instruction_count.cpp
-    
-    ${TGC_SOURCES}
-    ${TGC_VM_SOURCES}
+    ${GEN_SOURCES}
 )
-if(TARGET RapidJSON)
-    list(APPEND LIB_SOURCES src/plugin/cycle_estimate.cpp src/plugin/pctrace.cpp)
+if(TARGET RapidJSON OR TARGET RapidJSON::RapidJSON)
+    list(APPEND LIB_SOURCES src/iss/plugin/cycle_estimate.cpp src/iss/plugin/pctrace.cpp)
 endif()

 if(WITH_LLVM)
-	FILE(GLOB TGC_LLVM_SOURCES
-	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/llvm/vm_*.cpp
+	FILE(GLOB LLVM_GEN_SOURCES
+	    ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp
 	)
-	list(APPEND LIB_SOURCES ${TGC_LLVM_SOURCES})
+	list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
 endif()

 if(WITH_TCC)
-	FILE(GLOB TGC_TCC_SOURCES
+	FILE(GLOB TCC_GEN_SOURCES
 	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/tcc/vm_*.cpp
 	)
-	list(APPEND LIB_SOURCES ${TGC_TCC_SOURCES})
+	list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
 endif()

 # Define the library
@@ -69,16 +72,20 @@ if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
 elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
    target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
 endif()
-target_include_directories(${PROJECT_NAME} PUBLIC incl)
-target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp Boost::coroutine)
-if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
+target_include_directories(${PROJECT_NAME} PUBLIC src)
+target_include_directories(${PROJECT_NAME} PUBLIC src-gen)
+target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util Boost::coroutine)
+if(TARGET jsoncpp::jsoncpp)
+	target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp::jsoncpp)
+else()
+	target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp)
+endif()
+if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU" AND BUILD_SHARED_LIBS)
    target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-rise-core -Wl,--no-whole-archive)
 else()
    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-core)
 endif()
-if(TARGET CONAN_PKG::elfio)
-    target_link_libraries(${PROJECT_NAME} PUBLIC CONAN_PKG::elfio)
-elseif(TARGET elfio::elfio)
+if(TARGET elfio::elfio)
    target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
 else()
    message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
@@ -87,7 +94,9 @@ if(TARGET lz4::lz4)
    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_LZ4)
    target_link_libraries(${PROJECT_NAME} PUBLIC lz4::lz4)
 endif()
-if(TARGET RapidJSON)
+if(TARGET RapidJSON::RapidJSON)
+    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON::RapidJSON)
+elseif(TARGET RapidJSON)
    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON)
 endif()

@@ -117,6 +126,7 @@ project(tgc-sim)
 find_package(Boost COMPONENTS program_options thread REQUIRED)

 add_executable(${PROJECT_NAME} src/main.cpp)
+FILE(GLOB TGC_SOURCES  ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp) 
 foreach(F IN LISTS TGC_SOURCES)
    string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
    string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
@@ -163,12 +173,12 @@ if(SystemC_FOUND)
        string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
    endforeach()
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
    if(WITH_LLVM)
        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
    endif()
    
-	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/core_complex.h)
+	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
    set_target_properties(${PROJECT_NAME} PROPERTIES
      VERSION ${PROJECT_VERSION}
      FRAMEWORK FALSE
--- a/contrib/.gitignore
+++ b/contrib/.gitignore
@@ -0,0 +1,3 @@
+/results
+/cwr
+/*.xml
--- a/contrib/README.md
+++ b/contrib/README.md
@@ -0,0 +1,43 @@
+# Notes
+
+* requires conan version 1.59
+* requires decent cmake version 3.23
+
+Setup for tcsh:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+setenv TGFS_INSTALL_ROOT `pwd`/install
+setenv COWAREHOME <your SNPS PA installation>
+setenv SNPSLMD_LICENSE_FILE <your SNPS PA license file>
+source $COWAREHOME/SLS/linux/setup.csh pae
+setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
+setenv PATH $COWAREHOME/common/bin/:${PATH}
+setenv CC  $COWAREHOME/SLS/linux/common/bin/gcc
+setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```
+
+Setup for bash:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+export TGFS_INSTALL_ROOT `pwd`/install
+module load tools/pa/T-2022.06
+export SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM=1
+export CC=$COWAREHOME/SLS/linux/common/bin/gcc
+export CXX=$COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```
--- a/contrib/build.tcl
+++ b/contrib/build.tcl
@@ -16,7 +16,7 @@ namespace eval Specification {
                set libdir "${install_dir}/lib64"
                set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
                # Set the Linker paths.
-                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc"]
+                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc -lscc-sysc"]
            }
            default {
               puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"
--- a/contrib/hello.dis
+++ b/contrib/hello.dis
--- a/contrib/hello.elf
+++ b/contrib/hello.elf
--- a/contrib/minres.png
+++ b/contrib/minres.png
--- a/contrib/tgc_import.tcl
+++ b/contrib/tgc_import.tcl
@@ -6,14 +6,11 @@ proc getScriptDirectory {} {
    set scriptFolder [file dirname $dispScriptFile]
    return $scriptFolder
 }
-if { $::env(SNPS_VP_PRODUCT) == "PAULTRA" } {
    set hardware /HARDWARE/HW/HW
-} else {
-    set hardware /HARDWARE
-}

 set scriptDir [getScriptDirectory]
 set top_design_name core_complex
+set encap_name sysc::tgfs::${top_design_name}
 set clocks clk_i
 set resets rst_i
 set model_prefix "i_"
@@ -28,7 +25,8 @@ set model_postfix ""
 ::pct::set_update_existing_encaps_flag true
 ::pct::set_dynamic_port_arrays_flag true
 ::pct::set_import_scml_properties_flag true
-::pct::load_modules --set-category modules tgc_import.cc
+::pct::set_import_encap_prop_as_extra_prop_flag true
+::pct::load_modules --set-category modules ${scriptDir}/tgc_import.cc

 # Set Port Protocols correctly
 set block ${top_design_name}
@@ -38,13 +36,15 @@ foreach clock ${clocks} {
 foreach reset ${resets} {
    ::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
 }
-::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
+#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16

 # Set compile settings and look
 set block SYSTEM_LIBRARY:${top_design_name}
-::pct::set_encap_build_script $block/${top_design_name} $scriptDir/build.tcl
+::pct::set_encap_build_script $block/${encap_name} $scriptDir/build.tcl
 ::pct::set_background_color_rgb $block 255 255 255 255
-::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${top_design_name} 
+::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${encap_name} ${encap_name}() 
+::pct::set_bounds i_${top_design_name} 200 300 100 400
+::pct::set_image i_${top_design_name} "$scriptDir/minres.png" center center false true

 # export the result as component
 ::pct::export_system_library ${top_design_name}  ${top_design_name}.xml
--- a/contrib/tgc_import_tb.tcl
+++ b/contrib/tgc_import_tb.tcl
@@ -0,0 +1,68 @@
+source tgc_import.tcl
+set hardware /HARDWARE/HW/HW
+set FW_name ${scriptDir}/hello.elf
+
+puts "instantiate testbench elements"
+::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
+::pct::set_param_value i_Memory_Generic/MEM:protocol {Protocol Common Parameters} address_width 30
+#::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
+#::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
+#::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
+::pct::set_bounds i_Memory_Generic 1000 300 100 100
+
+::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
+::BLWizard::generateFramework i_Bus SBLTLM2FT  * {} \
+						{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
+::pct::set_bounds i_Bus 700 300 100 400
+::pct::create_connection C_init i_core_complex/initiator i_Bus/i_core_complex_initiator
+::pct::set_location_on_owner i_Bus/i_core_complex_initiator 10
+::pct::create_connection C_targ i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
+
+puts "instantiating clock manager"
+set clock "Clk"
+::hw::create_hw_instance "" GenericIPlib:ClockGenerator ${clock}_clock
+::pct::set_bounds ${clock}_clock 100 100 100 100
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period 1000
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period_unit sc_core::SC_PS
+
+puts "instantiating reset manager"
+set reset "Rst"
+ ::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 0
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
+::pct::set_bounds ${reset}_reset 300 100 100 100
+
+puts "connecting reset/clock"
+::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
+::pct::add_ports_to_connection C_clk i_Bus/Clk
+::pct::add_ports_to_connection C_clk i_Memory_Generic/CLK
+::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
+::pct::add_ports_to_connection C_rst i_Bus/Rst
+
+puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
+::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name}
+::pct::set_address $hardware/i_${top_design_name}/initiator:i_Memory_Generic/MEM 0x0
+::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 }
+
+::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::create_simulation_build_config Debug
+::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
+# add build settings and save design for next steps
+#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
+#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
+
+#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
+#::simulation::run_simulation Simulation
+
+#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
+#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
+#::pct::export_system "export"
+#::cd "export"
+#::scsh::open-project
+#::scsh::build
+#::scsh::elab sim
+::pct::save_system testbench.xml
--- a/gen_input/templates/CORENAME.cpp.gtl
+++ b/gen_input/templates/CORENAME.cpp.gtl
@@ -37,9 +37,9 @@ def getRegisterSizes(){
    return regs
 }
 %>
+#include "${coreDef.name.toLowerCase()}.h"
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
--- a/gen_input/templates/CORENAME_decoder.cpp.gtl
+++ b/gen_input/templates/CORENAME_decoder.cpp.gtl
@@ -0,0 +1,86 @@
+#include "${coreDef.name.toLowerCase()}.h"
+#include <vector>
+#include <array>
+#include <cstdlib>
+#include <algorithm>
+
+namespace iss {
+namespace arch {
+namespace {
+// according to
+// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
+#ifdef __GCC__
+constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
+#elif __cplusplus < 201402L
+constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
+constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
+#else
+constexpr size_t bit_count(uint32_t u) {
+    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
+    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
+}
+#endif
+
+using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
+
+/****************************************************************************
+ * start opcode definitions
+ ****************************************************************************/
+struct instruction_desriptor {
+    size_t length;
+    uint32_t value;
+    uint32_t mask;
+    opcode_e op;
+};
+
+const std::array<instruction_desriptor, ${instructions.size}> instr_descr = {{
+     /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+    {${instr.length}, ${instr.encoding}, ${instr.mask}, opcode_e::${instr.instruction.name}},<%}%>
+}};
+
+}
+
+template<>
+struct instruction_decoder<${coreDef.name.toLowerCase()}> {
+    using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
+    using code_word_t=traits<${coreDef.name.toLowerCase()}>::code_word_t;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
+
+    template<typename T>
+    unsigned decode_instruction(T);
+
+    instruction_decoder() {
+        for (auto instr : instr_descr) {
+            auto quadrant = instr.value & 0x3;
+            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+        }
+        for(auto& lut: qlut){
+            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+                return bit_count(a.mask) < bit_count(b.mask);
+            });
+        }
+    }
+};
+
+template<>
+unsigned instruction_decoder<${coreDef.name.toLowerCase()}>::decode_instruction<traits<${coreDef.name.toLowerCase()}>::code_word_t>(traits<${coreDef.name.toLowerCase()}>::code_word_t instr){
+    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
+        return !((instr&e.mask) ^ e.value );
+    });
+    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
+}
+
+
+std::unique_ptr<instruction_decoder<${coreDef.name.toLowerCase()}>> traits<${coreDef.name.toLowerCase()}>::get_decoder(){
+    return std::make_unique<instruction_decoder<${coreDef.name.toLowerCase()}>>();
+}
+
+}
+}
--- a/gen_input/templates/CORENAME_instr.yaml.gtl
+++ b/gen_input/templates/CORENAME_instr.yaml.gtl
@@ -12,5 +12,6 @@
 ${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %>
  - ${it.instruction.name}:
    encoding: ${it.encoding}
-    mask: ${it.mask}<%}}%>
+    mask: ${it.mask}<%if(it.attributes.size) {%>
+    attributes: ${it.attributes}<%}}}%>

--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@@ -36,11 +36,10 @@ def nativeTypeSize(int size){
    if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
 %>
-#include "../fp_functions.h"
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/iss.h>
 #include <iss/interp/vm_base.h>
 #include <util/logging.h>
@@ -73,6 +72,7 @@ public:
    using addr_t      = typename super::addr_t;
    using reg_t       = typename traits::reg_t;
    using mem_type_e  = typename traits::mem_type_e;
+    using opcode_e    = typename traits::opcode_e;
    
    vm_impl();

@@ -92,7 +92,7 @@ protected:
    using compile_ret_t = virt_addr_t;
    using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);

-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+    inline const char *name(size_t index){return index<traits::reg_aliases.size()?traits::reg_aliases[index]:"illegal";}

    typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
    virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
@@ -122,7 +122,7 @@ protected:
    inline void raise(uint16_t trap_id, uint16_t cause){
        auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
        this->core.trap_state = trap_val;
-        this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
+        this->template get_reg<uint${addrDataWidth}_t>(traits::NEXT_PC) = std::numeric_limits<uint${addrDataWidth}_t>::max();
    }

    inline void leave(unsigned lvl){
@@ -137,44 +137,6 @@ protected:
    using coro_t = boost::coroutines2::coroutine<void>::pull_type;
    std::vector<coro_t> spawn_blocks;

-    template<typename T>
-    T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
-    inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint8_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint16_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint32_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint64_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
    inline S sext(U from) {
        auto mask = (1ULL<<W) - 1;
@@ -183,6 +145,7 @@ protected:
    }
    
    inline void process_spawn_blocks() {
+        if(spawn_blocks.size()==0) return;
        for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
             if(*it){
                 (*it)();
@@ -193,6 +156,7 @@ protected:
 <%functions.each{ it.eachLine { %>
    ${it}<%}%>
 <%}%>
+
 private:
    /****************************************************************************
     * start opcode definitions
@@ -278,8 +242,8 @@ typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t
 template <typename ARCH>
 typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
    auto pc=start;
-    auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-    auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+    auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+    auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
    auto& trap_state = this->core.trap_state;
    auto& icount = this->core.icount;
    auto& cycle = this->core.cycle;
@@ -298,14 +262,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                    (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
            auto inst_id = decode_inst_id(instr);
            // pre execution stuff
+            this->core.last_branch = 0;
            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
            switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
            case arch::traits<ARCH>::opcode_e::${instr.name}: {
                <%instr.fields.eachLine{%>${it}
                <%}%>if(this->disass_enabled){
-		            /* generate console output when executing the command */
-		            <%instr.disass.eachLine{%>${it}
-		            <%}%>
+                    /* generate console output when executing the command */<%instr.disass.eachLine{%>
+                    ${it}<%}%>
                }
                // used registers<%instr.usedVariables.each{ k,v->
                if(v.isArray) {%>
@@ -313,9 +277,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
                <%}}%>// calculate next pc value
                *NEXT_PC = *PC + ${instr.length/8};
-		        // execute instruction
-		        <%instr.behavior.eachLine{%>${it}
-		        <%}%>TRAP_${instr.name}:break;
+                // execute instruction<%instr.behavior.eachLine{%>
+                ${it}<%}%>
+                TRAP_${instr.name}:break;
            }// @suppress("No break at end of case")<%}%>
            default: {
                *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
@@ -325,6 +289,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
            // post execution stuff
            process_spawn_blocks();
            if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
+            // if(!this->core.trap_state) // update trap state if there is a pending interrupt
+            //    this->core.trap_state = this->core.pending_trap;
            // trap check
            if(trap_state!=0){
                super::core.enter_trap(trap_state, pc.val, instr);
--- a/gen_input/templates/llvm/vm-vm_CORENAME.cpp.gtl
+++ b/gen_input/templates/llvm/vm-vm_CORENAME.cpp.gtl
@@ -30,10 +30,10 @@
 *
 *******************************************************************************/

-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/iss.h>
 #include <iss/llvm/vm_base.h>
 #include <util/logging.h>
--- a/incl/iss/arch/.gitignore
+++ b/incl/iss/arch/.gitignore
@@ -1 +0,0 @@
-/tgc_*.h
--- a/src-gen/.gitignore
+++ b/src-gen/.gitignore
@@ -0,0 +1,2 @@
+/iss
+/vm
--- a/incl/iss/arch/hwl.h
+++ b/incl/iss/arch/hwl.h
--- a/incl/iss/arch/riscv_hart_common.h
+++ b/incl/iss/arch/riscv_hart_common.h
@@ -51,12 +51,18 @@ enum riscv_csr {
    ustatus = 0x000,
    uie = 0x004,
    utvec = 0x005,
+    utvt = 0x007, //CLIC
    // User Trap Handling
    uscratch = 0x040,
    uepc = 0x041,
    ucause = 0x042,
    utval = 0x043,
    uip = 0x044,
+    uxnti = 0x045, //CLIC
+    uintstatus   = 0xCB1, // MRW Current interrupt levels (CLIC) - addr subject to change
+    uintthresh   = 0x047, // MRW Interrupt-level threshold (CLIC) - addr subject to change
+    uscratchcsw  = 0x048, // MRW Conditional scratch swap on priv mode change (CLIC)
+    uscratchcswl = 0x049, // MRW Conditional scratch swap on level change (CLIC)
    // User Floating-Point CSRs
    fflags = 0x001,
    frm = 0x002,
@@ -114,11 +120,10 @@ enum riscv_csr {
    mtval = 0x343,
    mip = 0x344,
    mxnti = 0x345, //CLIC
-    mintstatus   = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
+    mintstatus   = 0xFB1, // MRW Current interrupt levels (CLIC) - addr subject to change
+    mintthresh   = 0x347, // MRW Interrupt-level threshold (CLIC) - addr subject to change
    mscratchcsw  = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
    mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
-    mintthresh   = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
-    mclicbase    = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
    // Physical Memory Protection
    pmpcfg0 = 0x3A0,
    pmpcfg1 = 0x3A1,
@@ -216,6 +221,7 @@ struct vm_info {

 struct feature_config {
    uint64_t clic_base{0xc0000000};
+    unsigned clic_int_ctl_bits{4};
    unsigned clic_num_irq{16};
    unsigned clic_num_trigger{0};
    uint64_t tcm_base{0x10000000};
--- a/incl/iss/arch/riscv_hart_m_p.h
+++ b/incl/iss/arch/riscv_hart_m_p.h
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2021 MINRES Technologies GmbH
+ * Copyright (C) 2019 - 2023 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -172,17 +172,94 @@ public:
            return 0b00000000000000000001100010001000;
        }
    };
+
+    // specialization 64bit
+    template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint64_t>::value>::type> {
+    public:
+        BEGIN_BF_DECL(mstatus_t, T);
+        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
+        BF_FIELD(SD, 63, 1);
+        // value of XLEN for S-mode
+        BF_FIELD(SXL, 34, 2);
+        // value of XLEN for U-mode
+        BF_FIELD(UXL, 32, 2);
+        // Trap SRET
+        BF_FIELD(TSR, 22, 1);
+        // Timeout Wait
+        BF_FIELD(TW, 21, 1);
+        // Trap Virtual Memory
+        BF_FIELD(TVM, 20, 1);
+        // Make eXecutable Readable
+        BF_FIELD(MXR, 19, 1);
+        // permit Supervisor User Memory access
+        BF_FIELD(SUM, 18, 1);
+        // Modify PRiVilege
+        BF_FIELD(MPRV, 17, 1);
+        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
+        BF_FIELD(XS, 15, 2);
+        // floating-point unit status Off/Initial/Clean/Dirty
+        BF_FIELD(FS, 13, 2);
+        // machine previous privilege
+        BF_FIELD(MPP, 11, 2);
+        // supervisor previous privilege
+        BF_FIELD(SPP, 8, 1);
+        // previous machine interrupt-enable
+        BF_FIELD(MPIE, 7, 1);
+        // previous supervisor interrupt-enable
+        BF_FIELD(SPIE, 5, 1);
+        // previous user interrupt-enable
+        BF_FIELD(UPIE, 4, 1);
+        // machine interrupt-enable
+        BF_FIELD(MIE, 3, 1);
+        // supervisor interrupt-enable
+        BF_FIELD(SIE, 1, 1);
+        // user interrupt-enable
+        BF_FIELD(UIE, 0, 1);
+        END_BF_DECL();
+
+        mstatus_t mstatus;
+
+        static const reg_t mstatus_reset_val = 0x1800;
+
+        void write_mstatus(T val) {
+            auto mask = get_mask() &0xff; // MPP is hardcode as 0x3
+            auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
+            mstatus = new_val;
+        }
+
+        static constexpr T get_mask() {
+            //return 0x8000000f007ff9ddULL; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
+            //
+            //                +-TSR
+            //                |+-TW
+            //                ||+-TVM
+            //                |||+-MXR
+            //                ||||+-SUM
+            //                |||||+-MPRV
+            //                |||||| +-XS
+            //                |||||| | +-FS
+            //                |||||| | | +-MPP
+            //                |||||| | | |  +-SPP
+            //                |||||| | | |  |+-MPIE
+            //                ||||||/|/|/|  ||   +-MIE
+            return 0b00000000000000000001100010001000;
+        }
+    };
+
    using hart_state_type = hart_state<reg_t>;

    constexpr reg_t get_irq_mask() {
        return 0b100010001000; // only machine mode is supported
    }

+    constexpr bool has_compressed() {
+        return traits<BASE>::MISA_VAL&0b0100;
+    }
    constexpr reg_t get_pc_mask() {
-        return traits<BASE>::MISA_VAL&0b0100?~1:~3;
+        return has_compressed()?(reg_t)~1:(reg_t)~3;
    }

-    riscv_hart_m_p();
+    riscv_hart_m_p(feature_config cfg = feature_config{});
    virtual ~riscv_hart_m_p() = default;

    void reset(uint64_t address) override;
@@ -194,9 +271,9 @@ public:
    iss::status write(const address_type type, const access_type access, const uint32_t space,
            const uint64_t addr, const unsigned length, const uint8_t *const data) override;

-    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data, fault_data); }
-    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
-    virtual uint64_t leave_trap(uint64_t flags) override;
+    uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data, fault_data); }
+    uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
+    uint64_t leave_trap(uint64_t flags) override;

    const reg_t& get_mhartid() const { return mhartid_reg;	}
 	void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
@@ -208,14 +285,6 @@ public:

    iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }

-    void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
-        mem_read_cb = memReadCb;
-    }
-
-    void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
-        mem_write_cb = memWriteCb;
-    }
-
    void set_csr(unsigned addr, reg_t val){
        csr[addr & csr.page_addr_mask] = val;
    }
@@ -247,7 +316,9 @@ protected:

        uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }

-        void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+
+        bool is_branch_taken() override { return arch.last_branch; };

        riscv_hart_m_p<BASE, FEAT> &arch;
    };
@@ -285,7 +356,6 @@ protected:
    std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
    std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
    uint8_t clic_cfg_reg{0};
-    uint32_t clic_info_reg{0};
    std::array<uint32_t, 32> clic_inttrig_reg;
    union clic_int_reg_t {
        struct{
@@ -297,6 +367,8 @@ protected:
        uint32_t raw;
    };
    std::vector<clic_int_reg_t> clic_int_reg;
+    uint8_t clic_mprev_lvl{0};
+    uint8_t clic_mact_lvl{0};

    std::vector<uint8_t> tcm;

@@ -312,14 +384,16 @@ protected:
    iss::status read_time(unsigned addr, reg_t &val);
    iss::status read_status(unsigned addr, reg_t &val);
    iss::status write_status(unsigned addr, reg_t val);
+    iss::status read_cause(unsigned addr, reg_t &val);
    iss::status write_cause(unsigned addr, reg_t val);
    iss::status read_ie(unsigned addr, reg_t &val);
    iss::status write_ie(unsigned addr, reg_t val);
    iss::status read_ip(unsigned addr, reg_t &val);
    iss::status read_hartid(unsigned addr, reg_t &val);
    iss::status write_epc(unsigned addr, reg_t val);
-    iss::status write_intstatus(unsigned addr, reg_t val);
+    iss::status read_intstatus(unsigned addr, reg_t& val);
    iss::status write_intthresh(unsigned addr, reg_t val);
+    iss::status write_xtvt(unsigned addr, reg_t val);
    iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
    iss::status read_dcsr_reg(unsigned addr, reg_t &val);
    iss::status write_dcsr_reg(unsigned addr, reg_t val);
@@ -337,8 +411,6 @@ protected:
    }

    reg_t mhartid_reg{0x0};
-    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
-    std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;

    void check_interrupt();
    bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
@@ -346,30 +418,37 @@ protected:
    std::vector<std::function<mem_read_f>> memfn_read;
    std::vector<std::function<mem_write_f>> memfn_write;
    void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
-    uint64_t clic_base_addr{0};
-    unsigned clic_num_irq{0};
-    unsigned clic_num_trigger{0};
-    unsigned mcause_max_irq{16};
+    feature_config cfg;
+    unsigned mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
    inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
+    std::pair<std::function<mem_read_f>, std::function<mem_write_f>>
+    replace_mem_access(std::function<mem_read_f> rd, std::function<mem_write_f> wr){
+        std::pair<std::function<mem_read_f>, std::function<mem_write_f>> ret{hart_mem_rd_delegate, hart_mem_wr_delegate};
+        hart_mem_rd_delegate = rd;
+        hart_mem_wr_delegate = wr;
+        return ret;
+    }
+    std::function<mem_read_f> hart_mem_rd_delegate;
+    std::function<mem_write_f> hart_mem_wr_delegate;
 };

 template <typename BASE, features_e FEAT>
-riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
+riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
 : state()
-, instr_if(*this) {
+, instr_if(*this)
+, cfg(cfg) {
    // reset values
    csr[misa] = traits<BASE>::MISA_VAL;
    csr[mvendorid] = 0x669;
    csr[marchid] = traits<BASE>::MARCHID_VAL;
    csr[mimpid] = 1;
-    csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file

    uart_buf.str("");
    for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
-    for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
+    if(traits<BASE>::XLEN==32) for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
@@ -380,34 +459,40 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
    for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
    }
-    for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
+    if(traits<BASE>::XLEN==32) for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
        //csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    // common regs
-    const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
-    for(auto addr: addrs) {
+    const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
+    for(auto addr: roaddrs) {
+        csr_rd_cb[addr] = &this_class::read_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_null;
+    }
+    const std::array<unsigned, 4> rwaddrs{{mepc, mtvec, mscratch, mtval}};
+    for(auto addr: rwaddrs) {
        csr_rd_cb[addr] = &this_class::read_csr_reg;
        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    // special handling & overrides
    csr_rd_cb[time] = &this_class::read_time;
-    csr_rd_cb[timeh] = &this_class::read_time;
+    if(traits<BASE>::XLEN==32)  csr_rd_cb[timeh] = &this_class::read_time;
    csr_rd_cb[cycle] = &this_class::read_cycle;
-    csr_rd_cb[cycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle;
    csr_rd_cb[instret] = &this_class::read_instret;
-    csr_rd_cb[instreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret;

    csr_rd_cb[mcycle] = &this_class::read_cycle;
    csr_wr_cb[mcycle] = &this_class::write_cycle;
-    csr_rd_cb[mcycleh] = &this_class::read_cycle;
-    csr_wr_cb[mcycleh] = &this_class::write_cycle;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle;
    csr_rd_cb[minstret] = &this_class::read_instret;
    csr_wr_cb[minstret] = &this_class::write_instret;
-    csr_rd_cb[minstreth] = &this_class::read_instret;
-    csr_wr_cb[minstreth] = &this_class::write_instret;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret;
    csr_rd_cb[mstatus] = &this_class::read_status;
    csr_wr_cb[mstatus] = &this_class::write_status;
+    csr_rd_cb[mcause] = &this_class::read_cause;
    csr_wr_cb[mcause] = &this_class::write_cause;
    csr_rd_cb[mtvec] = &this_class::read_tvec;
    csr_wr_cb[mepc] = &this_class::write_epc;
@@ -422,43 +507,38 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
    csr_wr_cb[mimpid] = &this_class::write_null;
    if(FEAT & FEAT_CLIC) {
        csr_rd_cb[mtvt] = &this_class::read_csr_reg;
-        csr_wr_cb[mtvt] = &this_class::write_csr_reg;
-        csr_rd_cb[mxnti] = &this_class::read_csr_reg;
-        csr_wr_cb[mxnti] = &this_class::write_csr_reg;
-        csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
+        csr_wr_cb[mtvt] = &this_class::write_xtvt;
+//        csr_rd_cb[mxnti] = &this_class::read_csr_reg;
+//        csr_wr_cb[mxnti] = &this_class::write_csr_reg;
+        csr_rd_cb[mintstatus] = &this_class::read_intstatus;
        csr_wr_cb[mintstatus] = &this_class::write_null;
-        csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
-        csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
-        csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg;
-        csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
+//        csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
+//        csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
+//        csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg;
+//        csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
        csr_rd_cb[mintthresh] = &this_class::read_csr_reg;
        csr_wr_cb[mintthresh] = &this_class::write_intthresh;
-        csr_rd_cb[mclicbase] = &this_class::read_csr_reg;
-        csr_wr_cb[mclicbase] = &this_class::write_null;
-
-        clic_base_addr=0xC0000000;
-        clic_num_irq=16;
-        clic_int_reg.resize(clic_num_irq);
+        clic_int_reg.resize(cfg.clic_num_irq,  clic_int_reg_t{.raw=0});
        clic_cfg_reg=0x20;
-        clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + clic_num_irq;
-        mcause_max_irq=clic_num_irq+16;
-        insert_mem_range(clic_base_addr, 0x5000UL,
+        clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
+        csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
+        insert_mem_range(cfg.clic_base, 0x5000UL,
                [this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
                [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);});
    }
    if(FEAT & FEAT_TCM) {
-        tcm.resize(0x8000);
+        tcm.resize(cfg.tcm_size);
        std::function<mem_read_f> read_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t * const data) {
-            auto offset=addr.val-0x10000000;
+            auto offset=addr.val-this->cfg.tcm_base;
            std::copy(tcm.data() + offset, tcm.data() + offset + length, data);
            return iss::Ok;
        };
        std::function<mem_write_f> write_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {
-            auto offset=addr.val-0x10000000;
+            auto offset=addr.val-this->cfg.tcm_base;
            std::copy(data, data + length, tcm.data() + offset);
            return iss::Ok;
        };
-        insert_mem_range(0x10000000, 0x8000UL, read_clic_cb, write_clic_cb);
+        insert_mem_range(cfg.tcm_base, cfg.tcm_size, read_clic_cb, write_clic_cb);
    }
    if(FEAT & FEAT_DEBUG){
        csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg;
@@ -470,6 +550,12 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
        csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
        csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
    }
+    hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status {
+        return this->read_mem(a, l, d);
+    };
+    hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status {
+        return this->write_mem(a, l, d);
+    };
 }

 template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT>::load_file(std::string name, int type) {
@@ -477,10 +563,10 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
    if (fp) {
        std::array<char, 5> buf;
        auto n = fread(buf.data(), 1, 4, fp);
+        fclose(fp);
        if (n != 4) throw std::runtime_error("input file has insufficient size");
        buf[4] = 0;
        if (strcmp(buf.data() + 1, "ELF") == 0) {
-            fclose(fp);
            // Create elfio reader
            ELFIO::elfio reader;
            // Load ELF data
@@ -567,22 +653,22 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
    try {
        switch (space) {
        case traits<BASE>::MEM: {
-            auto alignment = is_fetch(access)? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
+            auto alignment = is_fetch(access)? (has_compressed()? 2 : 4) : length;
            if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                fault_data = addr;
                if (is_debug(access)) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1UL << 31); // issue trap 0
                return iss::Err;
            }
            try {
                if(!is_debug(access) && (addr&(alignment-1))){
-                    this->trap_state = 1<<31 | 4<<16;
+                    this->trap_state = (1UL << 31) | 4<<16;
                    fault_data=addr;
                    return iss::Err;
                }
                auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
                auto res = iss::Err;
-                if(!is_fetch(access) && memfn_range.size()){
+                if(access != access_type::FETCH && memfn_range.size()){
                    auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
                        return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
                    });
@@ -590,17 +676,17 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
                        auto idx = std::distance(std::begin(memfn_range), it);
                        res = memfn_read[idx](phys_addr, length, data);
                    } else
-                        res = read_mem( phys_addr, length, data);
+                        res = hart_mem_rd_delegate( phys_addr, length, data);
                } else {
-                    res = read_mem( phys_addr, length, data);
+                    res = hart_mem_rd_delegate( phys_addr, length, data);
                }
                if (unlikely(res != iss::Ok)){
-                    this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                    this->trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                    fault_data=addr;
                }
                return res;
            } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1UL << 31) | ta.id;
                fault_data=ta.addr;
                return iss::Err;
            }
@@ -626,7 +712,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
        }
        return iss::Ok;
    } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1UL << 31) | ta.id;
        fault_data=ta.addr;
        return iss::Err;
    }
@@ -664,12 +750,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
            if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                fault_data = addr;
                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1UL << 31); // issue trap 0
                return iss::Err;
            }
            try {
                if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
-                    this->trap_state = 1<<31 | 6<<16;
+                    this->trap_state = (1UL << 31) | 6<<16;
                    fault_data=addr;
                    return iss::Err;
                }
@@ -688,12 +774,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                    res = write_mem( phys_addr, length, data);
                }
                if (unlikely(res != iss::Ok)) {
-                    this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    this->trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
                    fault_data=addr;
                }
                return res;
            } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1UL << 31) | ta.id;
                fault_data=ta.addr;
                return iss::Err;
            }
@@ -753,7 +839,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
        }
        return iss::Ok;
    } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1UL << 31) | ta.id;
        fault_data=ta.addr;
        return iss::Err;
    }
@@ -803,7 +889,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
    if (addr == mcycle) {
        val = static_cast<reg_t>(cycle_val);
    } else if (addr == mcycleh) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
        val = static_cast<reg_t>(cycle_val >> 32);
    }
    return iss::Ok;
@@ -811,8 +896,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>

 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cycle(unsigned addr, reg_t val) {
    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if (addr == mcycleh)
-            return iss::Err;
        mcycle_csr = static_cast<uint64_t>(val);
    } else {
        if (addr == mcycle) {
@@ -829,7 +912,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
    if ((addr&0xff) == (minstret&0xff)) {
        val = static_cast<reg_t>(this->instret);
    } else if ((addr&0xff) == (minstreth&0xff)) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
        val = static_cast<reg_t>(this->instret >> 32);
    }
    return iss::Ok;
@@ -837,8 +919,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>

 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_instret(unsigned addr, reg_t val) {
    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if ((addr&0xff) == (minstreth&0xff))
-            return iss::Err;
        this->instret = static_cast<uint64_t>(val);
    } else {
        if ((addr&0xff) == (minstret&0xff)) {
@@ -863,7 +943,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_tvec(unsigned addr, reg_t &val) {
-    val = csr[mtvec] & ~2;
+    val = FEAT & features_e::FEAT_CLIC? csr[addr] : csr[addr] & ~2;
    return iss::Ok;
 }

@@ -878,8 +958,30 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
    return iss::Ok;
 }

+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_cause(unsigned addr, reg_t &val) {
+    auto res = csr[addr];
+    if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) {
+        val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16));
+        val |= clic_mprev_lvl<<16;
+        val |= state.mstatus.MPIE<<27;
+        val |= state.mstatus.MPP<<28;
+    } else
+        val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
+    return iss::Ok;
+}
+
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
-    csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))| (mcause_max_irq-1));
+    csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
+    if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) {
+        auto mask = ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16));
+        csr[addr] = (val & mask) | (csr[addr] & ~mask);
+        clic_mprev_lvl = ((val>>16)&0xff) | (1<<(8-cfg. clic_int_ctl_bits)) - 1;
+        state.mstatus.MPIE=(val>>27)&0x1;
+        state.mstatus.MPP=(val>>28)&0x3;
+    } else {
+        auto mask = ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
+        csr[addr] = (val & mask) | (csr[addr] & ~mask);
+    }
    return iss::Ok;
 }

@@ -951,15 +1053,26 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
    return iss::Ok;
 }

+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::read_intstatus(unsigned addr, reg_t& val) {
+	val = (clic_mact_lvl&0xff) <<24;
+    return iss::Ok;
+}
+
 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
-    csr[addr]= val &0xff;
+    csr[addr]= (val &0xff) | (1<<(cfg.clic_int_ctl_bits)) - 1;
+    return iss::Ok;
+}
+
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::write_xtvt(unsigned addr, reg_t val) {
+    csr[addr]= val & ~0x3fULL;
    return iss::Ok;
 }

 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
-    if(mem_read_cb) return mem_read_cb(paddr, length, data);
    switch (paddr.val) {
    case 0x0200BFF8: { // CLINT base, mtime reg
        if (sizeof(reg_t) < length) return iss::Err;
@@ -984,14 +1097,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned len

 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
-    if(mem_write_cb) return mem_write_cb(paddr, length, data);
    switch (paddr.val) {
    case 0x10013000: // UART0 base, TXFIFO reg
    case 0x10023000: // UART1 base, TXFIFO reg
        uart_buf << (char)data[0];
        if (((char)data[0]) == '\n' || data[0] == 0) {
-            // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
-            // '"<<uart_buf.str()<<"'";
+            LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send '"<<uart_buf.str()<<"'";
            std::cout << uart_buf.str();
            uart_buf.str("");
        }
@@ -1062,15 +1173,13 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le

 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length, uint8_t *const data) {
-    if(addr==clic_base_addr) { // cliccfg
+    if(addr==cfg.clic_base) { // cliccfg
        *data=clic_cfg_reg;
        for(auto i=1; i<length; ++i) *(data+i)=0;
-    } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+8)){ // clicinfo
-        read_reg_uint32(addr, clic_info_reg, data, length);
-    } else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0x40+clic_num_trigger*4)){ // clicinttrig
+    } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
        auto offset = ((addr&0x7fff)-0x40)/4;
        read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
-    } else if(addr>=(clic_base_addr+0x1000) && (addr+length)<=(clic_base_addr+clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
+    } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
        auto offset = ((addr&0x7fff)-0x1000)/4;
        read_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
    } else {
@@ -1081,17 +1190,15 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length

 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
-    if(addr==clic_base_addr) { // cliccfg
-        clic_cfg_reg = *data;
-        clic_cfg_reg&= 0x7e;
-//    } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+4)){ // clicinfo
-//        write_uint32(addr, clic_info_reg, data, length);
-    } else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0xC0)){ // clicinttrig
+    if(addr==cfg.clic_base) { // cliccfg
+        clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e);
+    } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
        auto offset = ((addr&0x7fff)-0x40)/4;
        write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
-    } else if(addr>=(clic_base_addr+0x1000) && (addr+length)<=(clic_base_addr+clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
+    } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
        auto offset = ((addr&0x7fff)-0x1000)/4;
        write_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
+        clic_int_reg[offset].raw &= 0xf0c70101; // clicIntCtlBits->0xf0, clicintattr->0xc7, clicintie->0x1, clicintip->0x1
    }
    return iss::Ok;
 }
@@ -1102,6 +1209,7 @@ template <typename BASE, features_e FEAT> inline void riscv_hart_m_p<BASE, FEAT>
 }

 template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check_interrupt() {
+    //TODO: Implement CLIC functionality
    //auto ideleg = csr[mideleg];
    // Multiple simultaneous interrupts and traps at the same privilege level are
    // handled in the following decreasing priority order:
@@ -1109,8 +1217,8 @@ template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check
    // any synchronous traps.
    auto ena_irq = csr[mip] & csr[mie];

-    bool mie = state.mstatus.MIE;
-    auto m_enabled = this->reg.PRIV < PRIV_M || (this->reg.PRIV == PRIV_M && mie);
+    bool mstatus_mie = state.mstatus.MIE;
+    auto m_enabled = this->reg.PRIV < PRIV_M || mstatus_mie;
    auto enabled_interrupts = m_enabled ? ena_irq : 0;

    if (enabled_interrupts != 0) {
@@ -1126,7 +1234,7 @@ template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check
 template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
    // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
    // calculate and write mcause val
-    auto trap_id = bit_sub<0, 16>(flags);
+    auto const trap_id = bit_sub<0, 16>(flags);
    auto cause = bit_sub<16, 15>(flags);
    // calculate effective privilege level
    unsigned new_priv = PRIV_M;
@@ -1146,7 +1254,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
            csr[mtval] = static_cast<reg_t>(addr);
            break;
        case 2:
-            csr[mtval] = (instr & 0x3)==3?instr:instr&0xffff;
+            csr[mtval] = (!has_compressed() || (instr & 0x3)==3)?instr:instr&0xffff;
            break;
        case 3:
            if((FEAT & FEAT_DEBUG) && (csr[dcsr] & 0x8000)) {
@@ -1182,11 +1290,19 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
    state.mstatus.MIE = false;

    // get trap vector
-    auto ivec = csr[mtvec];
-    // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
+    auto xtvec = csr[mtvec];
+    // calculate adds// set NEXT_PC to trap addressess to jump to based on MODE
+    if((FEAT & features_e::FEAT_CLIC) && trap_id!=0 && (xtvec & 0x3UL)==3UL) {
+        reg_t data;
+        auto ret = read(address_type::LOGICAL, access_type::READ, 0, csr[mtvt], sizeof(reg_t), reinterpret_cast<uint8_t*>(&data));
+        if(ret == iss::Err)
+            return this->reg.PC;
+        this->reg.NEXT_PC = data;
+    } else {
        // bits in mtvec
-    this->reg.NEXT_PC = ivec & ~0x3UL;
-    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
+        this->reg.NEXT_PC = xtvec & ~0x3UL;
+        if ((xtvec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
+    }
    // reset trap state
    this->reg.PRIV = new_priv;
    this->trap_state = 0;
@@ -1210,6 +1326,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::l
    this->reg.NEXT_PC = csr[mepc] & get_pc_mask();
    CLOG(INFO, disass) << "Executing xRET";
    check_interrupt();
+    this->trap_state = this->pending_trap;
    return this->reg.NEXT_PC;
 }

--- a/incl/iss/arch/riscv_hart_msu_vp.h
+++ b/incl/iss/arch/riscv_hart_msu_vp.h
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, 2021 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -312,14 +312,6 @@ public:

    iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }

-    void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
-        mem_read_cb = memReadCb;
-    }
-
-    void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
-        mem_write_cb = memWriteCb;
-    }
-
    void set_csr(unsigned addr, reg_t val){
        csr[addr & csr.page_addr_mask] = val;
    }
@@ -348,7 +340,9 @@ protected:

        uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }

-        virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+
+        bool is_branch_taken() override { return arch.last_branch; };

        riscv_hart_msu_vp<BASE> &arch;
    };
@@ -422,8 +416,6 @@ private:
    }

    reg_t mhartid_reg{0x0};
-    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
-    std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;

 protected:
    void check_interrupt();
@@ -853,7 +845,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_reg(unsigned
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigned addr, reg_t &val) {
    auto cycle_val = this->icount + cycle_offset;
    if (addr == mcycle) {
        val = static_cast<reg_t>(cycle_val);
@@ -864,7 +856,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned a
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned addr, reg_t val) {
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_cycle(unsigned addr, reg_t val) {
    if (sizeof(typename traits<BASE>::reg_t) != 4) {
        if (addr == mcycleh)
            return iss::Err;
@@ -880,7 +872,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned addr, reg_t &val) {
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_instret(unsigned addr, reg_t &val) {
    if ((addr&0xff) == (minstret&0xff)) {
        val = static_cast<reg_t>(this->reg.instret);
    } else if ((addr&0xff) == (minstreth&0xff)) {
@@ -890,7 +882,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigned addr, reg_t val) {
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_instret(unsigned addr, reg_t val) {
    if (sizeof(typename traits<BASE>::reg_t) != 4) {
        if ((addr&0xff) == (minstreth&0xff))
            return iss::Err;
@@ -906,7 +898,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigne
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned addr, reg_t &val) {
    uint64_t time_val = this->icount / (100000000 / 32768 - 1); //-> ~3052;
    if (addr == time) {
        val = static_cast<reg_t>(time_val);
@@ -917,7 +909,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned ad
    return iss::Ok;
 }

-template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_tvec(unsigned addr, reg_t &val) {
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_tvec(unsigned addr, reg_t &val) {
    val = csr[addr] & ~2;
    return iss::Ok;
 }
@@ -1031,7 +1023,6 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_fcsr(unsigne

 template <typename BASE>
 iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
-    if(mem_read_cb) return mem_read_cb(paddr, length, data);
    switch (paddr.val) {
    case 0x0200BFF8: { // CLINT base, mtime reg
        if (sizeof(reg_t) < length) return iss::Err;
@@ -1056,7 +1047,6 @@ iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length

 template <typename BASE>
 iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
-    if(mem_write_cb) return mem_write_cb(paddr, length, data);
    switch (paddr.val) {
    case 0x10013000: // UART0 base, TXFIFO reg
    case 0x10023000: // UART1 base, TXFIFO reg
--- a/incl/iss/arch/riscv_hart_mu_p.h
+++ b/incl/iss/arch/riscv_hart_mu_p.h
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2021 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -181,6 +181,89 @@ public:
 #endif
        }
    };
+
+    // specialization 64bit
+    template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint64_t>::value>::type> {
+    public:
+        BEGIN_BF_DECL(mstatus_t, T);
+        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
+        BF_FIELD(SD, 63, 1);
+        // value of XLEN for S-mode
+        BF_FIELD(SXL, 34, 2);
+        // value of XLEN for U-mode
+        BF_FIELD(UXL, 32, 2);
+        // Trap SRET
+        BF_FIELD(TSR, 22, 1);
+        // Timeout Wait
+        BF_FIELD(TW, 21, 1);
+        // Trap Virtual Memory
+        BF_FIELD(TVM, 20, 1);
+        // Make eXecutable Readable
+        BF_FIELD(MXR, 19, 1);
+        // permit Supervisor User Memory access
+        BF_FIELD(SUM, 18, 1);
+        // Modify PRiVilege
+        BF_FIELD(MPRV, 17, 1);
+        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
+        BF_FIELD(XS, 15, 2);
+        // floating-point unit status Off/Initial/Clean/Dirty
+        BF_FIELD(FS, 13, 2);
+        // machine previous privilege
+        BF_FIELD(MPP, 11, 2);
+        // supervisor previous privilege
+        BF_FIELD(SPP, 8, 1);
+        // previous machine interrupt-enable
+        BF_FIELD(MPIE, 7, 1);
+        // previous supervisor interrupt-enable
+        BF_FIELD(SPIE, 5, 1);
+        // previous user interrupt-enable
+        BF_FIELD(UPIE, 4, 1);
+        // machine interrupt-enable
+        BF_FIELD(MIE, 3, 1);
+        // supervisor interrupt-enable
+        BF_FIELD(SIE, 1, 1);
+        // user interrupt-enable
+        BF_FIELD(UIE, 0, 1);
+        END_BF_DECL();
+
+        mstatus_t mstatus;
+
+        static const reg_t mstatus_reset_val = 0x1800;
+
+        void write_mstatus(T val, unsigned priv_lvl) {
+            auto mask = get_mask(priv_lvl);
+            auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
+            mstatus = new_val;
+        }
+
+        static constexpr uint64_t get_mask(unsigned priv_lvl) {
+#if __cplusplus < 201402L
+            return priv_lvl == PRIV_U ? 0x011ULL : priv_lvl == PRIV_S ? 0x000de133ULL : 0x007ff9ddULL;
+#else
+            switch (priv_lvl) {
+            case PRIV_U: return 0x00000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001
+            default:
+            //       +-SD
+            //       |        +-TSR
+            //       |        |+-TW
+            //       |        ||+-TVM
+            //       |        |||+-MXR
+            //       |        ||||+-SUM
+            //       |        |||||+-MPRV
+            //       |        |||||| +-XS
+            //       |        |||||| | +-FS
+            //       |        |||||| | | +-MPP
+            //       |        |||||| | | |  +-SPP
+            //       |        |||||| | | |  |+-MPIE
+            //       |        |||||| | | |  ||  +-UPIE
+            //       |        ||||||/|/|/|  ||  |+-MIE
+            //       |        ||||||/|/|/|  ||  ||  +-UIE
+            return 0b00000000000000000001100010011001;
+            }
+#endif
+        }
+    };
+
    using hart_state_type = hart_state<reg_t>;

    constexpr reg_t get_irq_mask(size_t mode) {
@@ -193,8 +276,11 @@ public:
        return m[mode];
    }

+    constexpr bool has_compressed() {
+        return traits<BASE>::MISA_VAL&0b0100;
+    }
    constexpr reg_t get_pc_mask() {
-        return traits<BASE>::MISA_VAL&0b0100?~1:~3;
+        return has_compressed()?~1:~3;
    }

    riscv_hart_mu_p(feature_config cfg = feature_config{});
@@ -223,14 +309,6 @@ public:

    iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }

-    void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
-        mem_read_cb = memReadCb;
-    }
-
-    void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
-        mem_write_cb = memWriteCb;
-    }
-
    void set_csr(unsigned addr, reg_t val){
        csr[addr & csr.page_addr_mask] = val;
    }
@@ -250,26 +328,26 @@ protected:
         */
        const std::string core_type_name() const override { return traits<BASE>::core_type; }

-        virtual uint64_t get_pc() { return arch.get_pc(); };
+        uint64_t get_pc() override { return arch.reg.PC; };

-        virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };

        uint64_t get_instr_word() override { return arch.instruction; }

-        uint64_t get_instr_count() { return arch.icount; }
+        uint64_t get_instr_count() override { return arch.icount; }

        uint64_t get_pendig_traps() override { return arch.trap_state; }

        uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }

-        virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+
+        bool is_branch_taken() override { return arch.last_branch; };

        riscv_hart_mu_p<BASE, FEAT> &arch;
    };

    friend struct riscv_instrumentation_if;
-    addr_t get_pc() { return this->reg.PC; }
-    addr_t get_next_pc() { return this->reg.NEXT_PC; }

    virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
    virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
@@ -302,7 +380,6 @@ protected:
    std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
    std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
    uint8_t clic_cfg_reg{0};
-    uint32_t clic_info_reg{0};
    std::array<uint32_t, 32> clic_inttrig_reg;
    union clic_int_reg_t {
        struct{
@@ -314,6 +391,8 @@ protected:
        uint32_t raw;
    };
    std::vector<clic_int_reg_t> clic_int_reg;
+    uint8_t clic_mprev_lvl{0}, clic_uprev_lvl{0};
+    uint8_t clic_mact_lvl{0}, clic_uact_lvl{0};

    std::vector<uint8_t> tcm;

@@ -329,6 +408,7 @@ protected:
    iss::status read_time(unsigned addr, reg_t &val);
    iss::status read_status(unsigned addr, reg_t &val);
    iss::status write_status(unsigned addr, reg_t val);
+    iss::status read_cause(unsigned addr, reg_t &val);
    iss::status write_cause(unsigned addr, reg_t val);
    iss::status read_ie(unsigned addr, reg_t &val);
    iss::status write_ie(unsigned addr, reg_t val);
@@ -337,8 +417,9 @@ protected:
    iss::status write_edeleg(unsigned addr, reg_t val);
    iss::status read_hartid(unsigned addr, reg_t &val);
    iss::status write_epc(unsigned addr, reg_t val);
-    iss::status write_intstatus(unsigned addr, reg_t val);
+    iss::status read_intstatus(unsigned addr, reg_t& val);
    iss::status write_intthresh(unsigned addr, reg_t val);
+    iss::status write_xtvt(unsigned addr, reg_t val);
    iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
    iss::status read_dcsr_reg(unsigned addr, reg_t &val);
    iss::status write_dcsr_reg(unsigned addr, reg_t val);
@@ -357,8 +438,6 @@ protected:
    }

    reg_t mhartid_reg{0x0};
-    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
-    std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;

    void check_interrupt();
    bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
@@ -367,8 +446,18 @@ protected:
    std::vector<std::function<mem_write_f>> memfn_write;
    void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
    feature_config cfg;
-    unsigned mcause_max_irq{16};
+    unsigned mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
    inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
+
+    std::pair<std::function<mem_read_f>, std::function<mem_write_f>>
+    replace_mem_access(std::function<mem_read_f> rd, std::function<mem_write_f> wr){
+        std::pair<std::function<mem_read_f>, std::function<mem_write_f>> ret{hart_mem_rd_delegate, hart_mem_wr_delegate};
+        hart_mem_rd_delegate = rd;
+        hart_mem_wr_delegate = wr;
+        return ret;
+    }
+    std::function<mem_read_f> hart_mem_rd_delegate;
+    std::function<mem_write_f> hart_mem_wr_delegate;
 };

 template <typename BASE, features_e FEAT>
@@ -381,14 +470,13 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
    csr[mvendorid] = 0x669;
    csr[marchid] = traits<BASE>::MARCHID_VAL;
    csr[mimpid] = 1;
-    csr[mclicbase] = cfg.clic_base; // TODO: should be taken from YAML file

    uart_buf.str("");
    for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
-    for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
+    if(traits<BASE>::XLEN==32) for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
@@ -399,38 +487,43 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
    for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
    }
-    for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
+    if(traits<BASE>::XLEN==32) for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
        csr_rd_cb[addr] = &this_class::read_null;
        //csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    // common regs
-    const std::array<unsigned, 14> addrs{{
-        misa, mvendorid, marchid, mimpid,
-        mepc, mtvec, mscratch, mcause, mtval,
-        uepc, utvec, uscratch, ucause, utval,
+    const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
+    for(auto addr: roaddrs) {
+        csr_rd_cb[addr] = &this_class::read_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_null;
+    }
+    const std::array<unsigned, 8> rwaddrs{{
+        mepc, mtvec, mscratch, mtval,
+        uepc, utvec, uscratch, utval,
    }};
-    for(auto addr: addrs) {
+    for(auto addr: rwaddrs) {
        csr_rd_cb[addr] = &this_class::read_csr_reg;
        csr_wr_cb[addr] = &this_class::write_csr_reg;
    }
    // special handling & overrides
    csr_rd_cb[time] = &this_class::read_time;
-    csr_rd_cb[timeh] = &this_class::read_time;
+    if(traits<BASE>::XLEN==32)  csr_rd_cb[timeh] = &this_class::read_time;
    csr_rd_cb[cycle] = &this_class::read_cycle;
-    csr_rd_cb[cycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle;
    csr_rd_cb[instret] = &this_class::read_instret;
-    csr_rd_cb[instreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret;

    csr_rd_cb[mcycle] = &this_class::read_cycle;
    csr_wr_cb[mcycle] = &this_class::write_cycle;
-    csr_rd_cb[mcycleh] = &this_class::read_cycle;
-    csr_wr_cb[mcycleh] = &this_class::write_cycle;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle;
    csr_rd_cb[minstret] = &this_class::read_instret;
    csr_wr_cb[minstret] = &this_class::write_instret;
-    csr_rd_cb[minstreth] = &this_class::read_instret;
-    csr_wr_cb[minstreth] = &this_class::write_instret;
+    if(traits<BASE>::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret;
+    if(traits<BASE>::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret;
    csr_rd_cb[mstatus] = &this_class::read_status;
    csr_wr_cb[mstatus] = &this_class::write_status;
+    csr_rd_cb[mcause] = &this_class::read_cause;
    csr_wr_cb[mcause] = &this_class::write_cause;
    csr_rd_cb[mtvec] = &this_class::read_tvec;
    csr_wr_cb[mepc] = &this_class::write_epc;
@@ -451,7 +544,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
            csr_rd_cb[i] = &this_class::read_csr_reg;
            csr_wr_cb[i] = &this_class::write_csr_reg;
        }
-        for(size_t i=pmpcfg0; i<=pmpcfg3; ++i){
+        for(size_t i=pmpcfg0; i<pmpcfg0+16/sizeof(reg_t); ++i){
            csr_rd_cb[i] = &this_class::read_csr_reg;
            csr_wr_cb[i] = &this_class::write_pmpcfg_reg;
        }
@@ -468,29 +561,37 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
        csr_wr_cb[uepc] = &this_class::write_epc;
        csr_rd_cb[ustatus] = &this_class::read_status;
        csr_wr_cb[ustatus] = &this_class::write_status;
+        csr_rd_cb[ucause] = &this_class::read_cause;
        csr_wr_cb[ucause] = &this_class::write_cause;
        csr_rd_cb[utvec] = &this_class::read_tvec;
    }
    if(FEAT & FEAT_CLIC) {
        csr_rd_cb[mtvt] = &this_class::read_csr_reg;
-        csr_wr_cb[mtvt] = &this_class::write_csr_reg;
-        csr_rd_cb[mxnti] = &this_class::read_csr_reg;
-        csr_wr_cb[mxnti] = &this_class::write_csr_reg;
-        csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
+        csr_wr_cb[mtvt] = &this_class::write_xtvt;
+//        csr_rd_cb[mxnti] = &this_class::read_csr_reg;
+//        csr_wr_cb[mxnti] = &this_class::write_csr_reg;
+        csr_rd_cb[mintstatus] = &this_class::read_intstatus;
        csr_wr_cb[mintstatus] = &this_class::write_null;
-        csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
-        csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
-        csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg;
-        csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
+//        csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
+//        csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
+//        csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg;
+//        csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
        csr_rd_cb[mintthresh] = &this_class::read_csr_reg;
        csr_wr_cb[mintthresh] = &this_class::write_intthresh;
-        csr_rd_cb[mclicbase] = &this_class::read_csr_reg;
-        csr_wr_cb[mclicbase] = &this_class::write_null;
-
-        clic_int_reg.resize(cfg.clic_num_irq);
-        clic_cfg_reg=0x20;
-        clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq;
-        mcause_max_irq=cfg.clic_num_irq+16;
+        if(FEAT & FEAT_EXT_N){
+            csr_rd_cb[utvt] = &this_class::read_csr_reg;
+            csr_wr_cb[utvt] = &this_class::write_xtvt;
+            csr_rd_cb[uintstatus] = &this_class::read_intstatus;
+            csr_wr_cb[uintstatus] = &this_class::write_null;
+            csr_rd_cb[uintthresh] = &this_class::read_csr_reg;
+            csr_wr_cb[uintthresh] = &this_class::write_intthresh;
+        }
+        clic_int_reg.resize(cfg.clic_num_irq,  clic_int_reg_t{.raw=0});
+        clic_cfg_reg=0x30;
+        clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
+        clic_uact_lvl = clic_uprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
+        csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
+        csr[uintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
        insert_mem_range(cfg.clic_base, 0x5000UL,
                [this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
                [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);});
@@ -519,6 +620,12 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
        csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
        csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
    }
+    hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status {
+        return this->read_mem(a, l, d);
+    };
+    hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status {
+        return this->write_mem(a, l, d);
+    };
 }

 template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT>::load_file(std::string name, int type) {
@@ -526,10 +633,10 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
    if (fp) {
        std::array<char, 5> buf;
        auto n = fread(buf.data(), 1, 4, fp);
+        fclose(fp);
        if (n != 4) throw std::runtime_error("input file has insufficient size");
        buf[4] = 0;
        if (strcmp(buf.data() + 1, "ELF") == 0) {
-            fclose(fp);
            // Create elfio reader
            ELFIO::elfio reader;
            // Load ELF data
@@ -619,9 +726,10 @@ template <typename BASE, features_e FEAT> bool riscv_hart_mu_p<BASE, FEAT>::pmp_
    constexpr auto PMP_NAPOT =0x3U;
    reg_t base = 0;
    auto any_active = false;
+    auto const cfg_reg_size=sizeof(reg_t);
    for (size_t i = 0; i < 16; i++) {
        reg_t tor = csr[pmpaddr0+i] << PMP_SHIFT;
-        uint8_t cfg = csr[pmpcfg0+(i/4)]>>(i%4);
+        uint8_t cfg = csr[pmpcfg0+(i/cfg_reg_size)]>>(i%cfg_reg_size);
        if (cfg & PMP_A) {
            any_active=true;
            auto pmp_a = (cfg & PMP_A) >> 3;
@@ -708,20 +816,20 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                if(!pmp_check(access, addr, length) && !is_debug(access)) {
                    fault_data = addr;
                    if (is_debug(access)) throw trap_access(0, addr);
-                    this->trap_state = (1 << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1
+                    this->trap_state = (1UL << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1
                    return iss::Err;
                }
            }
-            auto alignment = is_fetch(access)? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
+            auto alignment = is_fetch(access)? (has_compressed()? 2 : 4) : length;
            if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                fault_data = addr;
                if (is_debug(access)) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1UL << 31); // issue trap 0
                return iss::Err;
            }
            try {
                if(!is_debug(access) && (addr&(alignment-1))){
-                    this->trap_state = 1<<31 | 4<<16;
+                    this->trap_state = (1UL << 31) | 4<<16;
                    fault_data=addr;
                    return iss::Err;
                }
@@ -735,17 +843,17 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                        auto idx = std::distance(std::begin(memfn_range), it);
                        res = memfn_read[idx](phys_addr, length, data);
                    } else
-                        res = read_mem( phys_addr, length, data);
+                        res = hart_mem_rd_delegate( phys_addr, length, data);
                } else {
-                    res = read_mem( phys_addr, length, data);
+                    res = hart_mem_rd_delegate( phys_addr, length, data);
                }
                if (unlikely(res != iss::Ok)){
-                    this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                    this->trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                    fault_data=addr;
                }
                return res;
            } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1UL << 31) | ta.id;
                fault_data=ta.addr;
                return iss::Err;
            }
@@ -771,7 +879,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
        }
        return iss::Ok;
    } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1UL << 31) | ta.id;
        fault_data=ta.addr;
        return iss::Err;
    }
@@ -810,19 +918,19 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) {
                    fault_data = addr;
                    if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                    this->trap_state = (1 << 31) | (7 << 16); // issue trap 1
+                    this->trap_state = (1UL << 31) | (7 << 16); // issue trap 1
                    return iss::Err;
                }
            }
            if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                fault_data = addr;
                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1UL << 31); // issue trap 0
                return iss::Err;
            }
            try {
                if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
-                    this->trap_state = 1<<31 | 6<<16;
+                    this->trap_state = (1UL << 31) | 6<<16;
                    fault_data=addr;
                    return iss::Err;
                }
@@ -836,17 +944,17 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                        auto idx = std::distance(std::begin(memfn_range), it);
                        res = memfn_write[idx]( phys_addr, length, data);
                    } else
-                        res = write_mem( phys_addr, length, data);
+                        res = hart_mem_wr_delegate( phys_addr, length, data);
                } else {
-                    res = write_mem( phys_addr, length, data);
+                    res = hart_mem_wr_delegate( phys_addr, length, data);
                }
                if (unlikely(res != iss::Ok)) {
-                    this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    this->trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
                    fault_data=addr;
                }
                return res;
            } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1UL << 31) | ta.id;
                fault_data=ta.addr;
                return iss::Err;
            }
@@ -906,7 +1014,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
        }
        return iss::Ok;
    } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1UL << 31) | ta.id;
        fault_data=ta.addr;
        return iss::Err;
    }
@@ -956,7 +1064,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
    if (addr == mcycle) {
        val = static_cast<reg_t>(cycle_val);
    } else if (addr == mcycleh) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
        val = static_cast<reg_t>(cycle_val >> 32);
    }
    return iss::Ok;
@@ -964,8 +1071,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT

 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_cycle(unsigned addr, reg_t val) {
    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if (addr == mcycleh)
-            return iss::Err;
        mcycle_csr = static_cast<uint64_t>(val);
    } else {
        if (addr == mcycle) {
@@ -982,7 +1087,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
    if ((addr&0xff) == (minstret&0xff)) {
        val = static_cast<reg_t>(this->instret);
    } else if ((addr&0xff) == (minstreth&0xff)) {
-        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
        val = static_cast<reg_t>(this->instret >> 32);
    }
    return iss::Ok;
@@ -990,8 +1094,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT

 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_instret(unsigned addr, reg_t val) {
    if (sizeof(typename traits<BASE>::reg_t) != 4) {
-        if ((addr&0xff) == (minstreth&0xff))
-            return iss::Err;
        this->instret = static_cast<uint64_t>(val);
    } else {
        if ((addr&0xff) == (minstret&0xff)) {
@@ -1016,24 +1118,60 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_tvec(unsigned addr, reg_t &val) {
-    val = csr[addr] & ~2;
+    val = FEAT & features_e::FEAT_CLIC? csr[addr] : csr[addr] & ~2;
    return iss::Ok;
 }
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_status(unsigned addr, reg_t &val) {
-    auto req_priv_lvl = (addr >> 8) & 0x3;
-    val = state.mstatus & hart_state_type::get_mask(req_priv_lvl);
+    val = state.mstatus & hart_state_type::get_mask((addr >> 8) & 0x3);
    return iss::Ok;
 }

 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_status(unsigned addr, reg_t val) {
-    auto req_priv_lvl = (addr >> 8) & 0x3;
-    state.write_mstatus(val, req_priv_lvl);
+    state.write_mstatus(val, (addr >> 8) & 0x3);
    check_interrupt();
    return iss::Ok;
 }

+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_cause(unsigned addr, reg_t &val) {
+    if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) {
+        val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16));
+        auto mode = (addr >> 8) & 0x3;
+        switch(mode) {
+        case 0:
+            val |= clic_uprev_lvl<<16;
+            val |= state.mstatus.UPIE<<27;
+            break;
+        default:
+            val |= clic_mprev_lvl<<16;
+            val |= state.mstatus.MPIE<<27;
+            val |= state.mstatus.MPP<<28;
+            break;
+        }
+    } else
+        val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
+    return iss::Ok;
+}
+
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
-    csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1))|(mcause_max_irq-1));
+    if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) {
+        auto mask = ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16));
+        csr[addr] = (val & mask) | (csr[addr] & ~mask);
+        auto mode = (addr >> 8) & 0x3;
+        switch(mode) {
+        case 0:
+            clic_uprev_lvl = ((val>>16)&0xff) | (1<<(8-cfg. clic_int_ctl_bits)) - 1;
+            state.mstatus.UPIE=(val>>27)&0x1;
+            break;
+        default:
+            clic_mprev_lvl = ((val>>16)&0xff) | (1<<(8-cfg. clic_int_ctl_bits)) - 1;
+            state.mstatus.MPIE=(val>>27)&0x1;
+            state.mstatus.MPP=(val>>28)&0x3;
+            break;
+        }
+    } else {
+        auto mask = ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
+        csr[addr] = (val & mask) | (csr[addr] & ~mask);
+    }
    return iss::Ok;
 }

@@ -1121,15 +1259,29 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
    return iss::Ok;
 }

+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::read_intstatus(unsigned addr, reg_t& val) {
+    auto mode = (addr >> 8) & 0x3;
+    val = clic_uact_lvl&0xff;
+    if(mode==0x3)
+        val += (clic_mact_lvl&0xff) <<24;
+    return iss::Ok;
+}
+
 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
-    csr[addr]= val &0xff;
+    csr[addr]= (val &0xff) | (1<<(cfg.clic_int_ctl_bits)) - 1;
+    return iss::Ok;
+}
+
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::write_xtvt(unsigned addr, reg_t val) {
+    csr[addr]= val & ~0x3fULL;
    return iss::Ok;
 }

 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
-    if(mem_read_cb) return mem_read_cb(paddr, length, data);
    switch (paddr.val) {
    case 0x0200BFF8: { // CLINT base, mtime reg
        if (sizeof(reg_t) < length) return iss::Err;
@@ -1154,7 +1306,6 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned le

 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
-    if(mem_write_cb) return mem_write_cb(paddr, length, data);
    switch (paddr.val) {
    case 0x10013000: // UART0 base, TXFIFO reg
    case 0x10023000: // UART1 base, TXFIFO reg
@@ -1234,8 +1385,6 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned lengt
    if(addr==cfg.clic_base) { // cliccfg
        *data=clic_cfg_reg;
        for(auto i=1; i<length; ++i) *(data+i)=0;
-    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+8)){ // clicinfo
-        read_reg_uint32(addr, clic_info_reg, data, length);
    } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
        auto offset = ((addr&0x7fff)-0x40)/4;
        read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
@@ -1251,16 +1400,14 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned lengt
 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
    if(addr==cfg.clic_base) { // cliccfg
-        clic_cfg_reg = *data;
-        clic_cfg_reg&= 0x7e;
-//    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+4)){ // clicinfo
-//        write_uint32(addr, clic_info_reg, data, length);
+        clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e);
    } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
        auto offset = ((addr&0x7fff)-0x40)/4;
        write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
    } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
        auto offset = ((addr&0x7fff)-0x1000)/4;
        write_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
+        clic_int_reg[offset].raw &= 0xf0c70101; // clicIntCtlBits->0xf0, clicintattr->0xc7, clicintie->0x1, clicintip->0x1
    }
    return iss::Ok;
 }
@@ -1271,6 +1418,7 @@ template <typename BASE, features_e FEAT> inline void riscv_hart_mu_p<BASE, FEAT
 }

 template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::check_interrupt() {
+    //TODO: Implement CLIC functionality
    auto ideleg = csr[mideleg];
    // Multiple simultaneous interrupts and traps at the same privilege level are
    // handled in the following decreasing priority order:
@@ -1278,8 +1426,8 @@ template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::chec
    // any synchronous traps.
    auto ena_irq = csr[mip] & csr[mie];

-    bool mie = state.mstatus.MIE;
-    auto m_enabled = this->reg.PRIV < PRIV_M ||  mie;
+    bool mstatus_mie = state.mstatus.MIE;
+    auto m_enabled = this->reg.PRIV < PRIV_M || mstatus_mie;
    auto enabled_interrupts = m_enabled ? ena_irq & ~ideleg : 0;

    if (enabled_interrupts != 0) {
@@ -1318,7 +1466,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
            csr[utval | (new_priv << 8)] = static_cast<reg_t>(addr);
            break;
        case 2:
-            csr[utval | (new_priv << 8)] = (instr & 0x3)==3?instr:instr&0xffff;
+            csr[utval | (new_priv << 8)] = (!has_compressed() || (instr & 0x3)==3)?instr:instr&0xffff;
            break;
        case 3:
            if((FEAT & FEAT_DEBUG) && (csr[dcsr] & 0x8000)) {
@@ -1368,13 +1516,26 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
    }

    // get trap vector
-    auto ivec = csr[utvec | (new_priv << 8)];
+    auto xtvec = csr[utvec | (new_priv << 8)];
    // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
    // bits in mtvec
-    this->reg.NEXT_PC = ivec & ~0x3UL;
-    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
+    if((FEAT & features_e::FEAT_CLIC) && trap_id!=0 &&  (xtvec & 0x3UL)==3UL) {
+        reg_t data;
+        auto ret = read(address_type::LOGICAL, access_type::READ, 0, csr[mtvt], sizeof(reg_t), reinterpret_cast<uint8_t*>(&data));
+        if(ret == iss::Err)
+            return this->reg.PC;
+        this->reg.NEXT_PC = data;
+    } else {
+        this->reg.NEXT_PC = xtvec & ~0x3UL;
+        if ((xtvec & 0x1) == 1 && trap_id != 0)
+            this->reg.NEXT_PC += 4 * cause;
+    }
    std::array<char, 32> buffer;
+#if defined(_MSC_VER)
+    sprintf(buffer.data(), "0x%016llx", addr);
+#else
    sprintf(buffer.data(), "0x%016lx", addr);
+#endif
    if((flags&0xffffffff) != 0xffffffff)
    CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
                       << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
--- a/src/iss/arch/tgc_c.cpp
+++ b/src/iss/arch/tgc_c.cpp
@@ -30,9 +30,9 @@
 *
 *******************************************************************************/

+#include "tgc_c.h"
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/tgc_c.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
--- a/incl/iss/arch/tgc_c.h
+++ b/incl/iss/arch/tgc_c.h
@@ -53,7 +53,7 @@ template <> struct traits<tgc_c> {
    static constexpr std::array<const char*, 36> reg_aliases{
        {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};

-    enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, RFS=32, INSTR_ALIGNMENT=2, XLEN=32, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
+    enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};

    constexpr static unsigned FP_REGS_SIZE = 0;

@@ -81,7 +81,7 @@ template <> struct traits<tgc_c> {

    enum sreg_flag_e { FLAGS };

-    enum mem_type_e { MEM, CSR, FENCE, RES };
+    enum mem_type_e { MEM, FENCE, RES, CSR };
    
    enum class opcode_e : unsigned short {
        LUI = 0,
@@ -124,56 +124,53 @@ template <> struct traits<tgc_c> {
        FENCE = 37,
        ECALL = 38,
        EBREAK = 39,
-        URET = 40,
-        SRET = 41,
-        MRET = 42,
-        WFI = 43,
-        DRET = 44,
-        CSRRW = 45,
-        CSRRS = 46,
-        CSRRC = 47,
-        CSRRWI = 48,
-        CSRRSI = 49,
-        CSRRCI = 50,
-        FENCE_I = 51,
-        MUL = 52,
-        MULH = 53,
-        MULHSU = 54,
-        MULHU = 55,
-        DIV = 56,
-        DIVU = 57,
-        REM = 58,
-        REMU = 59,
-        CADDI4SPN = 60,
-        CLW = 61,
-        CSW = 62,
-        CADDI = 63,
-        CNOP = 64,
-        CJAL = 65,
-        CLI = 66,
-        CLUI = 67,
-        CADDI16SP = 68,
-        __reserved_clui = 69,
-        CSRLI = 70,
-        CSRAI = 71,
-        CANDI = 72,
-        CSUB = 73,
-        CXOR = 74,
-        COR = 75,
-        CAND = 76,
-        CJ = 77,
-        CBEQZ = 78,
-        CBNEZ = 79,
-        CSLLI = 80,
-        CLWSP = 81,
-        CMV = 82,
-        CJR = 83,
-        __reserved_cmv = 84,
-        CADD = 85,
-        CJALR = 86,
-        CEBREAK = 87,
-        CSWSP = 88,
-        DII = 89,
+        MRET = 40,
+        WFI = 41,
+        CSRRW = 42,
+        CSRRS = 43,
+        CSRRC = 44,
+        CSRRWI = 45,
+        CSRRSI = 46,
+        CSRRCI = 47,
+        FENCE_I = 48,
+        MUL = 49,
+        MULH = 50,
+        MULHSU = 51,
+        MULHU = 52,
+        DIV = 53,
+        DIVU = 54,
+        REM = 55,
+        REMU = 56,
+        CADDI4SPN = 57,
+        CLW = 58,
+        CSW = 59,
+        CADDI = 60,
+        CNOP = 61,
+        CJAL = 62,
+        CLI = 63,
+        CLUI = 64,
+        CADDI16SP = 65,
+        __reserved_clui = 66,
+        CSRLI = 67,
+        CSRAI = 68,
+        CANDI = 69,
+        CSUB = 70,
+        CXOR = 71,
+        COR = 72,
+        CAND = 73,
+        CJ = 74,
+        CBEQZ = 75,
+        CBNEZ = 76,
+        CSLLI = 77,
+        CLWSP = 78,
+        CMV = 79,
+        CJR = 80,
+        __reserved_cmv = 81,
+        CADD = 82,
+        CJALR = 83,
+        CEBREAK = 84,
+        CSWSP = 85,
+        DII = 86,
        MAX_OPCODE
    };
 };
--- a/src/iss/arch/tgc_c_decoder.cpp
+++ b/src/iss/arch/tgc_c_decoder.cpp
@@ -0,0 +1,175 @@
+#include "tgc_c.h"
+#include <vector>
+#include <array>
+#include <cstdlib>
+#include <algorithm>
+
+namespace iss {
+namespace arch {
+namespace {
+// according to
+// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
+#ifdef __GCC__
+constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
+#elif __cplusplus < 201402L
+constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
+constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
+#else
+constexpr size_t bit_count(uint32_t u) {
+    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
+    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
+}
+#endif
+
+using opcode_e = traits<tgc_c>::opcode_e;
+
+/****************************************************************************
+ * start opcode definitions
+ ****************************************************************************/
+struct instruction_desriptor {
+    size_t length;
+    uint32_t value;
+    uint32_t mask;
+    opcode_e op;
+};
+
+const std::array<instruction_desriptor, 90> instr_descr = {{
+     /* entries are: size, valid value, valid mask, function ptr */
+    {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, opcode_e::LUI},
+    {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, opcode_e::AUIPC},
+    {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, opcode_e::JAL},
+    {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, opcode_e::JALR},
+    {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, opcode_e::BEQ},
+    {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, opcode_e::BNE},
+    {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, opcode_e::BLT},
+    {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, opcode_e::BGE},
+    {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, opcode_e::BLTU},
+    {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, opcode_e::BGEU},
+    {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, opcode_e::LB},
+    {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, opcode_e::LH},
+    {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, opcode_e::LW},
+    {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, opcode_e::LBU},
+    {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, opcode_e::LHU},
+    {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, opcode_e::SB},
+    {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, opcode_e::SH},
+    {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, opcode_e::SW},
+    {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, opcode_e::ADDI},
+    {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, opcode_e::SLTI},
+    {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, opcode_e::SLTIU},
+    {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, opcode_e::XORI},
+    {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, opcode_e::ORI},
+    {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, opcode_e::ANDI},
+    {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, opcode_e::SLLI},
+    {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRLI},
+    {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRAI},
+    {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::ADD},
+    {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::SUB},
+    {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::SLL},
+    {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::SLT},
+    {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::SLTU},
+    {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::XOR},
+    {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRL},
+    {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRA},
+    {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::OR},
+    {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::AND},
+    {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE},
+    {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, opcode_e::ECALL},
+    {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, opcode_e::EBREAK},
+    {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::URET},
+    {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::SRET},
+    {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::MRET},
+    {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, opcode_e::WFI},
+    {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::DRET},
+    {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRW},
+    {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRS},
+    {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRC},
+    {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRWI},
+    {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRSI},
+    {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRCI},
+    {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE_I},
+    {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::MUL},
+    {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::MULH},
+    {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::MULHSU},
+    {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::MULHU},
+    {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::DIV},
+    {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::DIVU},
+    {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::REM},
+    {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::REMU},
+    {16, 0b0000000000000000, 0b1110000000000011, opcode_e::CADDI4SPN},
+    {16, 0b0100000000000000, 0b1110000000000011, opcode_e::CLW},
+    {16, 0b1100000000000000, 0b1110000000000011, opcode_e::CSW},
+    {16, 0b0000000000000001, 0b1110000000000011, opcode_e::CADDI},
+    {16, 0b0000000000000001, 0b1110111110000011, opcode_e::CNOP},
+    {16, 0b0010000000000001, 0b1110000000000011, opcode_e::CJAL},
+    {16, 0b0100000000000001, 0b1110000000000011, opcode_e::CLI},
+    {16, 0b0110000000000001, 0b1110000000000011, opcode_e::CLUI},
+    {16, 0b0110000100000001, 0b1110111110000011, opcode_e::CADDI16SP},
+    {16, 0b0110000000000001, 0b1111000001111111, opcode_e::__reserved_clui},
+    {16, 0b1000000000000001, 0b1111110000000011, opcode_e::CSRLI},
+    {16, 0b1000010000000001, 0b1111110000000011, opcode_e::CSRAI},
+    {16, 0b1000100000000001, 0b1110110000000011, opcode_e::CANDI},
+    {16, 0b1000110000000001, 0b1111110001100011, opcode_e::CSUB},
+    {16, 0b1000110000100001, 0b1111110001100011, opcode_e::CXOR},
+    {16, 0b1000110001000001, 0b1111110001100011, opcode_e::COR},
+    {16, 0b1000110001100001, 0b1111110001100011, opcode_e::CAND},
+    {16, 0b1010000000000001, 0b1110000000000011, opcode_e::CJ},
+    {16, 0b1100000000000001, 0b1110000000000011, opcode_e::CBEQZ},
+    {16, 0b1110000000000001, 0b1110000000000011, opcode_e::CBNEZ},
+    {16, 0b0000000000000010, 0b1111000000000011, opcode_e::CSLLI},
+    {16, 0b0100000000000010, 0b1110000000000011, opcode_e::CLWSP},
+    {16, 0b1000000000000010, 0b1111000000000011, opcode_e::CMV},
+    {16, 0b1000000000000010, 0b1111000001111111, opcode_e::CJR},
+    {16, 0b1000000000000010, 0b1111111111111111, opcode_e::__reserved_cmv},
+    {16, 0b1001000000000010, 0b1111000000000011, opcode_e::CADD},
+    {16, 0b1001000000000010, 0b1111000001111111, opcode_e::CJALR},
+    {16, 0b1001000000000010, 0b1111111111111111, opcode_e::CEBREAK},
+    {16, 0b1100000000000010, 0b1110000000000011, opcode_e::CSWSP},
+    {16, 0b0000000000000000, 0b1111111111111111, opcode_e::DII},
+}};
+
+}
+
+template<>
+struct instruction_decoder<tgc_c> {
+    using opcode_e = traits<tgc_c>::opcode_e;
+    using code_word_t=traits<tgc_c>::code_word_t;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
+
+    template<typename T>
+    unsigned decode_instruction(T);
+
+    instruction_decoder() {
+        for (auto instr : instr_descr) {
+            auto quadrant = instr.value & 0x3;
+            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+        }
+        for(auto& lut: qlut){
+            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+                return bit_count(a.mask) > bit_count(b.mask);
+            });
+        }
+    }
+};
+
+template<>
+unsigned instruction_decoder<tgc_c>::decode_instruction<traits<tgc_c>::code_word_t>(traits<tgc_c>::code_word_t instr){
+    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
+        return !((instr&e.mask) ^ e.value );
+    });
+    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
+}
+
+
+std::unique_ptr<instruction_decoder<tgc_c>> traits<tgc_c>::get_decoder(){
+    return std::make_unique<instruction_decoder<tgc_c>>();
+}
+
+}
+}
--- a/incl/iss/arch/tgc_mapper.h
+++ b/incl/iss/arch/tgc_mapper.h
@@ -4,39 +4,46 @@
 #include "riscv_hart_m_p.h"
 #include "tgc_c.h"
 using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
+#ifdef CORE_TGC_A
+#include "riscv_hart_m_p.h"
+#include <iss/arch/tgc_a.h>
+using tgc_a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_a>;
+#endif
 #ifdef CORE_TGC_B
 #include "riscv_hart_m_p.h"
-#include "tgc_b.h"
+#include <iss/arch/tgc_b.h>
 using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
 #endif
 #ifdef CORE_TGC_C_XRB_NN
 #include "riscv_hart_m_p.h"
-#include "tgc_c_xrb_nn.h"
-using tgc_c_xrb_nn_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>;
+#include "hwl.h"
+#include <iss/arch/tgc_c_xrb_nn.h>
+using tgc_c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>>;
 #endif
 #ifdef CORE_TGC_D
 #include "riscv_hart_mu_p.h"
-#include "tgc_d.h"
+#include <iss/arch/tgc_d.h>
 using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
 #ifdef CORE_TGC_D_XRB_MAC
 #include "riscv_hart_mu_p.h"
-#include "tgc_d_xrb_mac.h"
+#include <iss/arch/tgc_d_xrb_mac.h>
 using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
 #ifdef CORE_TGC_D_XRB_NN
 #include "riscv_hart_mu_p.h"
-#include "tgc_d_xrb_nn.h"
-using tgc_d_xrb_nn_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#include "hwl.h"
+#include <iss/arch/tgc_d_xrb_nn.h>
+using tgc_d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
 #endif
 #ifdef CORE_TGC_E
 #include "riscv_hart_mu_p.h"
-#include "tgc_e.h"
+#include <iss/arch/tgc_e.h>
 using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
 #ifdef CORE_TGC_X
 #include "riscv_hart_mu_p.h"
-#include "tgc_x.h"
+#include <iss/arch/tgc_x.h>
 using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
 #endif

--- a/src/iss/arch/wt_cache.h
+++ b/src/iss/arch/wt_cache.h
@@ -0,0 +1,172 @@
+/*******************************************************************************
+ * Copyright (C) 2023 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial implementation
+ ******************************************************************************/
+
+#ifndef _RISCV_HART_M_P_WT_CACHE_H
+#define _RISCV_HART_M_P_WT_CACHE_H
+
+#include <iss/vm_types.h>
+#include <util/ities.h>
+#include <vector>
+#include <map>
+#include <memory>
+
+namespace iss {
+namespace arch {
+namespace cache {
+
+enum class state { INVALID, VALID};
+struct line {
+    uint64_t tag_addr{0};
+    state st{state::INVALID};
+    std::vector<uint8_t> data;
+    line(unsigned line_sz):  data(line_sz) {}
+};
+struct set {
+    std::vector<line> ways;
+    set(unsigned ways_count, line const& l): ways(ways_count, l) {}
+};
+struct cache {
+    std::vector<set> sets;
+
+    cache(unsigned size, unsigned line_sz, unsigned ways) {
+        line const ref_line{line_sz};
+        set const ref_set{ways, ref_line};
+        sets.resize(size/(ways*line_sz), ref_set);
+    }
+};
+
+struct wt_policy {
+    bool is_cacheline_hit(cache& c );
+};
+}
+
+// write thru, allocate on read, direct mapped or set-associative with round-robin replacement policy
+template <typename BASE> class wt_cache : public BASE {
+public:
+    using base_class = BASE;
+    using this_class = wt_cache<BASE>;
+    using reg_t = typename BASE::reg_t;
+    using mem_read_f = typename BASE::mem_read_f;
+    using mem_write_f = typename BASE::mem_write_f;
+    using phys_addr_t = typename BASE::phys_addr_t;
+
+    wt_cache();
+    virtual ~wt_cache() = default;
+
+    unsigned size{4096};
+    unsigned line_sz{32};
+    unsigned ways{1};
+    uint64_t io_address{0xf0000000};
+    uint64_t io_addr_mask{0xf0000000};
+protected:
+    iss::status read_cache(phys_addr_t addr, unsigned, uint8_t *const);
+    iss::status write_cache(phys_addr_t addr, unsigned, uint8_t const *const);
+    std::function<mem_read_f> cache_mem_rd_delegate;
+    std::function<mem_write_f> cache_mem_wr_delegate;
+    std::unique_ptr<cache::cache> dcache_ptr;
+    std::unique_ptr<cache::cache> icache_ptr;
+    size_t get_way_select() {
+        return 0;
+    }
+};
+
+
+template<typename BASE>
+inline wt_cache<BASE>::wt_cache() {
+    auto cb = base_class::replace_mem_access(
+            [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l,d);},
+            [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l,d);});
+    cache_mem_rd_delegate = cb.first;
+    cache_mem_wr_delegate = cb.second;
+}
+
+template<typename BASE>
+iss::status iss::arch::wt_cache<BASE>::read_cache(phys_addr_t a, unsigned l, uint8_t* const d) {
+    if(!icache_ptr) {
+        icache_ptr.reset(new cache::cache(size, line_sz, ways));
+        dcache_ptr.reset(new cache::cache(size, line_sz, ways));
+    }
+    if((a.val&io_addr_mask) != io_address) {
+        auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways);
+        auto tag_addr=a.val>>util::ilog2(line_sz);
+        auto& set = (a.access==access_type::FETCH?icache_ptr:dcache_ptr)->sets[set_addr];
+        for(auto& cl: set.ways) {
+            if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
+                auto start_addr = a.val&(line_sz-1);
+                for(auto i = 0U; i<l; ++i)
+                    d[i] = cl.data[start_addr+i];
+                return iss::Ok;
+            }
+        }
+        auto& cl = set.ways[get_way_select()];
+        phys_addr_t cl_addr{a};
+        cl_addr.val=tag_addr<<util::ilog2(line_sz);
+        cache_mem_rd_delegate(cl_addr, line_sz, cl.data.data());
+        cl.tag_addr=tag_addr;
+        cl.st=cache::state::VALID;
+        auto start_addr = a.val&(line_sz-1);
+        for(auto i = 0U; i<l; ++i)
+            d[i] = cl.data[start_addr+i];
+        return iss::Ok;
+    } else
+        return cache_mem_rd_delegate(a, l, d);
+}
+
+template<typename BASE>
+iss::status iss::arch::wt_cache<BASE>::write_cache(phys_addr_t a, unsigned l, const uint8_t* const d) {
+    if(!dcache_ptr)
+        dcache_ptr.reset(new cache::cache(size, line_sz, ways));
+    auto res = cache_mem_wr_delegate(a, l, d);
+    if(res == iss::Ok && ((a.val&io_addr_mask) != io_address)) {
+        auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways);
+        auto tag_addr=a.val>>util::ilog2(line_sz);
+        auto& set = dcache_ptr->sets[set_addr];
+        for(auto& cl: set.ways) {
+            if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
+                auto start_addr = a.val&(line_sz-1);
+                for(auto i = 0U; i<l; ++i)
+                    cl.data[start_addr+1] = d[i];
+                break;
+            }
+        }
+    }
+    return res;
+}
+
+
+
+} // namespace arch
+} // namespace iss
+
+#endif /* _RISCV_HART_M_P_H */
--- a/incl/iss/debugger/riscv_target_adapter.h
+++ b/incl/iss/debugger/riscv_target_adapter.h
@@ -120,9 +120,9 @@ public:

    status packetsize_query(std::string &out_buf) override;

-    status add_break(int type, uint64_t addr, unsigned int length) override;
+    status add_break(break_type type, uint64_t addr, unsigned int length) override;

-    status remove_break(int type, uint64_t addr, unsigned int length) override;
+    status remove_break(break_type type, uint64_t addr, unsigned int length) override;

    status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
            std::function<void(unsigned)> stop_callback) override;
@@ -331,7 +331,12 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std
    return Ok;
 }

-template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
+        return Err;
+    case SW_EXEC:
+    case HW_EXEC: {
        auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
        auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
        target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
@@ -340,8 +345,15 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type,
        LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
        return Ok;
    }
+    }
+}

-template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
+        return Err;
+    case SW_EXEC:
+    case HW_EXEC: {
        auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
        unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
        if (handle) {
@@ -355,6 +367,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int typ
        LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
        return Err;
    }
+    }
+}

 template <typename ARCH>
 status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
--- a/incl/iss/factory.h
+++ b/incl/iss/factory.h
--- a/src/iss/plugin/cycle_estimate.cpp
+++ b/src/iss/plugin/cycle_estimate.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -32,14 +32,14 @@
 *       eyck@minres.com - initial API and implementation
 ******************************************************************************/

-#include "iss/plugin/cycle_estimate.h"
+#include "cycle_estimate.h"

 #include <iss/arch_if.h>
 #include <util/logging.h>
 #include <rapidjson/document.h>
 #include <rapidjson/istreamwrapper.h>
-#include "rapidjson/writer.h"
-#include "rapidjson/stringbuffer.h"
+#include <rapidjson/writer.h>
+#include <rapidjson/stringbuffer.h>
 #include <rapidjson/ostreamwrapper.h>
 #include <rapidjson/error/en.h>
 #include <fstream>
@@ -107,12 +107,12 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&

 }

-void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const& exc_info) {
+void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
    assert(instr_if && "No instrumentation interface available but callback executed");
    auto entry = delays[instr_info.instr_id];
-    bool taken = exc_info.branch_taken;
-    if (exc_info.branch_taken && (entry.taken > 1))
-        instr_if->set_curr_instr_cycles(entry.taken);
+    bool taken = instr_if->is_branch_taken();
+    if (taken && (entry.taken > 1))
+        instr_if->update_last_instr_cycles(entry.taken);
    else if (entry.not_taken > 1)
-        instr_if->set_curr_instr_cycles(entry.not_taken);
+        instr_if->update_last_instr_cycles(entry.not_taken);
 }
--- a/incl/iss/plugin/cycle_estimate.h
+++ b/incl/iss/plugin/cycle_estimate.h
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -45,7 +45,7 @@ namespace iss {

 namespace plugin {

-class cycle_estimate: public iss::vm_plugin {
+class cycle_estimate: public vm_plugin {
 	BEGIN_BF_DECL(instr_desc, uint32_t)
 		BF_FIELD(taken, 24, 8)
 		BF_FIELD(not_taken, 16, 8)
@@ -78,7 +78,7 @@ public:

    sync_type get_sync() override { return POST_SYNC; };

-    void callback(instr_info_t instr_info, exec_info const&) override;
+    void callback(instr_info_t instr_info) override;

 private:
    iss::instrumentation_if *instr_if;
--- a/src/iss/plugin/instruction_count.cpp
+++ b/src/iss/plugin/instruction_count.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -32,8 +32,8 @@
 *       eyck@minres.com - initial API and implementation
 ******************************************************************************/

-#include "iss/plugin/instruction_count.h"
-#include "iss/instrumentation_if.h"
+#include "instruction_count.h"
+#include <iss/instrumentation_if.h>

 #include <iss/arch_if.h>
 #include <util/logging.h>
@@ -90,6 +90,6 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
 	return true;
 }

-void iss::plugin::instruction_count::callback(instr_info_t instr_info, exec_info const&) {
+void iss::plugin::instruction_count::callback(instr_info_t instr_info) {
 	rep_counts[instr_info.instr_id]++;
 }
--- a/incl/iss/plugin/instruction_count.h
+++ b/incl/iss/plugin/instruction_count.h
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -69,7 +69,7 @@ public:

    sync_type get_sync() override { return POST_SYNC; };

-    void callback(instr_info_t, exec_info const&) override;
+    void callback(instr_info_t) override;

 private:
    Json::Value root;
--- a/src/iss/plugin/pctrace.cpp
+++ b/src/iss/plugin/pctrace.cpp
@@ -1,11 +1,45 @@
+/*******************************************************************************
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       alex.com - initial implementation
+ ******************************************************************************/
+
 #include <iss/arch_if.h>
 #include <iss/plugin/pctrace.h>
 #include <util/logging.h>
 #include <util/ities.h>
 #include <rapidjson/document.h>
 #include <rapidjson/istreamwrapper.h>
-#include "rapidjson/writer.h"
-#include "rapidjson/stringbuffer.h"
+#include <rapidjson/writer.h>
+#include <rapidjson/stringbuffer.h>
 #include <rapidjson/ostreamwrapper.h>
 #include <rapidjson/error/en.h>
 #include <fstream>
@@ -89,7 +123,7 @@ private:
 };
 #endif

-cov::cov(std::string const &filename)
+pctrace::pctrace(std::string const &filename)
 : instr_if(nullptr)
 , filename(filename)
 , output("output.trc")
@@ -99,9 +133,9 @@ cov::cov(std::string const &filename)
 #endif
 { }

-cov::~cov() { }
+pctrace::~pctrace() { }

-bool cov::registration(const char *const version, vm_if& vm) {
+bool pctrace::registration(const char *const version, vm_if& vm) {
    instr_if = vm.get_arch()->get_instrumentation_if();
    if(!instr_if) return false;
    const string  core_name = instr_if->core_type_name();
@@ -152,22 +186,22 @@ bool cov::registration(const char *const version, vm_if& vm) {
    return true;
 }

-void cov::callback(instr_info_t iinfo, const exec_info& einfo) {
+void pctrace::callback(instr_info_t iinfo) {
    auto delay = 0;
    size_t id = iinfo.instr_id;
    auto entry = delays[id];
    auto instr = instr_if->get_instr_word();
    auto call = id==65 || id ==86 || ((id==2 || id==3) && bit_sub<7,5>(instr)!=0) ;//not taking care of tail calls (jalr with loading x6)
-    bool taken = einfo.branch_taken;
+    bool taken = instr_if->is_branch_taken();
    bool compressed = (instr&0x3)!=0x3;
-    if (einfo.branch_taken) {
+    if (taken) {
        delay = entry.taken;
        if(entry.taken > 1)
-            instr_if->set_curr_instr_cycles(entry.taken);
+            instr_if->update_last_instr_cycles(entry.taken);
    } else {
        delay = entry.not_taken;
        if (entry.not_taken > 1)
-            instr_if->set_curr_instr_cycles(entry.not_taken);
+            instr_if->update_last_instr_cycles(entry.not_taken);
    }
 #ifndef WITH_LZ4
    output<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
--- a/incl/iss/plugin/pctrace.h
+++ b/incl/iss/plugin/pctrace.h
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -45,7 +45,7 @@
 namespace iss {
 namespace plugin {
 class lz4compress_steambuf;
-class cov : public iss::vm_plugin {
+class pctrace : public iss::vm_plugin {
    struct instr_delay {
        std::string instr_name;
        size_t size;
@@ -67,23 +67,23 @@ class cov : public iss::vm_plugin {

 public:

-    cov(const cov &) = delete;
+    pctrace(const pctrace &) = delete;

-    cov(const cov &&) = delete;
+    pctrace(const pctrace &&) = delete;

-    cov(std::string const &);
+    pctrace(std::string const &);

-    virtual ~cov();
+    virtual ~pctrace();

-    cov &operator=(const cov &) = delete;
+    pctrace &operator=(const pctrace &) = delete;

-    cov &operator=(const cov &&) = delete;
+    pctrace &operator=(const pctrace &&) = delete;

    bool registration(const char *const version, vm_if &arch) override;

    sync_type get_sync() override { return POST_SYNC; };

-    void callback(instr_info_t, exec_info const&) override;
+    void callback(instr_info_t) override;

 private:
    iss::instrumentation_if *instr_if  {nullptr};
--- a/src/main.cpp
+++ b/src/main.cpp
@@ -31,19 +31,21 @@
 *******************************************************************************/

 #include <iostream>
-#include <iss/factory.h>
+#include "iss/factory.h"

 #include <boost/lexical_cast.hpp>
 #include <boost/program_options.hpp>
-#include <iss/arch/tgc_mapper.h>
+#include "iss/arch/tgc_mapper.h"
 #ifdef WITH_LLVM
 #include <iss/llvm/jit_helper.h>
 #endif
 #include <iss/log_categories.h>
-#include <iss/plugin/cycle_estimate.h>
-#include <iss/plugin/instruction_count.h>
-#include <iss/plugin/pctrace.h>
+#include "iss/plugin/cycle_estimate.h"
+#include "iss/plugin/instruction_count.h"
+#include "iss/plugin/pctrace.h"
+#ifndef WIN32
 #include <iss/plugin/loader.h>
+#endif
 #if defined(HAS_LUA)
 #include <iss/plugin/lua.h>
 #endif
@@ -177,17 +179,20 @@ int main(int argc, char *argv[]) {
                    vm->register_plugin(*ce_plugin);
                    plugin_list.push_back(ce_plugin);
                } else if (plugin_name == "pctrace") {
-                    auto *plugin = new iss::plugin::cov(filename);
+                    auto *plugin = new iss::plugin::pctrace(filename);
                    vm->register_plugin(*plugin);
                    plugin_list.push_back(plugin);
               } else {
+#ifndef WIN32
                    std::array<char const*, 1> a{{filename.c_str()}};
                    iss::plugin::loader l(plugin_name, {{"initPlugin"}});
                    auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
                    if(plugin){
                        vm->register_plugin(*plugin);
                        plugin_list.push_back(plugin);
-                    } else {
+                    } else
+#endif
+                    {
                        LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
                        return 127;
                    }
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -37,8 +37,10 @@
 #include <iss/debugger/target_adapter_if.h>
 #include <iss/iss.h>
 #include <iss/vm_types.h>
+#ifndef WIN32
 #include <iss/plugin/loader.h>
-#include <sysc/core_complex.h>
+#endif
+#include "core_complex.h"
 #include <iss/arch/tgc_mapper.h>
 #include <scc/report.h>
 #include <util/ities.h>
@@ -184,17 +186,17 @@ public:
    void local_irq(short id, bool value) {
        reg_t mask = 0;
        switch (id) {
-        case 16: // SW
+        case 3: // SW
            mask = 1 << 3;
            break;
-        case 17: // timer
+        case 7: // timer
            mask = 1 << 7;
            break;
-        case 18: // external
+        case 11: // external
            mask = 1 << 11;
            break;
        default:
-            /* do nothing*/
+            if(id>15) mask = 1 << id;
            break;
        }
        if (value) {
@@ -355,8 +357,11 @@ void core_complex::init(){
    sensitive << sw_irq_i;
    SC_METHOD(timer_irq_cb);
    sensitive << timer_irq_i;
-    SC_METHOD(global_irq_cb);
-    sensitive << global_irq_i;
+    SC_METHOD(ext_irq_cb);
+    sensitive << ext_irq_i;
+    SC_METHOD(local_irq_cb);
+    for(auto pin:local_irq_i)
+        sensitive << pin;
    trc->m_db=scv_tr_db::get_default_db();

 	SC_METHOD(forward);
@@ -405,10 +410,11 @@ void core_complex::before_end_of_elaboration() {
                cpu->vm->register_plugin(*plugin);
                plugin_list.push_back(plugin);
            } else if (plugin_name == "pctrace") {
-                auto *plugin = new iss::plugin::cov(filename);
+                auto *plugin = new iss::plugin::pctrace(filename);
                cpu->vm->register_plugin(*plugin);
                plugin_list.push_back(plugin);
            } else {
+#ifndef WIN32
                std::array<char const*, 1> a{{filename.c_str()}};
                iss::plugin::loader l(plugin_name, {{"initPlugin"}});
                auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
@@ -416,6 +422,7 @@ void core_complex::before_end_of_elaboration() {
                    cpu->vm->register_plugin(*plugin);
                    plugin_list.push_back(plugin);
                } else
+#endif
                    SCCERR(SCMOD) << "Unknown plugin '" << plugin_name << "' or plugin not found";
            }
        }
@@ -424,7 +431,7 @@ void core_complex::before_end_of_elaboration() {
 }

 void core_complex::start_of_simulation() {
-    quantum_keeper.reset();
+    // quantum_keeper.reset();
    if (GET_PROP_VALUE(elf_file).size() > 0) {
        istringstream is(GET_PROP_VALUE(elf_file));
        string s;
@@ -476,15 +483,24 @@ void core_complex::rst_cb() {
    if (rst_i.read()) cpu->set_interrupt_execution(true);
 }

-void core_complex::sw_irq_cb() { cpu->local_irq(16, sw_irq_i.read()); }
+void core_complex::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }

-void core_complex::timer_irq_cb() { cpu->local_irq(17, timer_irq_i.read()); }
+void core_complex::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }

-void core_complex::global_irq_cb() { cpu->local_irq(18, global_irq_i.read()); }
+void core_complex::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
+
+void core_complex::local_irq_cb() {
+    for(auto i=0U; i<local_irq_i.size(); ++i) {
+        if(local_irq_i[i].event()) {
+            cpu->local_irq(16+i, local_irq_i[i].read());
+        }
+    }
+}

 void core_complex::run() {
    wait(SC_ZERO_TIME); // separate from elaboration phase
    do {
+        wait(SC_ZERO_TIME);
        if (rst_i.read()) {
            cpu->reset(GET_PROP_VALUE(reset_address));
            wait(rst_i.negedge_event());
@@ -492,6 +508,7 @@ void core_complex::run() {
        while (curr_clk.read() == SC_ZERO_TIME) {
            wait(curr_clk.value_changed_event());
        }
+        quantum_keeper.reset();
        cpu->set_interrupt_execution(false);
        cpu->start();
    } while (cpu->get_interrupt_execution());
@@ -500,8 +517,7 @@ void core_complex::run() {

 bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch) {
    auto lut_entry = read_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
+    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
        auto offset = addr - lut_entry.get_start_address();
        std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
        quantum_keeper.inc(lut_entry.get_read_latency());
@@ -522,7 +538,8 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
            gp.set_extension(preExt);
        }
        initiator->b_transport(gp, delay);
-        SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : " << data;
+        quantum_keeper.set(delay);
+        SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
        if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
            return false;
        }
@@ -534,9 +551,6 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
                if (dmi_data.is_read_allowed())
                    read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
                                      dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
-                if (dmi_data.is_write_allowed())
-                    write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
-                                       dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
            }
        }
        return true;
@@ -567,7 +581,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
        }
        initiator->b_transport(gp, delay);
        quantum_keeper.set(delay);
-        SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : " << data;
+        SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
        if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
            return false;
        }
@@ -576,9 +590,6 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
            gp.set_address(addr);
            tlm_dmi_ext dmi_data;
            if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
-                if (dmi_data.is_read_allowed())
-                    read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
-                                      dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
                if (dmi_data.is_write_allowed())
                    write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
                                       dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
@@ -589,14 +600,6 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
 }

 bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data) {
-    auto lut_entry = read_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
-        auto offset = addr - lut_entry.get_start_address();
-        std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
-        quantum_keeper.inc(lut_entry.get_read_latency());
-        return true;
-    } else {
    tlm::tlm_generic_payload gp;
    gp.set_command(tlm::TLM_READ_COMMAND);
    gp.set_address(addr);
@@ -605,17 +608,8 @@ bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const d
    gp.set_streaming_width(length);
    return initiator->transport_dbg(gp) == length;
 }
-}

 bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data) {
-    auto lut_entry = write_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
-        auto offset = addr - lut_entry.get_start_address();
-        std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
-        quantum_keeper.inc(lut_entry.get_read_latency());
-        return true;
-    } else {
    write_buf.resize(length);
    std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
    tlm::tlm_generic_payload gp;
@@ -626,6 +620,5 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *
    gp.set_streaming_width(length);
    return initiator->transport_dbg(gp) == length;
 }
-}
 } /* namespace SiFive */
 } /* namespace sysc */
--- a/incl/sysc/core_complex.h
+++ b/incl/sysc/core_complex.h
@@ -69,11 +69,11 @@ struct core_trace;

 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
-    tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<32>> initiator{"intor"};

    sc_core::sc_in<bool> rst_i{"rst_i"};

-    sc_core::sc_in<bool> global_irq_i{"global_irq_i"};
+    sc_core::sc_in<bool> ext_irq_i{"ext_irq_i"};

    sc_core::sc_in<bool> timer_irq_i{"timer_irq_i"};

@@ -84,7 +84,7 @@ public:
 #ifndef CWR_SYSTEMC
 	sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};

-    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
+    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o{"mtime_o"};

    cci::cci_param<std::string> elf_file{"elf_file", ""};

@@ -140,6 +140,7 @@ public:
    , gdb_server_port{"gdb_server_port", 0}
    , dump_ir{"dump_ir", false}
    , mhartid{"mhartid", 0}
+    , plugins{"plugins", ""}
    , read_lut(tlm_dmi_ext())
    , write_lut(tlm_dmi_ext())
    {
@@ -181,7 +182,8 @@ protected:
    void rst_cb();
    void sw_irq_cb();
    void timer_irq_cb();
-    void global_irq_cb();
+    void ext_irq_cb();
+    void local_irq_cb();
    uint64_t last_sync_cycle = 0;
    util::range_lut<tlm_dmi_ext> read_lut, write_lut;
    tlm_utils::tlm_quantumkeeper quantum_keeper;
--- a/src/vm/interp/.gitignore
+++ b/src/vm/interp/.gitignore
@@ -1 +0,0 @@
-/vm_tgc_*.cpp
--- a/src/vm/interp/vm_tgc_c.cpp
+++ b/src/vm/interp/vm_tgc_c.cpp
--- a/src/vm/llvm/vm_tgc_c.cpp
+++ b/src/vm/llvm/vm_tgc_c.cpp
@@ -30,7 +30,7 @@
 *
 *******************************************************************************/

-#include <iss/arch/tgf_c.h>
+#include <iss/arch/tgc_c.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
@@ -52,7 +52,7 @@ namespace fp_impl {
 void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
 }

-namespace tgf_c {
+namespace tgc_c {
 using namespace ::llvm;
 using namespace iss::arch;
 using namespace iss::debugger;
@@ -4151,11 +4151,11 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *b
                          bb, this->trap_blk, 1);
 }

-} // namespace tgf_c
+} // namespace tgc_c

 template <>
-std::unique_ptr<vm_if> create<arch::tgf_c>(arch::tgf_c *core, unsigned short port, bool dump) {
-    auto ret = new tgf_c::vm_impl<arch::tgf_c>(*core, dump);
+std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
+    auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
    return std::unique_ptr<vm_if>(ret);
 }
--- a/src/vm/llvm/vm_tgf_b.cpp
+++ b/src/vm/llvm/vm_tgf_b.cpp
--- a/src/vm/tcc/vm_tgc_c.cpp
+++ b/src/vm/tcc/vm_tgc_c.cpp
@@ -30,7 +30,7 @@
 *
 *******************************************************************************/

-#include <iss/arch/tgf_c.h>
+#include <iss/arch/tgc_c.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
@@ -49,7 +49,7 @@

 namespace iss {
 namespace tcc {
-namespace tgf_c {
+namespace tgc_c {
 using namespace iss::arch;
 using namespace iss::debugger;

@@ -3251,8 +3251,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
 } // namespace mnrv32

 template <>
-std::unique_ptr<vm_if> create<arch::tgf_c>(arch::tgf_c *core, unsigned short port, bool dump) {
-    auto ret = new tgf_c::vm_impl<arch::tgf_c>(*core, dump);
+std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
+    auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
    return std::unique_ptr<vm_if>(ret);
 }
--- a/src/vm/tcc/vm_tgf_b.cpp
+++ b/src/vm/tcc/vm_tgf_b.cpp
Author	SHA1	Message	Date
Eyck Jentzsch	aa70d8a54a	fixes CLIC to match clicinfo description in CLIC spec 11.04.2023	2023-05-02 17:22:13 +02:00
Eyck Jentzsch	b493745cd7	sets reset start time to 0	2023-05-02 11:21:42 +02:00
Eyck Jentzsch	f9e8e1d857	fixes core_complex wrt. tlm quantum and DMI	2023-05-02 11:13:25 +02:00
Eyck Jentzsch	974d64a627	adds logo to imported instance	2023-05-02 08:17:17 +02:00
Eyck Jentzsch	d70489cbb8	update import script to initialize broker	2023-05-02 07:58:48 +02:00
Eyck Jentzsch	d990f1cf5d	fixes reading of 64bit CSR register	2023-05-01 22:23:35 +02:00
Eyck Jentzsch	1672b01e62	adds WT cache functionality as mixin	2023-04-28 20:38:07 +02:00
Eyck Jentzsch	00b0f101ac	adapts to changes of instrumentation interface in dbt-rise-core	2023-04-28 20:38:07 +02:00
Rocco Jonack	54f75f92ea	improved testbench import; added prebuild FW for testing	2023-04-24 08:44:12 -07:00
Rocco Jonack	0304aac9e5	fixed some issues in import script; added README for reference; added initial testbench script(to be improved)	2023-04-19 05:20:58 -07:00
Eyck Jentzsch	8ff55d7b92	updates CWR dependent core_complex definition	2023-04-14 19:34:41 +02:00
Eyck Jentzsch	f626ee2684	fixes privilege wrapper for M/U to cope with 64bit	2023-04-05 15:38:25 +02:00
Eyck Jentzsch	a8a2782329	adds changes from latest CoreDSL description	2023-04-04 16:10:12 +02:00
Eyck Jentzsch	98dd329833	fixes CSR access rights	2023-04-04 09:23:08 +02:00
Eyck Jentzsch	6213445bc4	fixes 64bit behavior of CSR regs	2023-03-27 12:04:43 +02:00
Eyck Jentzsch	c5465bf9e2	fixes according to fixed generator	2023-03-26 14:44:15 +02:00
Eyck Jentzsch	d881cb6e63	fix data width of generated code	2023-03-26 12:12:34 +02:00
Eyck Jentzsch	2e4faa4d50	fixes mstatus mask	2023-03-25 09:14:56 +01:00
Eyck Jentzsch	8e1951f298	adds 64bit mstatus	2023-03-23 07:47:21 +01:00
Eyck Jentzsch	7efa924510	fixes m/uintstatus read	2023-03-17 10:51:39 +01:00
Eyck Jentzsch	febbc4fff0	fixes m/uintstatus read	2023-03-17 10:23:05 +01:00
Eyck Jentzsch	39b2788b7e	implements and fixes CLIC CSR behavior	2023-03-17 09:09:09 +01:00
Eyck Jentzsch	a943dd3bdf	fixes wrong array size which led to unintended CSR definitions	2023-03-15 14:16:08 +01:00
Eyck Jentzsch	fedbff5971	fixes xcause and u-mode clic CSRs	2023-03-15 12:27:39 +01:00
Eyck Jentzsch	c2758e8321	removes mscratchcsw from CLIC feature	2023-03-15 09:07:00 +01:00
Eyck Jentzsch	8be5fe71df	fixes template name typo	2023-03-12 07:42:09 +01:00
Eyck Jentzsch	3f7ce41b9d	fixes CLIC mtvt register behavior	2023-03-11 14:03:03 +01:00
Eyck Jentzsch	ad1cbedf00	adds back missing max irq functions	2023-03-11 12:47:10 +01:00
Eyck Jentzsch	83f54b5074	fixes CLICCFG settings	2023-03-11 08:48:03 +01:00
Eyck Jentzsch	a83928fd8c	fixes CSR/CLIC implementation	2023-03-10 20:40:21 +01:00
Eyck Jentzsch	ec55efd322	adds generator changed files	2023-02-17 06:36:34 +01:00
Eyck Jentzsch	8c3709f92a	adds generator changed files	2023-02-17 06:29:27 +01:00
Eyck Jentzsch	207dbf1071	fixes out of range access for register alias names	2023-02-17 06:28:30 +01:00
Eyck Jentzsch	62c118e501	fixes CSR to match latest fast interrupts spec	2023-01-20 16:21:04 +01:00
Eyck Jentzsch	65dca13b42	fixes WFI miss of interrupt	2023-01-14 17:40:21 +01:00
Eyck Jentzsch	3187cbdfe2	removes CONAN_PKG from build system	2022-12-12 02:55:44 +01:00
Eyck Jentzsch	8c701d55c1	adapt to latest changes in SCC	2022-12-05 09:15:48 +01:00
Eyck Jentzsch	f585489ff5	fixes pin naming	2022-10-26 17:21:44 +02:00
Eyck Jentzsch	7113683ee0	moves pending interrupt check before handling trap thus saving 1 cycle	2022-10-15 10:47:35 +02:00
Eyck Jentzsch	1a0fc4bd5d	fixes wrong mcounteren in M-mode only priv wrapper	2022-10-10 08:59:27 +02:00
Eyck Jentzsch	40d1966e9a	fixes pending irq within irq hander behavior	2022-10-08 11:20:52 +02:00
Eyck Jentzsch	a977200284	cleans up priv wrappers	2022-10-05 08:58:57 +02:00
Eyck Jentzsch	b20fd3eba5	fix static build	2022-09-28 19:37:47 +02:00
Eyck Jentzsch	b20daa1ac2	fixes wrong path in install	2022-09-27 09:11:41 +02:00
Eyck Jentzsch	b1a18459e7	adds more flexible use of availabel targets	2022-09-26 13:57:24 +02:00
Eyck Jentzsch	6ba7c82f80	fixes wrapper definitions for hwl cores	2022-09-26 13:31:46 +02:00
Eyck Jentzsch	ad7bb28b4c	fixes write mask of clic memory mapped registers	2022-09-17 12:15:19 +02:00
Eyck Jentzsch	fa7eda0889	fixes wrong check for exception	2022-08-31 11:45:53 +02:00
Eyck Jentzsch	00e02bf565	adds support for different branch types in tracing	2022-08-08 06:30:37 +02:00
Eyck Jentzsch	1ad66a71d8	extends supported break point types	2022-08-06 09:53:24 +02:00
Eyck Jentzsch	e60fa3d5e6	adaptes to changes in dbt-rise-core	2022-08-06 09:49:32 +02:00
Eyck Jentzsch	8407f6287f	replaces core_complex socket	2022-07-24 20:52:28 +02:00
Eyck Jentzsch	0833198d34	aads missing windows compat firx to template	2022-07-23 14:36:23 +02:00
Eyck Jentzsch	57347ae4d9	fixes cppcheck flagged issues	2022-07-23 13:49:10 +02:00
Eyck Jentzsch	4876f18ba9	adds windows compatibility fixes	2022-07-18 11:43:42 +02:00
Eyck Jentzsch	a53ee42e13	updates TGC_C according to CoreDSL description update	2022-07-12 22:34:22 +02:00
Eyck Jentzsch	12ccfc055a	updates generate tgc_c definition	2022-07-11 22:58:10 +02:00
Eyck Jentzsch	feaa49d367	removes decoder again as there is some issue	2022-06-20 00:39:11 +02:00
Eyck Jentzsch	18f33b4a68	fixes ordering of instructions for decoding	2022-06-19 16:52:29 +02:00
Eyck Jentzsch	f096b15dbd	factors decoder into separate component	2022-06-19 13:17:31 +02:00
Eyck Jentzsch	cb5375258a	removes compilatioon of unneeded files	2022-06-10 07:19:46 +02:00
Eyck Jentzsch	076b5a39ad	fix class naming	2022-06-02 08:30:49 +02:00
Eyck Jentzsch	f40ab41899	fix left-over from layout refactoring	2022-06-02 08:30:02 +02:00
Eyck Jentzsch	e8fd5143bc	fix build options for standalone ISS	2022-05-31 11:05:26 +02:00
Eyck Jentzsch	31fb51de95	update tgc_c generated code	2022-05-30 22:15:44 +02:00
Eyck Jentzsch	5d481eb79d	fix generation of non-exception code	2022-05-30 22:04:16 +02:00
Eyck Jentzsch	1c90fe765d	Merge remote-tracking branch 'origin/Trace_enhancement' into develop	2022-05-30 14:18:09 +02:00
Eyck Jentzsch	52ed8b81a6	fixed template to work with previous code generator	2022-05-30 14:08:02 +02:00
Eyck Jentzsch	0703a0a845	update tgc-mapper	2022-05-30 07:45:32 +02:00
Eyck Jentzsch	0c542d42aa	separate generated sources	2022-05-21 12:48:28 +02:00
Eyck Jentzsch	966d1616c5	change source code to unified layout	2022-05-21 11:55:24 +02:00