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fe2d5cb2f9
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adds semihosting to all backends
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2024-01-10 11:47:12 +01:00 |
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207f778ee6
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adds initial semihosting host capabilities
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2024-01-08 17:17:59 +01:00 |
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bc4ea30815
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apply clang-format 10 fixes
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2023-12-01 14:50:54 +01:00 |
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e921201f7b
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applies clang-format fixes
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2023-11-30 11:51:49 +01:00 |
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e6aa6e5842
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adds handling of variable number of clic interrupts
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2023-11-22 11:47:31 +01:00 |
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0eb1db0e7e
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adds functionality, adds working asmjit
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2023-11-20 11:45:52 +01:00 |
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e48597b2b7
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adds formatting fixes
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2023-11-05 17:19:43 +01:00 |
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759061b569
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applies clang-format changes
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2023-10-29 17:06:56 +01:00 |
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9180ad1f9c
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debugger memory accesses should never lead to traps
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2023-10-06 21:39:48 +02:00 |
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b7f023756e
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fixes constructor calls of derived riscv_hart classes
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2023-09-27 07:51:49 +02:00 |
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3fb8fe765a
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aligns riscv_hart_msu_vp with riscv_hart_m_p
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2023-09-26 20:17:26 +02:00 |
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8db0cc5d05
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removes clutter
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2023-09-23 10:34:58 +02:00 |
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212fb1c8ff
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adds tracing functionality
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2023-09-22 12:40:35 +02:00 |
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633c0d21a0
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Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop
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2023-09-20 15:17:43 +02:00 |
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51f6fbe0dd
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applies newest CoreDSL changes
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2023-09-20 15:12:03 +02:00 |
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de45d06878
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adds initial working version of llvm backend
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2023-09-19 16:26:07 +02:00 |
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b5d915f389
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fixes compile issues from merge
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2023-08-30 15:49:28 +02:00 |
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813b40409d
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Merge branch 'develop' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop
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2023-08-30 10:05:42 +02:00 |
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c8a4a4c736
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renames core(s)
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2023-08-28 07:09:55 +02:00 |
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20e920338c
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removes v2p function
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2023-08-04 13:08:10 +02:00 |
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0b719a4b57
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fixes literal type
|
2023-07-10 20:39:02 +02:00 |
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250ea3c980
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extends factory to support SystemC core wrapper
|
2023-07-09 18:19:59 +02:00 |
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7b31b8ca8e
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adds updated generated files
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2023-07-09 16:58:47 +02:00 |
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87b4082633
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Merge branch 'tmp' into develop
|
2023-07-03 14:22:50 +02:00 |
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4dbc7433a5
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fixes cause CSR handling
|
2023-06-12 17:38:56 +02:00 |
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99a9970ddd
|
fixes sysc compile issues
|
2023-06-12 09:58:24 +02:00 |
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0b5de90fb1
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changes [m|u]cause rd/wr handling
|
2023-06-11 18:29:58 +02:00 |
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2281ec4144
|
corrects errors and adds new backend and
|
2023-06-05 15:18:27 +02:00 |
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11c481cec2
|
adds verbosity to error
|
2023-06-05 15:17:16 +02:00 |
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a123beb301
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fixes duplicate variable declaration and templates
|
2023-05-27 10:20:49 +02:00 |
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ee6218279e
|
adapts to latest code gen changes
|
2023-05-25 12:52:30 +02:00 |
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6ed7eafc5d
|
adds inital version of tcc backend
|
2023-05-16 21:51:35 +02:00 |
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32848ec396
|
fixes build system and typo in wt_cache
|
2023-05-13 16:57:01 +02:00 |
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aa70d8a54a
|
fixes CLIC to match clicinfo description in CLIC spec 11.04.2023
|
2023-05-02 17:22:13 +02:00 |
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d990f1cf5d
|
fixes reading of 64bit CSR register
|
2023-05-01 22:23:35 +02:00 |
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1672b01e62
|
adds WT cache functionality as mixin
|
2023-04-28 20:38:07 +02:00 |
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00b0f101ac
|
adapts to changes of instrumentation interface in dbt-rise-core
|
2023-04-28 20:38:07 +02:00 |
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f626ee2684
|
fixes privilege wrapper for M/U to cope with 64bit
|
2023-04-05 15:38:25 +02:00 |
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98dd329833
|
fixes CSR access rights
|
2023-04-04 09:23:08 +02:00 |
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|
6213445bc4
|
fixes 64bit behavior of CSR regs
|
2023-03-27 12:04:43 +02:00 |
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|
|
2e4faa4d50
|
fixes mstatus mask
|
2023-03-25 09:14:56 +01:00 |
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|
8e1951f298
|
adds 64bit mstatus
|
2023-03-23 07:47:21 +01:00 |
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|
7efa924510
|
fixes m/uintstatus read
|
2023-03-17 10:51:39 +01:00 |
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|
|
febbc4fff0
|
fixes m/uintstatus read
|
2023-03-17 10:23:05 +01:00 |
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|
|
39b2788b7e
|
implements and fixes CLIC CSR behavior
|
2023-03-17 09:09:09 +01:00 |
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|
a943dd3bdf
|
fixes wrong array size which led to unintended CSR definitions
|
2023-03-15 14:16:08 +01:00 |
|
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|
fedbff5971
|
fixes xcause and u-mode clic CSRs
|
2023-03-15 12:27:39 +01:00 |
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|
c2758e8321
|
removes mscratchcsw from CLIC feature
|
2023-03-15 09:07:00 +01:00 |
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|
|
8be5fe71df
|
fixes template name typo
|
2023-03-12 07:42:09 +01:00 |
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|
3f7ce41b9d
|
fixes CLIC mtvt register behavior
|
2023-03-11 14:03:03 +01:00 |
|
