 Eyck Jentzsch
|
0a76ccbdac
|
make RSP register response independend of register definition
|
2021-03-31 07:48:46 +00:00 |
|
Eyck Jentzsch
|
32e4aa83b8
|
use extracted variables
|
2021-03-27 09:36:52 +00:00 |
|
Eyck Jentzsch
|
78c7064295
|
update groovy template to extract used registers
|
2021-03-26 08:24:45 +00:00 |
|
Eyck Jentzsch
|
412a4bd9bb
|
update name
|
2021-03-23 17:13:32 +00:00 |
 Stanislaw Kaushanski
|
ea3ff3c0cd
|
build with SCV lib
|
2021-03-23 11:57:47 +01:00 |
|
Eyck Jentzsch
|
b0bcb7febb
|
small fixes for robustness and readability
|
2021-03-22 22:47:30 +00:00 |
|
Stanislaw Kaushanski
|
c941890901
|
SCC refactoring
|
2021-03-22 14:50:53 +01:00 |
|
Eyck Jentzsch
|
51fbc34fb3
|
change namespace of core complex
|
2021-03-22 11:57:40 +00:00 |
|
Eyck Jentzsch
|
4e0f20eba0
|
rework abort conditions
|
2021-03-17 19:32:57 +00:00 |
|
Eyck Jentzsch
|
ff3fa19208
|
fix RVM description bugs
|
2021-03-13 10:46:41 +00:00 |
|
Eyck Jentzsch
|
80057eef32
|
fix RVC description bugs, remove paged fetch
|
2021-03-13 10:46:41 +00:00 |
|
Stanislaw Kaushanski
|
a5186ff88d
|
optional dependency to TGF_B_src target
|
2021-03-12 11:16:24 +01:00 |
|
Eyck Jentzsch
|
f4ec21007b
|
fix signedness issues
|
2021-03-11 16:12:28 +00:00 |
|
Eyck Jentzsch
|
ac8eab6e25
|
update RISC-V desciptions
|
2021-03-10 17:31:10 +00:00 |
|
Stanislaw Kaushanski
|
b7c0fb2b1c
|
fix bitfield structure
|
2021-03-10 12:40:06 +01:00 |
|
Eyck Jentzsch
|
768716b064
|
fix another missing XLEN
|
2021-03-09 11:07:56 +00:00 |
|
Eyck Jentzsch
|
bea0dcc387
|
update missing XLEN
|
2021-03-09 11:03:37 +00:00 |
|
Eyck Jentzsch
|
a6691bcd3c
|
update generated code with correct sign extension
|
2021-03-09 10:21:36 +00:00 |
|
Eyck Jentzsch
|
40db74ce02
|
remove tgf_b code generation
|
2021-03-07 16:26:14 +00:00 |
|
Eyck Jentzsch
|
c171e3c1ba
|
update CoreDSL descriptions
|
2021-03-07 10:51:15 +00:00 |
|
Eyck Jentzsch
|
c251fe15d5
|
fix desscriptions to conform to ISA spec version 20191213 and TGF-C
|
2021-03-07 10:51:00 +00:00 |
|
Eyck Jentzsch
|
dae8acb8a3
|
checkpoint before refactor
|
2021-03-06 07:17:42 +00:00 |
|
Eyck Jentzsch
|
f7cec99fa6
|
adapt to changes in SCC
|
2021-03-01 21:08:18 +00:00 |
|
Eyck Jentzsch
|
be0e7db185
|
fix templates to comply with CoreDSL2
|
2021-03-01 21:07:20 +00:00 |
|
Eyck Jentzsch
|
4aa26b85a0
|
adapt to change in SCC
|
2021-03-01 06:36:27 +00:00 |
|
Eyck Jentzsch
|
9534d58d01
|
regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
|
2021-03-01 06:26:33 +00:00 |
|
Eyck Jentzsch
|
1668df0531
|
regenerated sources and and add opcode enum to headers
|
2021-02-23 08:29:31 +00:00 |
|
Eyck Jentzsch
|
d8e009c72b
|
update CoreDSL decriptions
|
2021-02-15 18:15:13 +00:00 |
|
Eyck Jentzsch
|
d07c8679ed
|
update core definition
|
2021-02-15 18:14:52 +00:00 |
|
Eyck Jentzsch
|
3d5b61f301
|
move boost libraries from tgfs_sc to tgfs library
|
2021-02-15 18:03:39 +00:00 |
|
Eyck Jentzsch
|
337f1634c0
|
add mssing change
|
2021-02-15 18:01:46 +00:00 |
|
Eyck Jentzsch
|
72b09472d5
|
update RISC-V descriptions
|
2021-02-15 18:01:33 +00:00 |
|
Eyck Jentzsch
|
3261055871
|
update description to latest CoreDSL2
|
2021-02-15 11:35:56 +00:00 |
|
Eyck Jentzsch
|
34bb8e62ae
|
generate working ISS from CoreDSL 2.0
|
2021-02-06 14:47:06 +00:00 |
|
Eyck Jentzsch
|
da7e29fbb7
|
update definitions of derived constants
|
2021-01-01 09:19:48 +00:00 |
|
Eyck Jentzsch
|
c4da47cedd
|
integrate code generation into build process (first attempt)
|
2020-12-30 07:29:52 +00:00 |
|
Eyck Jentzsch
|
ab554539e3
|
first version of tgf_c based on CoreDSL 2.0
|
2020-12-29 08:48:22 +00:00 |
|
Eyck Jentzsch
|
d43b35949e
|
fix CMakeList.txt so that it builds without platform and external libs
|
2020-12-23 16:24:10 +00:00 |
|
Stanislaw Kaushanski
|
be49b8b545
|
Relative path to a submodule
|
2020-12-10 15:32:03 +01:00 |
|
Stanislaw Kaushanski
|
43488676dd
|
Update TGF naming convention
|
2020-09-11 10:45:44 +02:00 |
|
Stanislaw Kaushanski
|
f3d578f050
|
Remove 64bit support
|
2020-09-07 14:30:19 +02:00 |
|
Stanislaw Kaushanski
|
293c396a0d
|
update core wrapper: remove virtual memory support
|
2020-09-07 13:29:45 +02:00 |
|
Stanislaw Kaushanski
|
6f3963a473
|
Strip down privileged modes. Only machine mode is supported
|
2020-09-07 11:54:45 +02:00 |
|
Stanislaw Kaushanski
|
969b408288
|
Implement MHARTID register
|
2020-09-04 15:37:21 +02:00 |
|
Stanislaw Kaushanski
|
886b8f5716
|
TGF02 is a default core
|
2020-08-31 14:20:13 +02:00 |
|
Stanislaw Kaushanski
|
c2c8fb5ca9
|
update README
|
2020-08-24 15:14:49 +02:00 |
|
Stanislaw Kaushanski
|
9754e3953f
|
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
|
2020-08-24 15:01:54 +02:00 |
|
Stanislaw Kaushanski
|
03172e352d
|
move CoreDSL instraction set description files into a dedicated repository CoreDSL-Instruction-Set-Description
|
2020-08-21 15:57:01 +02:00 |
|
Stanislaw Kaushanski
|
8fce0c4759
|
Generate TGF01 and TGF02 cores
|
2020-08-20 17:29:36 +02:00 |
|
Eyck Jentzsch
|
18976e2ce4
|
adapt to newer gdb protocol
|
2020-06-22 08:45:12 +02:00 |