DBT-RISE
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DBT-RISE-TGC
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275 Commits

Author SHA1 Message Date
Eyck-Alexander Jentzsch de45d06878 adds initial working version of llvm backend 2023-09-19 16:26:07 +02:00
Eyck-Alexander Jentzsch b360fc2c75 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2023-09-05 10:08:49 +02:00
Eyck-Alexander Jentzsch e21f8dc379 allows functions in interp and updates generated 2023-09-05 10:08:00 +02:00
Eyck Jentzsch 8ee3ac90f7 adapts name changes 2023-09-04 12:45:45 +02:00
Eyck Jentzsch b5d915f389 fixes compile issues from merge 2023-08-30 15:49:28 +02:00
Eyck Jentzsch 813b40409d Merge branch 'develop' of 
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop
 2023-08-30 10:05:42 +02:00
Eyck Jentzsch c8a4a4c736 renames core(s) 2023-08-28 07:09:55 +02:00
Eyck Jentzsch 20e920338c removes v2p function 2023-08-04 13:08:10 +02:00
Eyck Jentzsch e151416f58 fixes systemc factory registration 2023-07-31 12:55:09 +02:00
Eyck Jentzsch 24de2bbdf5 purge build system 2023-07-30 13:55:57 +02:00
Eyck Jentzsch e68f9c573f Merge branch 'develop' of 
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop
 2023-07-30 09:14:58 +02:00
Eyck Jentzsch f38cc7d8b9 updates LLVM build 2023-07-29 17:55:37 +02:00
Eyck-Alexander Jentzsch 7af7e040da Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2023-07-29 11:47:25 +02:00
Eyck-Alexander Jentzsch 6e52af168b adds faster decoding to tcc and cleans up others 2023-07-29 11:42:46 +02:00
Eyck-Alexander Jentzsch bd0d15f3a2 updates template for faster instruction decoding 2023-07-23 08:10:57 +02:00
Eyck-Alexander Jentzsch c78026b720 adds faster instruction decoding 2023-07-23 08:05:15 +02:00
Eyck Jentzsch a0ca3cdfa5 revive LLVM support (WIP) 2023-07-14 12:55:34 +02:00
Eyck Jentzsch 720236ec3f add generated core registration 2023-07-14 12:51:51 +02:00
Eyck Jentzsch 957145ca84 add SystemC ISS factory 2023-07-14 11:11:03 +02:00
Eyck Jentzsch 0b719a4b57 fixes literal type 2023-07-10 20:39:02 +02:00
Eyck Jentzsch b4b03f7850 fixes build system to handle TCC properly 2023-07-09 22:20:50 +02:00
Eyck Jentzsch 145a0cf68b updates registration of cores for sysc 2023-07-09 20:24:45 +02:00
Eyck Jentzsch 1cef7de8c7 fixes missing namespaces 2023-07-09 20:16:16 +02:00
Eyck Jentzsch e95f422aab cleans vm implementation up 2023-07-09 20:13:26 +02:00
Eyck Jentzsch 250ea3c980 extends factory to support SystemC core wrapper 2023-07-09 18:19:59 +02:00
Eyck-Alexander Jentzsch 7b31b8ca8e adds updated generated files 2023-07-09 16:58:47 +02:00
Eyck-Alexander Jentzsch 91a23a4a18 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2023-07-09 16:55:06 +02:00
Eyck Jentzsch a32c83e1be fixes CLI handling of plugin paramters in ISS 2023-07-05 08:32:05 +02:00
Eyck-Alexander Jentzsch 87b4082633 Merge branch 'tmp' into develop 2023-07-03 14:22:50 +02:00
Eyck Jentzsch 4dbc7433a5 fixes cause CSR handling 2023-06-12 17:38:56 +02:00
Eyck Jentzsch 99a9970ddd fixes sysc compile issues 2023-06-12 09:58:24 +02:00
Eyck Jentzsch 0b5de90fb1 changes [m|u]cause rd/wr handling 2023-06-11 18:29:58 +02:00
Eyck-Alexander Jentzsch 15cd36dcd4 adds fix for compressed instructions and reads 2023-06-05 17:57:38 +02:00
Eyck-Alexander Jentzsch 2281ec4144 corrects errors and adds new backend and 2023-06-05 15:18:27 +02:00
Eyck-Alexander Jentzsch 11c481cec2 adds verbosity to error 2023-06-05 15:17:16 +02:00
Eyck Jentzsch 60d07f2eb6 changes default loglevel to info for tgc-sim 2023-06-01 06:55:21 +02:00
Eyck Jentzsch a123beb301 fixes duplicate variable declaration and templates 2023-05-27 10:20:49 +02:00
Eyck Jentzsch ee6218279e adapts to latest code gen changes 2023-05-25 12:52:30 +02:00
Eyck-Alexander Jentzsch 6ed7eafc5d adds inital version of tcc backend 2023-05-16 21:51:35 +02:00
Eyck Jentzsch 32848ec396 fixes build system and typo in wt_cache 2023-05-13 16:57:01 +02:00
Eyck Jentzsch 6789cf4c32 fixes case of unavailable backend 2023-05-12 15:45:53 +02:00
Eyck Jentzsch afdf8fb97f adds missing namespaces 2023-05-11 23:11:04 +02:00
Eyck Jentzsch cfa7b72363 changes time handling at sockets 2023-05-06 19:57:29 +02:00
Eyck Jentzsch d330307ed5 splits bus into 2 sockets for i/dbus 2023-05-04 21:59:31 +02:00
Eyck Jentzsch aa70d8a54a fixes CLIC to match clicinfo description in CLIC spec 11.04.2023 2023-05-02 17:22:13 +02:00
Eyck Jentzsch b493745cd7 sets reset start time to 0 2023-05-02 11:21:42 +02:00
Eyck Jentzsch f9e8e1d857 fixes core_complex wrt. tlm quantum and DMI 2023-05-02 11:13:25 +02:00
Eyck Jentzsch d990f1cf5d fixes reading of 64bit CSR register 2023-05-01 22:23:35 +02:00
Eyck Jentzsch 1672b01e62 adds WT cache functionality as mixin 2023-04-28 20:38:07 +02:00
Eyck Jentzsch 00b0f101ac adapts to changes of instrumentation interface in dbt-rise-core 2023-04-28 20:38:07 +02:00
Eyck Jentzsch 8ff55d7b92 updates CWR dependent core_complex definition 2023-04-14 19:34:41 +02:00
Eyck Jentzsch f626ee2684 fixes privilege wrapper for M/U to cope with 64bit 2023-04-05 15:38:25 +02:00
Eyck Jentzsch a8a2782329 adds changes from latest CoreDSL description 2023-04-04 16:10:12 +02:00
Eyck Jentzsch 98dd329833 fixes CSR access rights 2023-04-04 09:23:08 +02:00
Eyck Jentzsch 6213445bc4 fixes 64bit behavior of CSR regs 2023-03-27 12:04:43 +02:00
Eyck Jentzsch c5465bf9e2 fixes according to fixed generator 2023-03-26 14:44:15 +02:00
Eyck Jentzsch 2e4faa4d50 fixes mstatus mask 2023-03-25 09:14:56 +01:00
Eyck Jentzsch 8e1951f298 adds 64bit mstatus 2023-03-23 07:47:21 +01:00
Eyck Jentzsch 7efa924510 fixes m/uintstatus read 2023-03-17 10:51:39 +01:00
Eyck Jentzsch febbc4fff0 fixes m/uintstatus read 2023-03-17 10:23:05 +01:00
Eyck Jentzsch 39b2788b7e implements and fixes CLIC CSR behavior 2023-03-17 09:09:09 +01:00
Eyck Jentzsch a943dd3bdf fixes wrong array size which led to unintended CSR definitions 2023-03-15 14:16:08 +01:00
Eyck Jentzsch fedbff5971 fixes xcause and u-mode clic CSRs 2023-03-15 12:27:39 +01:00
Eyck Jentzsch c2758e8321 removes mscratchcsw from CLIC feature 2023-03-15 09:07:00 +01:00
Eyck Jentzsch 8be5fe71df fixes template name typo 2023-03-12 07:42:09 +01:00
Eyck Jentzsch 3f7ce41b9d fixes CLIC mtvt register behavior 2023-03-11 14:03:03 +01:00
Eyck Jentzsch ad1cbedf00 adds back missing max irq functions 2023-03-11 12:47:10 +01:00
Eyck Jentzsch 83f54b5074 fixes CLICCFG settings 2023-03-11 08:48:03 +01:00
Eyck Jentzsch a83928fd8c fixes CSR/CLIC implementation 2023-03-10 20:40:21 +01:00
Eyck Jentzsch ec55efd322 adds generator changed files 2023-02-17 06:36:34 +01:00
Eyck Jentzsch 8c3709f92a adds generator changed files 2023-02-17 06:29:27 +01:00
Eyck Jentzsch 62c118e501 fixes CSR to match latest fast interrupts spec 2023-01-20 16:21:04 +01:00
Eyck Jentzsch 65dca13b42 fixes WFI miss of interrupt 2023-01-14 17:40:21 +01:00
Eyck Jentzsch 8c701d55c1 adapt to latest changes in SCC 2022-12-05 09:15:48 +01:00
Eyck Jentzsch f585489ff5 fixes pin naming 2022-10-26 17:21:44 +02:00
Eyck Jentzsch 7113683ee0 moves pending interrupt check before handling trap thus saving 1 cycle 2022-10-15 10:47:35 +02:00
Eyck Jentzsch 1a0fc4bd5d fixes wrong mcounteren in M-mode only priv wrapper 2022-10-10 08:59:27 +02:00
Eyck Jentzsch 40d1966e9a fixes pending irq within irq hander behavior 2022-10-08 11:20:52 +02:00
Eyck Jentzsch a977200284 cleans up priv wrappers 2022-10-05 08:58:57 +02:00
Eyck Jentzsch 6ba7c82f80 fixes wrapper definitions for hwl cores 2022-09-26 13:31:46 +02:00
Eyck Jentzsch ad7bb28b4c fixes write mask of clic memory mapped registers 2022-09-17 12:15:19 +02:00
Eyck Jentzsch fa7eda0889 fixes wrong check for exception 2022-08-31 11:45:53 +02:00
Eyck Jentzsch 00e02bf565 adds support for different branch types in tracing 2022-08-08 06:30:37 +02:00
Eyck Jentzsch 1ad66a71d8 extends supported break point types 2022-08-06 09:53:24 +02:00
Eyck Jentzsch e60fa3d5e6 adaptes to changes in dbt-rise-core 2022-08-06 09:49:32 +02:00
Eyck Jentzsch 8407f6287f replaces core_complex socket 2022-07-24 20:52:28 +02:00
Eyck Jentzsch 57347ae4d9 fixes cppcheck flagged issues 2022-07-23 13:49:10 +02:00
Eyck Jentzsch 4876f18ba9 adds windows compatibility fixes 2022-07-18 11:43:42 +02:00
Eyck Jentzsch a53ee42e13 updates TGC_C according to CoreDSL description update 2022-07-12 22:34:22 +02:00
Eyck Jentzsch 12ccfc055a updates generate tgc_c definition 2022-07-11 22:58:10 +02:00
Eyck Jentzsch feaa49d367 removes decoder again as there is some issue 2022-06-20 00:39:11 +02:00
Eyck Jentzsch f096b15dbd factors decoder into separate component 2022-06-19 13:17:31 +02:00
Eyck Jentzsch 076b5a39ad fix class naming 2022-06-02 08:30:49 +02:00
Eyck Jentzsch f40ab41899 fix left-over from layout refactoring 2022-06-02 08:30:02 +02:00
Eyck Jentzsch 31fb51de95 update tgc_c generated code 2022-05-30 22:15:44 +02:00
Eyck Jentzsch 1c90fe765d Merge remote-tracking branch 'origin/Trace_enhancement' into develop 2022-05-30 14:18:09 +02:00
Eyck Jentzsch 52ed8b81a6 fixed template to work with previous code generator 2022-05-30 14:08:02 +02:00
Eyck Jentzsch 0703a0a845 update tgc-mapper 2022-05-30 07:45:32 +02:00
Eyck Jentzsch 0c542d42aa separate generated sources 2022-05-21 12:48:28 +02:00
Eyck Jentzsch 966d1616c5 change source code to unified layout 2022-05-21 11:55:24 +02:00