Commit Graph

322 Commits

Author SHA1 Message Date
Eyck Jentzsch 9db4e3fd87 fix assertion 2022-05-10 16:13:21 +02:00
Eyck-Alexander Jentzsch bb658be3b4 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2022-05-08 15:25:56 +02:00
Eyck-Alexander Jentzsch 6579780dc9 add call column in output 2022-05-08 15:24:26 +02:00
Eyck Jentzsch e56bc12788 fix non-lz4 build of plugin 2022-05-07 17:27:11 +02:00
Eyck Jentzsch e88f309ea2 add lz4 compression to pctrace 2022-05-07 17:22:06 +02:00
Eyck Jentzsch 03bec27376 implement extended instrumentation interface 2022-04-26 17:14:33 +02:00
Eyck Jentzsch 9d9008a3a2 fix pointer mess 2022-04-26 15:35:17 +02:00
Stanislaw Kaushanski 5f6d462973 check that no interrupts are pending before entering the wfi wait 2022-04-26 13:58:20 +02:00
Eyck Jentzsch a92b84bef4 add code word access for ISS plugins 2022-04-25 14:18:19 +02:00
Eyck Jentzsch 477c530847 extend debug mode handling 2022-04-13 11:41:01 +02:00
Eyck Jentzsch c054d75717 update to latest coredsl description 2022-04-10 18:55:44 +02:00
Eyck Jentzsch 15cd26f800 remove CoreDSL ISA repo 2022-04-10 12:15:40 +02:00
Eyck Jentzsch 9465cffe79 adapt to change in dbt-rise-core 2022-04-09 14:55:36 +02:00
Eyck Jentzsch 00d2d06cbd adapt to privileged spec 2022-03-31 20:33:12 +02:00
Eyck Jentzsch 8e4e702cb9 Merge remote-tracking branch 'origin/feature/reduced_output' into develop 2022-03-28 14:09:06 +02:00
Eyck-Alexander Jentzsch 58311b37db Merge branch 'feature/reduced_output' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into
feature/reduced_output
2022-03-28 11:16:09 +02:00
Eyck-Alexander Jentzsch ad8dc09bee Merge branch 'feature/reduced_output' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into feature/reduced_output 2022-03-28 11:15:45 +02:00
Eyck Jentzsch 49be143588 make features configurable 2022-03-27 17:54:08 +02:00
Eyck Jentzsch 0aea1d0177 remove mcounteren in M-mode only wrapper 2022-03-27 17:21:46 +02:00
Eyck Jentzsch 6ea7721961 add TCM 2022-03-27 15:38:18 +02:00
Eyck Jentzsch b0cb997009 add TGC_X with DMR 2022-03-26 10:48:21 +01:00
Eyck Jentzsch 9dfca612b7 add hardware loop CSR access 2022-03-25 11:33:44 +01:00
Eyck Jentzsch 30ae743361 add pctrace plugin to iss 2022-03-20 17:41:54 +01:00
Eyck Jentzsch d91f5f9df4 fix compiler warning for reduced number of registers 2022-03-14 15:38:05 +01:00
Stanislaw Kaushanski 5ec457c76b build pctrace plugin only if RapidJSON target is availble 2022-03-08 11:23:07 +01:00
Eyck Jentzsch 2e670c4d03 change interpreter structure 2022-03-06 15:11:38 +01:00
Eyck Jentzsch 3d32c33333 update gitignore 2022-03-05 20:59:45 +01:00
Eyck Jentzsch 521f40a3d6 refactored interpreter backend structure 2022-03-05 20:59:17 +01:00
Eyck-Alexander Jentzsch 2bba5645c3 adds functionality to reduce the output 2022-02-16 10:13:29 +01:00
Eyck-Alexander Jentzsch bf0a5a80de adds functionality to reduce the output 2022-02-16 10:12:45 +01:00
Eyck Jentzsch b37ef973de clean up 2022-02-14 20:36:12 +01:00
Eyck-Alexander Jentzsch 4c363f4073 adds additional functionality by fetching delay information 2022-02-11 11:28:00 +01:00
Eyck Jentzsch b8fa5fbbda adapt to extended instrumentation interface 2022-02-09 21:01:17 +01:00
Eyck Jentzsch ac86f14a54 add tgc_c_xrb_nn to tgc-sim 2022-02-02 21:33:42 +01:00
Eyck Jentzsch 68b5697c8f Fix cycles JSON template 2022-02-01 21:48:56 +01:00
Eyck Jentzsch 09b0f0d0c8 fix cycle estimation plugin 2022-02-01 21:14:50 +01:00
Eyck Jentzsch 98b418ff43 fix JSON reading 2022-02-01 19:28:11 +01:00
Eyck Jentzsch 059bd0d371 rework cycle estimation 2022-02-01 19:03:45 +01:00
Eyck Jentzsch ef2a4df925 simplify spawn block handling 2022-01-31 23:40:31 +01:00
Eyck-Alexander Jentzsch 7578906310 adds coverage plugin 2022-01-31 21:38:18 +01:00
Eyck Jentzsch afe8905ac9 fix else-ambiguity in CoreDSL description 2022-01-31 20:30:46 +01:00
Eyck-Alexander Jentzsch ecc6091d1e cleans up source code to remove clang compiler warnings 2022-01-19 08:01:15 +01:00
Eyck Jentzsch 3563ba80d0 add spawn blocks 2022-01-12 07:21:16 +01:00
Eyck Jentzsch 09955be90f update gitignore 2021-12-05 08:45:49 +01:00
Eyck Jentzsch dd4c19a15c add option to configure number of irq 2021-12-01 12:56:36 +01:00
Eyck Jentzsch 07d5af1dde fix stand-alone ISS compilation to include all generated cores 2021-11-26 17:56:40 +01:00
Eyck Jentzsch 6f8595759e make tgc-sim include all available ISS 2021-11-25 20:00:27 +01:00
Maribel Gomez 86da31033c correct size usage in pmp addr checks 2021-11-22 15:15:47 +01:00
Maribel Gomez 974d103381 fix pmpcfg register write 2021-11-22 10:49:29 +01:00
Eyck Jentzsch 309758b994 fix clic_cfg access scheme 2021-11-17 07:59:02 +01:00