 Eyck-Alexander Jentzsch
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86de536c8f
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changes jh globals to seperate riscv specifics
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2024-07-23 14:35:31 +02:00 |
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Eyck-Alexander Jentzsch
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051dd5e2d3
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updates templates for decoder in seperate class, adds again generated templates
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2024-07-23 13:46:10 +02:00 |
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Eyck-Alexander Jentzsch
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e3942be776
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Introduces decoder in a seperate class
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2024-07-23 13:08:53 +02:00 |
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Eyck-Alexander Jentzsch
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6ee484a771
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moves instruction decoder into own class
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2024-07-23 11:30:33 +02:00 |
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Eyck-Alexander Jentzsch
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60808c8649
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corrects template since util fns are no longer vm_base members
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2024-07-23 11:29:56 +02:00 |
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Eyck-Alexander Jentzsch
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0432803d82
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updates templates and vm impls for better LAST_BRANCH handling
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2024-07-22 09:04:17 +02:00 |
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Eyck-Alexander Jentzsch
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d42d2ce533
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corrects illegal instruction for llvm
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2024-07-18 14:04:23 +02:00 |
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Eyck-Alexander Jentzsch
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236d12d7f5
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integrates gen_bool for Conditions (was truncation) into llvm
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2024-07-18 13:30:42 +02:00 |
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Eyck-Alexander Jentzsch
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e1b6cab890
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removes setting of NEXT_PC to max when trapping in llvm and asmjit, adds default disass to llvm
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2024-07-18 12:02:40 +02:00 |
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Eyck-Alexander Jentzsch
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8361f88718
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removes setting of NEXT_PC to max if trap
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2024-07-18 11:37:53 +02:00 |
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Eyck-Alexander Jentzsch
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2ec7ea4b41
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removes leftover gen_sync in asmjit
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2024-07-17 22:39:12 +02:00 |
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Eyck-Alexander Jentzsch
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b24965d321
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corrects gen_sync update order, improves illegal instruction
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2024-07-17 20:52:01 +02:00 |
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Eyck-Alexander Jentzsch
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244bf6d2f2
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corrects gen_sync before trap check, improves illegal_instruction
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2024-07-17 20:25:49 +02:00 |
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Eyck-Alexander Jentzsch
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1a4465a371
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changes template: adds correct illegal instruction, reorders gen_sync to allow correct instr id eve when trapping, adds newly generated vm
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2024-07-17 19:59:01 +02:00 |
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Eyck-Alexander Jentzsch
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11a30caae8
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integrates generator changes to canPrecompute
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2024-07-17 15:14:13 +02:00 |
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Eyck-Alexander Jentzsch
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ac1a26a10c
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integrates new tval changes into llvm
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2024-07-17 14:17:02 +02:00 |
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Eyck-Alexander Jentzsch
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7a199e122d
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integrates new tval changes into asmjit
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2024-07-17 09:42:12 +02:00 |
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Eyck-Alexander Jentzsch
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d8c3d2e19c
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integrates new tval changes into tcc
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2024-07-16 17:35:23 +02:00 |
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Eyck-Alexander Jentzsch
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375755999a
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integrates new tval changes
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2024-07-16 15:32:35 +02:00 |
 Stanislaw Kaushanski
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9996fd4833
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change cache line size to 64
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2024-07-11 14:03:58 +02:00 |
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Eyck-Alexander Jentzsch
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149b3136d2
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updates generated files
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2024-07-10 12:55:36 +02:00 |
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Eyck-Alexander Jentzsch
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ac8f8b0539
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updates vms with fixed Zc in tgc5c.core_desc
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2024-07-10 12:51:59 +02:00 |
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Eyck-Alexander Jentzsch
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b2cbf90d0b
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updates generated files
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2024-07-10 12:51:59 +02:00 |
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Eyck-Alexander Jentzsch
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373145478e
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updats file because of generator changes
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2024-07-10 12:51:59 +02:00 |
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Eyck-Alexander Jentzsch
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55b0cea94f
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changes vm_base util API
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2024-07-10 12:51:59 +02:00 |
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Eyck-Alexander Jentzsch
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5b17599aa2
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allows usage of std::variants
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2024-07-10 12:51:59 +02:00 |
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Eyck-Alexander Jentzsch
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4cfb15c7cd
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Asmjit and interp working
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2024-07-10 12:51:31 +02:00 |
 Eyck Jentzsch
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63da7f8d57
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applies clang-format
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2024-07-09 13:57:11 +02:00 |
|
Eyck Jentzsch
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fb4012fbd1
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moves likely annotation
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2024-07-09 13:52:10 +02:00 |
|
Eyck Jentzsch
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24449f1c0f
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fixes some elf load issue
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2024-07-05 12:18:36 +02:00 |
|
Eyck Jentzsch
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fd303c8343
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fixes asmjit deprecation warning
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2024-07-05 07:51:37 +02:00 |
|
Eyck Jentzsch
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346b177a87
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extends finishing conditions
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2024-07-05 05:52:29 +02:00 |
|
Stanislaw Kaushanski
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d4ec131fa7
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change COUNT_LIMIT to ICOUNT_LIMIT
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2024-07-04 10:46:24 +02:00 |
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Eyck-Alexander Jentzsch
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48370a4555
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asmjit passes backend with new CoreDSL
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2024-06-22 09:28:26 +02:00 |
|
Eyck Jentzsch
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8460f4ab7f
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updates templates to re-enable interactive debugging of generator
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2024-06-21 10:46:11 +02:00 |
|
Eyck Jentzsch
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3fd51cc68c
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fixes templates
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2024-06-14 19:54:33 +02:00 |
|
Eyck Jentzsch
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551822916c
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applies clang-format
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2024-06-14 17:43:12 +02:00 |
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Eyck-Alexander Jentzsch
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e2da306eee
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fixes semihosting cb registration
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2024-05-31 10:45:28 +02:00 |
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Eyck-Alexander Jentzsch
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41051f8f34
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fixes tohost handling
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2024-05-31 10:43:38 +02:00 |
gabriel
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a6c48ceaac
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Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop
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2024-05-31 09:42:13 +02:00 |
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gabriel
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ed793471bb
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adding semhosting
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2024-05-31 07:27:47 +02:00 |
|
Eyck-Alexander Jentzsch
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58fb815f32
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fixes gen_raise in tcc
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2024-05-20 10:34:23 +02:00 |
|
Eyck-Alexander Jentzsch
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3cc8bd0854
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adds reformat bc of verilog literals
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2024-05-18 21:01:05 +02:00 |
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Eyck-Alexander Jentzsch
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a27850f841
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adds verilog literal and illegal_instr to asmjit
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2024-05-18 21:00:21 +02:00 |
|
Eyck-Alexander Jentzsch
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fb330cddea
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llvm passes act
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2024-05-18 19:33:57 +02:00 |
|
Eyck-Alexander Jentzsch
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b76c5bf0d6
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adds flush to fence_i
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2024-05-11 15:25:49 +02:00 |
|
Eyck-Alexander Jentzsch
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001c6349f7
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removes tcc sim stop when writing to tohost
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2024-05-11 15:16:46 +02:00 |
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Eyck-Alexander Jentzsch
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ee6a11dae6
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fixes typo
|
2024-05-09 20:54:30 +02:00 |
|
Eyck-Alexander Jentzsch
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2e27b025cc
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improves dump-ir comments
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2024-05-09 13:47:36 +02:00 |
|
Eyck-Alexander Jentzsch
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f0a004be9d
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adds information for debugging
|
2024-05-09 13:42:16 +02:00 |