Commit Graph

51 Commits

Author SHA1 Message Date
b9b165465d adds some template updates 2023-09-30 22:17:18 +02:00
e21f8dc379 allows functions in interp and updates generated 2023-09-05 10:08:00 +02:00
18e08cfc50 fixes missing template updates 2023-08-08 06:23:38 +02:00
7af7e040da Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2023-07-29 11:47:25 +02:00
6e52af168b adds faster decoding to tcc and cleans up others 2023-07-29 11:42:46 +02:00
bd0d15f3a2 updates template for faster instruction decoding 2023-07-23 08:10:57 +02:00
957145ca84 add SystemC ISS factory 2023-07-14 11:11:03 +02:00
b4b03f7850 fixes build system to handle TCC properly 2023-07-09 22:20:50 +02:00
e95f422aab cleans vm implementation up 2023-07-09 20:13:26 +02:00
250ea3c980 extends factory to support SystemC core wrapper 2023-07-09 18:19:59 +02:00
21d3250e1a changes templates 2023-07-09 16:53:59 +02:00
a123beb301 fixes duplicate variable declaration and templates 2023-05-27 10:20:49 +02:00
00b0f101ac adapts to changes of instrumentation interface in dbt-rise-core 2023-04-28 20:38:07 +02:00
d881cb6e63 fix data width of generated code 2023-03-26 12:12:34 +02:00
207dbf1071 fixes out of range access for register alias names 2023-02-17 06:28:30 +01:00
65dca13b42 fixes WFI miss of interrupt 2023-01-14 17:40:21 +01:00
7113683ee0 moves pending interrupt check before handling trap thus saving 1 cycle 2022-10-15 10:47:35 +02:00
00e02bf565 adds support for different branch types in tracing 2022-08-08 06:30:37 +02:00
0833198d34 aads missing windows compat firx to template 2022-07-23 14:36:23 +02:00
feaa49d367 removes decoder again as there is some issue 2022-06-20 00:39:11 +02:00
f096b15dbd factors decoder into separate component 2022-06-19 13:17:31 +02:00
5d481eb79d fix generation of non-exception code 2022-05-30 22:04:16 +02:00
52ed8b81a6 fixed template to work with previous code generator 2022-05-30 14:08:02 +02:00
0c542d42aa separate generated sources 2022-05-21 12:48:28 +02:00
df16378605 update template for changed code generator 2022-05-18 19:10:34 +02:00
9d9008a3a2 fix pointer mess 2022-04-26 15:35:17 +02:00
a92b84bef4 add code word access for ISS plugins 2022-04-25 14:18:19 +02:00
2e670c4d03 change interpreter structure 2022-03-06 15:11:38 +01:00
521f40a3d6 refactored interpreter backend structure 2022-03-05 20:59:17 +01:00
ef2a4df925 simplify spawn block handling 2022-01-31 23:40:31 +01:00
3563ba80d0 add spawn blocks 2022-01-12 07:21:16 +01:00
c42e336509 fix proper debug mode handling (#267 & #268) 2021-11-07 17:48:44 +01:00
334d3fb296 adapt to SCC changes 2021-10-21 22:53:16 +02:00
1d13c8196e fix wrong PGMASK usage 2021-10-11 10:40:01 +02:00
2f15d9676e fix unaligned instr fetch behavior 2021-09-30 19:27:46 +02:00
174259155d add support for non-compressed ISA 2021-09-23 21:09:52 +02:00
d95846a849 fix trap handling if illegal fetch (PMP) and U-mode CSRs 2021-08-01 17:23:22 +02:00
e68918c2e8 fix instruction decode 2021-07-09 07:37:12 +02:00
23b9741adf refine and fix TGC_C iss to becoem compliant 2021-06-29 11:51:30 +02:00
e432dd8208 fix handling of exceptions while accessing address spaces 2021-06-07 22:22:36 +02:00
aaceecd5dc fix mu_p platform features and CSRs 2021-05-17 09:20:09 +02:00
32e4aa83b8 use extracted variables 2021-03-27 09:36:52 +00:00
78c7064295 update groovy template to extract used registers 2021-03-26 08:24:45 +00:00
b0bcb7febb small fixes for robustness and readability 2021-03-22 22:47:30 +00:00
4e0f20eba0 rework abort conditions 2021-03-17 19:32:57 +00:00
80057eef32 fix RVC description bugs, remove paged fetch 2021-03-13 10:46:41 +00:00
a6691bcd3c update generated code with correct sign extension 2021-03-09 10:21:36 +00:00
c251fe15d5 fix desscriptions to conform to ISA spec version 20191213 and TGF-C 2021-03-07 10:51:00 +00:00
9534d58d01 regenerated sources and and add opcode enum to headers
Conflicts:
	gen_input/CoreDSL-Instruction-Set-Description
2021-03-01 06:26:33 +00:00
34bb8e62ae generate working ISS from CoreDSL 2.0 2021-02-06 14:47:06 +00:00