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a27850f841
|
adds verilog literal and illegal_instr to asmjit
|
2024-05-18 21:00:21 +02:00 |
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|
fb330cddea
|
llvm passes act
|
2024-05-18 19:33:57 +02:00 |
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|
ee6a11dae6
|
fixes typo
|
2024-05-09 20:54:30 +02:00 |
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|
2e27b025cc
|
improves dump-ir comments
|
2024-05-09 13:47:36 +02:00 |
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|
3422c7cd5c
|
optimizes writebacks
|
2024-05-08 15:18:38 +02:00 |
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|
ad79a28705
|
wip checkin
|
2024-04-30 19:21:27 +02:00 |
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|
1e6a0086e9
|
adds disass functionality
|
2024-03-07 13:58:08 +01:00 |
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|
119d4a8b43
|
adds generation if IMEM space
|
2024-02-21 07:08:24 +01:00 |
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|
9841b16122
|
fixes clang-format failures
|
2024-01-12 11:49:11 +01:00 |
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|
fe2d5cb2f9
|
adds semihosting to all backends
|
2024-01-10 11:47:12 +01:00 |
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|
207f778ee6
|
adds initial semihosting host capabilities
|
2024-01-08 17:17:59 +01:00 |
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|
f4f90c5e65
|
backports clang-format changes to template
|
2023-12-02 17:42:57 +01:00 |
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|
4418fa7e4f
|
fixes include path of asmjit helpers
|
2023-11-20 16:07:01 +01:00 |
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|
adaa7e1c04
|
updates template
|
2023-11-20 11:46:19 +01:00 |
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|
e48597b2b7
|
adds formatting fixes
|
2023-11-05 17:19:43 +01:00 |
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2115e9ceae
|
adds missing include to templates
|
2023-10-29 14:31:15 +01:00 |
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|
7001b693ae
|
updates templates for SystemC registration
|
2023-10-27 22:14:11 +02:00 |
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|
09db0cd35d
|
fixes LLVM backend registration for SystemC
|
2023-10-26 06:50:54 +02:00 |
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b7478965ab
|
adds asmjit backend registration for SystemC
|
2023-10-23 10:18:25 +02:00 |
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|
ffe730219d
|
merge commit
|
2023-10-22 15:13:25 +02:00 |
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|
60c926c921
|
adds asmjit
|
2023-10-22 15:11:20 +02:00 |
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|
3a86f4f9de
|
does some cleanup of generated files
|
2023-10-21 17:19:24 +02:00 |
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|
b9b165465d
|
adds some template updates
|
2023-09-30 22:17:18 +02:00 |
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|
b97853ff5a
|
update plugins to read YAML file
|
2023-09-30 22:10:24 +02:00 |
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|
417076f8e6
|
stops jit block creation in case of ECALL and EBREAK
|
2023-09-23 11:30:58 +02:00 |
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|
70839bbbf2
|
changes templates for correct plugin callback in case of trap
|
2023-09-23 10:35:21 +02:00 |
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|
|
8db0cc5d05
|
removes clutter
|
2023-09-23 10:34:58 +02:00 |
|
|
|
633c0d21a0
|
Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop
|
2023-09-20 15:17:43 +02:00 |
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|
51f6fbe0dd
|
applies newest CoreDSL changes
|
2023-09-20 15:12:03 +02:00 |
|
|
|
de45d06878
|
adds initial working version of llvm backend
|
2023-09-19 16:26:07 +02:00 |
|
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|
e21f8dc379
|
allows functions in interp and updates generated
|
2023-09-05 10:08:00 +02:00 |
|
|
|
813b40409d
|
Merge branch 'develop' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop
|
2023-08-30 10:05:42 +02:00 |
|
|
|
c8a4a4c736
|
renames core(s)
|
2023-08-28 07:09:55 +02:00 |
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|
|
18e08cfc50
|
fixes missing template updates
|
2023-08-08 06:23:38 +02:00 |
|
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|
20e920338c
|
removes v2p function
|
2023-08-04 13:08:10 +02:00 |
|
|
|
e151416f58
|
fixes systemc factory registration
|
2023-07-31 12:55:09 +02:00 |
|
|
|
e68f9c573f
|
Merge branch 'develop' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop
|
2023-07-30 09:14:58 +02:00 |
|
|
|
f38cc7d8b9
|
updates LLVM build
|
2023-07-29 17:55:37 +02:00 |
|
|
|
7af7e040da
|
Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop
|
2023-07-29 11:47:25 +02:00 |
|
|
|
6e52af168b
|
adds faster decoding to tcc and cleans up others
|
2023-07-29 11:42:46 +02:00 |
|
|
|
bd0d15f3a2
|
updates template for faster instruction decoding
|
2023-07-23 08:10:57 +02:00 |
|
|
|
720236ec3f
|
add generated core registration
|
2023-07-14 12:51:51 +02:00 |
|
|
|
957145ca84
|
add SystemC ISS factory
|
2023-07-14 11:11:03 +02:00 |
|
|
|
0b719a4b57
|
fixes literal type
|
2023-07-10 20:39:02 +02:00 |
|
|
|
b4b03f7850
|
fixes build system to handle TCC properly
|
2023-07-09 22:20:50 +02:00 |
|
|
|
e95f422aab
|
cleans vm implementation up
|
2023-07-09 20:13:26 +02:00 |
|
|
|
250ea3c980
|
extends factory to support SystemC core wrapper
|
2023-07-09 18:19:59 +02:00 |
|
|
|
21d3250e1a
|
changes templates
|
2023-07-09 16:53:59 +02:00 |
|
|
|
87b4082633
|
Merge branch 'tmp' into develop
|
2023-07-03 14:22:50 +02:00 |
|
|
|
99a9970ddd
|
fixes sysc compile issues
|
2023-06-12 09:58:24 +02:00 |
|
|
|
15cd36dcd4
|
adds fix for compressed instructions and reads
|
2023-06-05 17:57:38 +02:00 |
|
|
|
a123beb301
|
fixes duplicate variable declaration and templates
|
2023-05-27 10:20:49 +02:00 |
|
|
|
ce5b2e60b9
|
amends template to fix branching instructions
|
2023-05-22 17:00:36 +02:00 |
|
|
|
6ed7eafc5d
|
adds inital version of tcc backend
|
2023-05-16 21:51:35 +02:00 |
|
|
|
ee2ded931d
|
adds remaining register offsets
|
2023-05-14 17:16:42 +02:00 |
|
|
|
95ba5c901a
|
re-introduces last_branch register
|
2023-05-14 17:00:37 +02:00 |
|
|
|
00b0f101ac
|
adapts to changes of instrumentation interface in dbt-rise-core
|
2023-04-28 20:38:07 +02:00 |
|
|
|
d881cb6e63
|
fix data width of generated code
|
2023-03-26 12:12:34 +02:00 |
|
|
|
207dbf1071
|
fixes out of range access for register alias names
|
2023-02-17 06:28:30 +01:00 |
|
|
|
65dca13b42
|
fixes WFI miss of interrupt
|
2023-01-14 17:40:21 +01:00 |
|
|
|
7113683ee0
|
moves pending interrupt check before handling trap thus saving 1 cycle
|
2022-10-15 10:47:35 +02:00 |
|
|
|
00e02bf565
|
adds support for different branch types in tracing
|
2022-08-08 06:30:37 +02:00 |
|
|
|
0833198d34
|
aads missing windows compat firx to template
|
2022-07-23 14:36:23 +02:00 |
|
|
|
4876f18ba9
|
adds windows compatibility fixes
|
2022-07-18 11:43:42 +02:00 |
|
|
|
feaa49d367
|
removes decoder again as there is some issue
|
2022-06-20 00:39:11 +02:00 |
|
|
|
18f33b4a68
|
fixes ordering of instructions for decoding
|
2022-06-19 16:52:29 +02:00 |
|
|
|
f096b15dbd
|
factors decoder into separate component
|
2022-06-19 13:17:31 +02:00 |
|
|
|
5d481eb79d
|
fix generation of non-exception code
|
2022-05-30 22:04:16 +02:00 |
|
|
|
52ed8b81a6
|
fixed template to work with previous code generator
|
2022-05-30 14:08:02 +02:00 |
|
|
|
0c542d42aa
|
separate generated sources
|
2022-05-21 12:48:28 +02:00 |
|
|
|
df16378605
|
update template for changed code generator
|
2022-05-18 19:10:34 +02:00 |
|
|
|
e88f309ea2
|
add lz4 compression to pctrace
|
2022-05-07 17:22:06 +02:00 |
|
|
|
9d9008a3a2
|
fix pointer mess
|
2022-04-26 15:35:17 +02:00 |
|
|
|
a92b84bef4
|
add code word access for ISS plugins
|
2022-04-25 14:18:19 +02:00 |
|
|
|
2e670c4d03
|
change interpreter structure
|
2022-03-06 15:11:38 +01:00 |
|
|
|
3d32c33333
|
update gitignore
|
2022-03-05 20:59:45 +01:00 |
|
|
|
521f40a3d6
|
refactored interpreter backend structure
|
2022-03-05 20:59:17 +01:00 |
|
|
|
b8fa5fbbda
|
adapt to extended instrumentation interface
|
2022-02-09 21:01:17 +01:00 |
|
|
|
68b5697c8f
|
Fix cycles JSON template
|
2022-02-01 21:48:56 +01:00 |
|
|
|
059bd0d371
|
rework cycle estimation
|
2022-02-01 19:03:45 +01:00 |
|
|
|
ef2a4df925
|
simplify spawn block handling
|
2022-01-31 23:40:31 +01:00 |
|
|
|
afe8905ac9
|
fix else-ambiguity in CoreDSL description
|
2022-01-31 20:30:46 +01:00 |
|
|
|
3563ba80d0
|
add spawn blocks
|
2022-01-12 07:21:16 +01:00 |
|
|
|
07d5af1dde
|
fix stand-alone ISS compilation to include all generated cores
|
2021-11-26 17:56:40 +01:00 |
|
|
|
965929d1eb
|
remove descriptions
|
2021-11-15 09:30:16 +01:00 |
|
|
|
d31b4ef5a8
|
fix MISA val
|
2021-11-11 12:58:57 +01:00 |
|
|
|
7452c5df43
|
add TGC_D_XRB_NN definition
|
2021-11-11 12:16:35 +01:00 |
|
|
|
fd98ad95f6
|
rework PMP check and fix MISA for TGC_D
|
2021-11-09 15:55:22 +01:00 |
|
|
|
c42e336509
|
fix proper debug mode handling (#267 & #268)
|
2021-11-07 17:48:44 +01:00 |
|
|
|
8b6e3abd23
|
fix hard-code arch in templates
|
2021-10-30 13:37:17 +02:00 |
|
|
|
1616f0ac90
|
remove deprecated functions
|
2021-10-30 12:57:08 +02:00 |
|
|
|
a20f39e847
|
update core definitions to include Zicsr and Zifencei (#276)
|
2021-10-30 12:56:31 +02:00 |
|
|
|
334d3fb296
|
adapt to SCC changes
|
2021-10-21 22:53:16 +02:00 |
|
|
|
1d13c8196e
|
fix wrong PGMASK usage
|
2021-10-11 10:40:01 +02:00 |
|
|
|
b17682e50e
|
fix YAML template
|
2021-10-01 23:49:04 +02:00 |
|
|
|
6acf73a40f
|
add template to generate instruction YAML
|
2021-10-01 13:05:36 +02:00 |
|
|
|
2f15d9676e
|
fix unaligned instr fetch behavior
|
2021-09-30 19:27:46 +02:00 |
|
|
|
4186723d37
|
add marchid setting to CoreDSL description
|
2021-09-30 19:26:21 +02:00 |
|
|
|
aa84a27a5b
|
fix JALR alignment in description
|
2021-09-29 00:43:42 +02:00 |
|
|
|
438e598a4a
|
remove clutter from core descriptions, added instr alignment setting
|
2021-09-29 00:03:11 +02:00 |
|
