applies clang-format
This commit is contained in:
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0996d15bd4
commit
bb4e2766d1
@ -204,7 +204,7 @@ private:
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};
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this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
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}
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this->gen_sync(iss::PRE_SYNC, instr_descr.size());
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this->gen_sync(iss::PRE_SYNC, instr_descr.size());
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this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
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get_reg_ptr(traits::PC), true);
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this->builder.CreateStore(
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@ -381,4 +381,4 @@ volatile std::array<bool, 2> dummy = {
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};
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}
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}
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// clang-format on
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// clang-format on
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@ -602,7 +602,7 @@ std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT, LOGCAT>::load_file(std::str
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if(reader.get_machine() != EM_RISCV)
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throw std::runtime_error("wrong elf machine in file");
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auto entry = reader.get_entry();
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for(const auto pseg : reader.segments) {
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for(const auto& pseg : reader.segments) {
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const auto fsize = pseg->get_file_size(); // 0x42c/0x0
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const auto seg_data = pseg->get_data();
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const auto type = pseg->get_type();
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@ -689,7 +689,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
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}
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return res;
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} catch(trap_access& ta) {
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if( (access & access_type::DEBUG) == 0) {
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if((access & access_type::DEBUG) == 0) {
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this->reg.trap_state = (1UL << 31) | ta.id;
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fault_data = ta.addr;
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}
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@ -671,8 +671,10 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
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}
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return res;
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} catch(trap_access& ta) {
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this->reg.trap_state = (1 << 31) | ta.id;
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fault_data = ta.addr;
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if((access & access_type::DEBUG) == 0) {
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this->reg.trap_state = (1UL << 31) | ta.id;
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fault_data = ta.addr;
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}
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return iss::Err;
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}
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} break;
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@ -710,8 +712,10 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
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}
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return iss::Ok;
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} catch(trap_access& ta) {
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this->reg.trap_state = (1UL << 31) | ta.id;
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fault_data = ta.addr;
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if((access & access_type::DEBUG) == 0) {
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this->reg.trap_state = (1UL << 31) | ta.id;
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fault_data = ta.addr;
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}
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return iss::Err;
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}
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}
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@ -841,8 +845,10 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
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}
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return iss::Ok;
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} catch(trap_access& ta) {
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this->reg.trap_state = (1UL << 31) | ta.id;
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fault_data = ta.addr;
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if((access & access_type::DEBUG) == 0) {
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this->reg.trap_state = (1UL << 31) | ta.id;
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fault_data = ta.addr;
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}
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return iss::Err;
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}
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}
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@ -674,7 +674,7 @@ std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT, LOGCAT>::load_file(std::st
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if(reader.get_machine() != EM_RISCV)
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throw std::runtime_error("wrong elf machine in file");
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auto entry = reader.get_entry();
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for(const auto pseg : reader.segments) {
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for(const auto& pseg : reader.segments) {
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const auto fsize = pseg->get_file_size(); // 0x42c/0x0
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const auto seg_data = pseg->get_data();
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const auto type = pseg->get_type();
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@ -685,7 +685,7 @@ std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT, LOGCAT>::load_file(std::st
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CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
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}
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}
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for(const auto sec : reader.sections) {
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for(const auto& sec : reader.sections) {
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if(sec->get_name() == ".symtab") {
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if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) {
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ELFIO::symbol_section_accessor symbols(reader, sec);
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@ -877,8 +877,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read(const address_type type, c
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}
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return res;
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} catch(trap_access& ta) {
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this->reg.trap_state = (1UL << 31) | ta.id;
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fault_data = ta.addr;
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if((access & access_type::DEBUG) == 0) {
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this->reg.trap_state = (1UL << 31) | ta.id;
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fault_data = ta.addr;
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}
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return iss::Err;
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}
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} break;
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@ -905,8 +907,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read(const address_type type, c
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}
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return iss::Ok;
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} catch(trap_access& ta) {
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this->reg.trap_state = (1UL << 31) | ta.id;
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fault_data = ta.addr;
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if((access & access_type::DEBUG) == 0) {
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this->reg.trap_state = (1UL << 31) | ta.id;
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fault_data = ta.addr;
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}
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return iss::Err;
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}
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}
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@ -1045,8 +1049,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write(const address_type type,
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}
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return iss::Ok;
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} catch(trap_access& ta) {
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this->reg.trap_state = (1UL << 31) | ta.id;
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fault_data = ta.addr;
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if((access & access_type::DEBUG) == 0) {
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this->reg.trap_state = (1UL << 31) | ta.id;
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fault_data = ta.addr;
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}
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return iss::Err;
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}
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}
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File diff suppressed because it is too large
Load Diff
@ -39,8 +39,6 @@
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#include <iss/iss.h>
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#include <array>
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#include <iostream>
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#include <fstream>
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#include <memory>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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@ -109,7 +107,7 @@ public:
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status process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) override;
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status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num,
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bool& done) override;
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bool& done) override;
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status current_thread_query(rp_thread_ref& thread) override;
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@ -140,15 +138,11 @@ protected:
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rp_thread_ref thread_idx;
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};
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template <typename ARCH>
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typename std::enable_if<iss::arch::traits<ARCH>::FLEN!=0, unsigned>::type get_f0_offset() {
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template <typename ARCH> typename std::enable_if<iss::arch::traits<ARCH>::FLEN != 0, unsigned>::type get_f0_offset() {
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return iss::arch::traits<ARCH>::F0;
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}
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template <typename ARCH>
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typename std::enable_if<iss::arch::traits<ARCH>::FLEN==0, unsigned>::type get_f0_offset() {
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return 0;
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}
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template <typename ARCH> typename std::enable_if<iss::arch::traits<ARCH>::FLEN == 0, unsigned>::type get_f0_offset() { return 0; }
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template <typename ARCH> status riscv_target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) {
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thread_idx = thread;
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@ -197,14 +191,14 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::
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auto start_reg = arch::traits<ARCH>::X0;
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for(size_t i = 0; i < 33; ++i) {
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if(i < arch::traits<ARCH>::RFS || i == arch::traits<ARCH>::PC) {
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auto reg_no = i<32? start_reg + i: arch::traits<ARCH>::PC;
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auto reg_no = i < 32 ? start_reg + i : arch::traits<ARCH>::PC;
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unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
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for(size_t j = 0; j < arch::traits<ARCH>::XLEN/8; ++j) {
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for(size_t j = 0; j < arch::traits<ARCH>::XLEN / 8; ++j) {
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data.push_back(*(reg_base + offset + j));
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avail.push_back(0xff);
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}
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} else {
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for(size_t j = 0; j < arch::traits<ARCH>::XLEN/8; ++j) {
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for(size_t j = 0; j < arch::traits<ARCH>::XLEN / 8; ++j) {
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data.push_back(0);
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avail.push_back(0);
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}
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@ -229,15 +223,15 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
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auto start_reg = arch::traits<ARCH>::X0;
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auto* reg_base = core->get_regs_base_ptr();
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auto iter = data.data();
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auto iter_end = data.data()+data.size();
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auto iter_end = data.data() + data.size();
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for(size_t i = 0; i < 33 && iter < iter_end; ++i) {
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auto reg_width = arch::traits<ARCH>::XLEN / 8;
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if(i < arch::traits<ARCH>::RFS) {
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auto offset = traits<ARCH>::reg_byte_offsets[start_reg + i];
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std::copy(iter, iter + reg_width, reg_base+offset);
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std::copy(iter, iter + reg_width, reg_base + offset);
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} else if(i == 32) {
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auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
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std::copy(iter, iter + reg_width, reg_base+offset);
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std::copy(iter, iter + reg_width, reg_base + offset);
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}
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iter += reg_width;
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}
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@ -246,7 +240,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
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auto reg_width = arch::traits<ARCH>::FLEN / 8;
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for(size_t i = 0; i < 32 && iter < iter_end; ++i) {
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unsigned offset = traits<ARCH>::reg_byte_offsets[fstart_reg + i];
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std::copy(iter, iter + reg_width, reg_base+offset);
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std::copy(iter, iter + reg_width, reg_base + offset);
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iter += reg_width;
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}
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}
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@ -255,7 +249,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
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if(reg_no <csr_offset) {
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if(reg_no < csr_offset) {
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// auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
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// arch::traits<ARCH>::reg_e>(reg_no))/8;
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auto* reg_base = core->get_regs_base_ptr();
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@ -349,7 +343,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type
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auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
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target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
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CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
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<< std::dec;
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<< std::dec;
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CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
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return Ok;
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}
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@ -379,7 +373,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_t
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
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std::function<void(unsigned)> stop_callback) {
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std::function<void(unsigned)> stop_callback) {
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auto* reg_base = core->get_regs_base_ptr();
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
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auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
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@ -398,17 +392,20 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std
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oss << " <architectureriscv:rv64</architecture>\n";
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oss << " <feature name=\"org.gnu.gdb.riscv.cpu\">\n";
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auto reg_base_num = iss::arch::traits<ARCH>::X0;
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for(auto i = 0U; i<iss::arch::traits<ARCH>::RFS; ++i) {
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oss << " <reg name=\"x" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i] << "\" type=\"int\" regnum=\"" << i << "\"/>\n";
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for(auto i = 0U; i < iss::arch::traits<ARCH>::RFS; ++i) {
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oss << " <reg name=\"x" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i]
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<< "\" type=\"int\" regnum=\"" << i << "\"/>\n";
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}
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oss << " <reg name=\"pc\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[iss::arch::traits<ARCH>::PC] << "\" type=\"code_ptr\" regnum=\"" << 32U << "\"/>\n";
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oss << " <reg name=\"pc\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[iss::arch::traits<ARCH>::PC]
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<< "\" type=\"code_ptr\" regnum=\"" << 32U << "\"/>\n";
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oss << " </feature>\n";
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if(iss::arch::traits<ARCH>::FLEN > 0) {
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oss << " <feature name=\"org.gnu.gdb.riscv.fpu\">\n";
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auto reg_base_num = get_f0_offset<ARCH>();
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auto type = iss::arch::traits<ARCH>::FLEN==32?"ieee_single":"riscv_double";
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for(auto i = 0U; i<32; ++i) {
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oss << " <reg name=\"f" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i] << "\" type=\""<<type<<"\" regnum=\"" << i+33 << "\"/>\n";
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auto reg_base_num = get_f0_offset<ARCH>();
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auto type = iss::arch::traits<ARCH>::FLEN == 32 ? "ieee_single" : "riscv_double";
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for(auto i = 0U; i < 32; ++i) {
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oss << " <reg name=\"f" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i]
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<< "\" type=\"" << type << "\" regnum=\"" << i + 33 << "\"/>\n";
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}
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oss << " <reg name=\"fcsr\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"103\" type int/>\n";
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oss << " <reg name=\"fflags\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"101\" type int/>\n";
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@ -420,12 +417,13 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std
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std::vector<uint8_t> avail;
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data.resize(sizeof(typename traits<ARCH>::reg_t));
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avail.resize(sizeof(typename traits<ARCH>::reg_t));
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for(auto i = 0U; i<4096; ++i) {
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for(auto i = 0U; i < 4096; ++i) {
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typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, i);
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std::fill(avail.begin(), avail.end(), 0xff);
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auto res = core->read(a, data.size(), data.data());
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if(res == iss::Ok) {
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oss << " <reg name=\"" << get_csr_name(i) << "\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" type=\"int\" regnum=\"" << (i + csr_offset) << "\"/>\n";
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oss << " <reg name=\"" << get_csr_name(i) << "\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN
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<< "\" type=\"int\" regnum=\"" << (i + csr_offset) << "\"/>\n";
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}
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}
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oss << " </feature>\n";
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@ -42,7 +42,6 @@
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#include <iss/plugin/loader.h>
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#endif
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#include "sc_core_adapter_if.h"
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#include <iss/arch/tgc_mapper.h>
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#include <scc/report.h>
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#include <util/ities.h>
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#include <iostream>
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@ -208,8 +207,7 @@ core_complex<BUSWIDTH>::core_complex(sc_module_name const& name)
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}
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#endif
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template <unsigned int BUSWIDTH>
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void core_complex<BUSWIDTH>::init() {
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template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::init() {
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trc = new core_trace();
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ibus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
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auto lut_entry = fetch_lut.getEntry(start);
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@ -254,19 +252,16 @@ void core_complex<BUSWIDTH>::init() {
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#endif
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}
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template <unsigned int BUSWIDTH>
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core_complex<BUSWIDTH>::~core_complex() {
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template <unsigned int BUSWIDTH> core_complex<BUSWIDTH>::~core_complex() {
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delete cpu;
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delete trc;
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for(auto* p : plugin_list)
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delete p;
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}
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template <unsigned int BUSWIDTH>
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void core_complex<BUSWIDTH>::trace(sc_trace_file* trf) const {}
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template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::trace(sc_trace_file* trf) const {}
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template <unsigned int BUSWIDTH>
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void core_complex<BUSWIDTH>::before_end_of_elaboration() {
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template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::before_end_of_elaboration() {
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SCCDEBUG(SCMOD) << "instantiating iss::arch::tgf with " << GET_PROP_VALUE(backend) << " backend";
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// cpu = scc::make_unique<core_wrapper>(this);
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cpu = new core_wrapper(this);
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@ -307,8 +302,7 @@ void core_complex<BUSWIDTH>::before_end_of_elaboration() {
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}
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}
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template <unsigned int BUSWIDTH>
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void core_complex<BUSWIDTH>::start_of_simulation() {
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template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::start_of_simulation() {
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// quantum_keeper.reset();
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if(GET_PROP_VALUE(elf_file).size() > 0) {
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istringstream is(GET_PROP_VALUE(elf_file));
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@ -331,8 +325,7 @@ void core_complex<BUSWIDTH>::start_of_simulation() {
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}
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}
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template <unsigned int BUSWIDTH>
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bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_str) {
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template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_str) {
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if(trc->m_db == nullptr)
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return false;
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if(trc->tr_handle.is_active())
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@ -346,8 +339,7 @@ bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_
|
||||
return true;
|
||||
}
|
||||
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::forward() {
|
||||
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::forward() {
|
||||
#ifndef CWR_SYSTEMC
|
||||
set_clock_period(clk_i.read());
|
||||
#else
|
||||
@ -356,30 +348,24 @@ void core_complex<BUSWIDTH>::forward() {
|
||||
#endif
|
||||
}
|
||||
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::set_clock_period(sc_core::sc_time period) {
|
||||
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::set_clock_period(sc_core::sc_time period) {
|
||||
curr_clk = period;
|
||||
if(period == SC_ZERO_TIME)
|
||||
cpu->set_interrupt_execution(true);
|
||||
}
|
||||
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::rst_cb() {
|
||||
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::rst_cb() {
|
||||
if(rst_i.read())
|
||||
cpu->set_interrupt_execution(true);
|
||||
}
|
||||
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
|
||||
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
|
||||
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
|
||||
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
|
||||
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
|
||||
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
|
||||
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::local_irq_cb() {
|
||||
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::local_irq_cb() {
|
||||
for(auto i = 0U; i < local_irq_i.size(); ++i) {
|
||||
if(local_irq_i[i].event()) {
|
||||
cpu->local_irq(16 + i, local_irq_i[i].read());
|
||||
@ -387,8 +373,7 @@ void core_complex<BUSWIDTH>::local_irq_cb() {
|
||||
}
|
||||
}
|
||||
|
||||
template <unsigned int BUSWIDTH>
|
||||
void core_complex<BUSWIDTH>::run() {
|
||||
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::run() {
|
||||
wait(SC_ZERO_TIME); // separate from elaboration phase
|
||||
do {
|
||||
wait(SC_ZERO_TIME);
|
||||
@ -406,8 +391,7 @@ void core_complex<BUSWIDTH>::run() {
|
||||
sc_stop();
|
||||
}
|
||||
|
||||
template <unsigned int BUSWIDTH>
|
||||
bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
|
||||
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
|
||||
auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
|
||||
auto lut_entry = dmi_lut.getEntry(addr);
|
||||
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
|
||||
@ -465,8 +449,7 @@ bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* c
|
||||
}
|
||||
}
|
||||
|
||||
template <unsigned int BUSWIDTH>
|
||||
bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
|
||||
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
|
||||
auto lut_entry = write_lut.getEntry(addr);
|
||||
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
|
||||
auto offset = addr - lut_entry.get_start_address();
|
||||
@ -514,8 +497,7 @@ bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uin
|
||||
}
|
||||
}
|
||||
|
||||
template <unsigned int BUSWIDTH>
|
||||
bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
|
||||
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
|
||||
tlm::tlm_generic_payload gp;
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(addr);
|
||||
@ -525,8 +507,7 @@ bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_
|
||||
return dbus->transport_dbg(gp) == length;
|
||||
}
|
||||
|
||||
template <unsigned int BUSWIDTH>
|
||||
bool core_complex<BUSWIDTH>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
|
||||
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
|
||||
write_buf.resize(length);
|
||||
std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
|
||||
tlm::tlm_generic_payload gp;
|
||||
|
||||
@ -33,10 +33,10 @@
|
||||
#ifndef _SYSC_CORE_COMPLEX_H_
|
||||
#define _SYSC_CORE_COMPLEX_H_
|
||||
|
||||
#include <scc/signal_opt_ports.h>
|
||||
#include <scc/tick2time.h>
|
||||
#include <scc/traceable.h>
|
||||
#include <scc/utilities.h>
|
||||
#include <scc/signal_opt_ports.h>
|
||||
#include <tlm/scc/initiator_mixin.h>
|
||||
#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
|
||||
#ifdef CWR_SYSTEMC
|
||||
@ -71,28 +71,27 @@ struct core_complex_if {
|
||||
|
||||
virtual ~core_complex_if() = default;
|
||||
|
||||
virtual bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) =0;
|
||||
virtual bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) = 0;
|
||||
|
||||
virtual bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) =0;
|
||||
virtual bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) = 0;
|
||||
|
||||
virtual bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) =0;
|
||||
virtual bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) = 0;
|
||||
|
||||
virtual bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) =0;
|
||||
virtual bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) = 0;
|
||||
|
||||
virtual bool disass_output(uint64_t pc, const std::string instr) =0;
|
||||
virtual bool disass_output(uint64_t pc, const std::string instr) = 0;
|
||||
|
||||
virtual unsigned get_last_bus_cycles() =0;
|
||||
virtual unsigned get_last_bus_cycles() = 0;
|
||||
|
||||
//! Allow quantum keeper handling
|
||||
virtual void sync(uint64_t) =0;
|
||||
virtual void sync(uint64_t) = 0;
|
||||
|
||||
virtual char const* hier_name() = 0;
|
||||
|
||||
scc::sc_in_opt<uint64_t> mtime_i{"mtime_i"};
|
||||
};
|
||||
|
||||
template <unsigned int BUSWIDTH = scc::LT>
|
||||
class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
|
||||
template <unsigned int BUSWIDTH = scc::LT> class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
|
||||
public:
|
||||
tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> ibus{"ibus"};
|
||||
|
||||
@ -208,9 +207,7 @@ public:
|
||||
|
||||
void set_clock_period(sc_core::sc_time period);
|
||||
|
||||
char const* hier_name() override {
|
||||
return name();
|
||||
}
|
||||
char const* hier_name() override { return name(); }
|
||||
|
||||
protected:
|
||||
void before_end_of_elaboration() override;
|
||||
|
||||
@ -55,8 +55,8 @@ public:
|
||||
s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2)
|
||||
<< (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount + this->cycle_offset << "]";
|
||||
SCCDEBUG(owner->hier_name()) << "disass: "
|
||||
<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
|
||||
<< std::setfill(' ') << std::left << instr << s.str();
|
||||
<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t"
|
||||
<< std::setw(40) << std::setfill(' ') << std::left << instr << s.str();
|
||||
}
|
||||
};
|
||||
|
||||
@ -113,7 +113,7 @@ public:
|
||||
|
||||
iss::status read_csr(unsigned addr, reg_t& val) override {
|
||||
if((addr == iss::arch::time || addr == iss::arch::timeh)) {
|
||||
uint64_t time_val = owner->mtime_i.get_interface()? owner->mtime_i.read():0;
|
||||
uint64_t time_val = owner->mtime_i.get_interface() ? owner->mtime_i.read() : 0;
|
||||
if(addr == iss::arch::time) {
|
||||
val = static_cast<reg_t>(time_val);
|
||||
} else if(addr == iss::arch::timeh) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user