439 lines
19 KiB
C++
439 lines
19 KiB
C++
/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#ifndef _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_
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#define _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_
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#include "iss/arch_if.h"
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#include <iss/arch/traits.h>
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#include <iss/debugger/target_adapter_base.h>
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#include <iss/iss.h>
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#include <array>
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#include <memory>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <util/logging.h>
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namespace iss {
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namespace debugger {
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char const* const get_csr_name(unsigned);
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constexpr auto csr_offset = 100U;
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using namespace iss::arch;
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using namespace iss::debugger;
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template <typename ARCH> class riscv_target_adapter : public target_adapter_base {
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public:
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riscv_target_adapter(server_if* srv, iss::arch_if* core)
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: target_adapter_base(srv)
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, core(core) {}
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/*============== Thread Control ===============================*/
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/* Set generic thread */
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status set_gen_thread(rp_thread_ref& thread) override;
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/* Set control thread */
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status set_ctrl_thread(rp_thread_ref& thread) override;
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/* Get thread status */
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status is_thread_alive(rp_thread_ref& thread, bool& alive) override;
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/*============= Register Access ================================*/
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/* Read all registers. buf is 4-byte aligned and it is in
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target byte order. If register is not available
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corresponding bytes in avail_buf are 0, otherwise
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avail buf is 1 */
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status read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) override;
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/* Write all registers. buf is 4-byte aligned and it is in target
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byte order */
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status write_registers(const std::vector<uint8_t>& data) override;
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/* Read one register. buf is 4-byte aligned and it is in
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target byte order. If register is not available
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corresponding bytes in avail_buf are 0, otherwise
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avail buf is 1 */
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status read_single_register(unsigned int reg_no, std::vector<uint8_t>& buf, std::vector<uint8_t>& avail_buf) override;
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/* Write one register. buf is 4-byte aligned and it is in target byte
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order */
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status write_single_register(unsigned int reg_no, const std::vector<uint8_t>& buf) override;
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/*=================== Memory Access =====================*/
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/* Read memory, buf is 4-bytes aligned and it is in target
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byte order */
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status read_mem(uint64_t addr, std::vector<uint8_t>& buf) override;
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/* Write memory, buf is 4-bytes aligned and it is in target
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byte order */
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status write_mem(uint64_t addr, const std::vector<uint8_t>& buf) override;
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status process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) override;
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status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num,
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bool& done) override;
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status current_thread_query(rp_thread_ref& thread) override;
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status offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) override;
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status crc_query(uint64_t addr, size_t len, uint32_t& val) override;
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status raw_query(std::string in_buf, std::string& out_buf) override;
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status threadinfo_query(int first, std::string& out_buf) override;
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status threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) override;
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status packetsize_query(std::string& out_buf) override;
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status add_break(break_type type, uint64_t addr, unsigned int length) override;
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status remove_break(break_type type, uint64_t addr, unsigned int length) override;
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status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, std::function<void(unsigned)> stop_callback) override;
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status target_xml_query(std::string& out_buf) override;
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protected:
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static inline constexpr addr_t map_addr(const addr_t& i) { return i; }
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std::string csr_xml;
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iss::arch_if* core;
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rp_thread_ref thread_idx;
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};
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template <typename ARCH> typename std::enable_if<iss::arch::traits<ARCH>::FLEN != 0, unsigned>::type get_f0_offset() {
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return iss::arch::traits<ARCH>::F0;
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}
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template <typename ARCH> typename std::enable_if<iss::arch::traits<ARCH>::FLEN == 0, unsigned>::type get_f0_offset() { return 0; }
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template <typename ARCH> status riscv_target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) {
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thread_idx = thread;
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::set_ctrl_thread(rp_thread_ref& thread) {
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thread_idx = thread;
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_thread_ref& thread, bool& alive) {
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alive = 1;
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return Ok;
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}
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/* List threads. If first is non-zero then start from the first thread,
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* otherwise start from arg, result points to array of threads to be
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* filled out, result size is number of elements in the result,
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* num points to the actual number of threads found, done is
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* set if all threads are processed.
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*/
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result,
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size_t max_num, size_t& num, bool& done) {
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if(first == 0) {
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result.clear();
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result.push_back(thread_idx);
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num = 1;
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done = true;
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return Ok;
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} else
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return NotSupported;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query(rp_thread_ref& thread) {
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thread = thread_idx;
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
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CPPLOG(TRACE) << "reading target registers";
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data.clear();
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avail.clear();
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const uint8_t* reg_base = core->get_regs_base_ptr();
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auto start_reg = arch::traits<ARCH>::X0;
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for(size_t i = 0; i < 33; ++i) {
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if(i < arch::traits<ARCH>::RFS || i == arch::traits<ARCH>::PC) {
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auto reg_no = i < 32 ? start_reg + i : arch::traits<ARCH>::PC;
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unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
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for(size_t j = 0; j < arch::traits<ARCH>::XLEN / 8; ++j) {
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data.push_back(*(reg_base + offset + j));
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avail.push_back(0xff);
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}
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} else {
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for(size_t j = 0; j < arch::traits<ARCH>::XLEN / 8; ++j) {
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data.push_back(0);
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avail.push_back(0);
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}
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}
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}
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if(iss::arch::traits<ARCH>::FLEN > 0) {
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auto fstart_reg = get_f0_offset<ARCH>();
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for(size_t i = 0; i < 32; ++i) {
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auto reg_no = fstart_reg + i;
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
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unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
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for(size_t j = 0; j < reg_width; ++j) {
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data.push_back(*(reg_base + offset + j));
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avail.push_back(0xff);
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}
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}
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}
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(const std::vector<uint8_t>& data) {
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auto start_reg = arch::traits<ARCH>::X0;
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auto* reg_base = core->get_regs_base_ptr();
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auto iter = data.data();
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auto iter_end = data.data() + data.size();
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for(size_t i = 0; i < 33 && iter < iter_end; ++i) {
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auto reg_width = arch::traits<ARCH>::XLEN / 8;
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if(i < arch::traits<ARCH>::RFS) {
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auto offset = traits<ARCH>::reg_byte_offsets[start_reg + i];
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std::copy(iter, iter + reg_width, reg_base + offset);
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} else if(i == 32) {
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auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
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std::copy(iter, iter + reg_width, reg_base + offset);
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}
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iter += reg_width;
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}
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if(iss::arch::traits<ARCH>::FLEN > 0) {
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auto fstart_reg = get_f0_offset<ARCH>();
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auto reg_width = arch::traits<ARCH>::FLEN / 8;
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for(size_t i = 0; i < 32 && iter < iter_end; ++i) {
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unsigned offset = traits<ARCH>::reg_byte_offsets[fstart_reg + i];
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std::copy(iter, iter + reg_width, reg_base + offset);
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iter += reg_width;
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}
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}
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return Ok;
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}
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
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if(reg_no < csr_offset) {
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// auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
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// arch::traits<ARCH>::reg_e>(reg_no))/8;
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auto* reg_base = core->get_regs_base_ptr();
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
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data.resize(reg_width);
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avail.resize(reg_width);
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auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
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std::copy(reg_base + offset, reg_base + offset + reg_width, data.begin());
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std::fill(avail.begin(), avail.end(), 0xff);
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} else {
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typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, reg_no - csr_offset);
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data.resize(sizeof(typename traits<ARCH>::reg_t));
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avail.resize(sizeof(typename traits<ARCH>::reg_t));
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std::fill(avail.begin(), avail.end(), 0xff);
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core->read(a, data.size(), data.data());
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std::fill(avail.begin(), avail.end(), 0xff);
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}
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return data.size() > 0 ? Ok : Err;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t>& data) {
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if(reg_no < csr_offset) {
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auto* reg_base = core->get_regs_base_ptr();
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
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auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
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std::copy(data.begin(), data.begin() + reg_width, reg_base + offset);
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} else {
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typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - csr_offset);
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core->write(a, data.size(), data.data());
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}
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t>& data) {
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auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
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auto f = [&]() -> status { return core->read(a, data.size(), data.data()); };
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return srv->execute_syncronized(f);
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t>& data) {
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auto a = map_addr({iss::access_type::DEBUG_WRITE, iss::address_type::VIRTUAL, 0, addr});
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auto f = [&]() -> status { return core->write(a, data.size(), data.data()); };
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return srv->execute_syncronized(f);
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}
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) {
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return NotSupported;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) {
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text = 0;
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data = 0;
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bss = 0;
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t& val) { return NotSupported; }
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template <typename ARCH> status riscv_target_adapter<ARCH>::raw_query(std::string in_buf, std::string& out_buf) { return NotSupported; }
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template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int first, std::string& out_buf) {
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if(first) {
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out_buf = fmt::format("m{:x}", thread_idx.val);
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} else {
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out_buf = "l";
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}
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) {
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std::array<char, 20> buf;
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memset(buf.data(), 0, 20);
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sprintf(buf.data(), "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
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out_buf = buf.data();
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std::string& out_buf) {
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out_buf = "PacketSize=1000";
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type type, uint64_t addr, unsigned int length) {
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switch(type) {
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default:
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return Err;
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case SW_EXEC:
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case HW_EXEC: {
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auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
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auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
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target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
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CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
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<< std::dec;
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CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
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return Ok;
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}
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}
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_type type, uint64_t addr, unsigned int length) {
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switch(type) {
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default:
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return Err;
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case SW_EXEC:
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case HW_EXEC: {
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auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
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unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
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if(handle) {
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CPPLOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec;
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// TODO: check length of addr range
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target_adapter_base::bp_lut.removeEntry(handle);
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CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
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return Ok;
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}
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CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
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return Err;
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}
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}
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}
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
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std::function<void(unsigned)> stop_callback) {
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auto* reg_base = core->get_regs_base_ptr();
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auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
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auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
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const uint8_t* iter = reinterpret_cast<const uint8_t*>(&addr);
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std::copy(iter, iter + reg_width, reg_base);
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return resume_from_current(step, sig, thread, stop_callback);
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string& out_buf) {
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if(!csr_xml.size()) {
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std::ostringstream oss;
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oss << "<?xml version=\"1.0\"?><!DOCTYPE feature SYSTEM \"gdb-target.dtd\"><target version=\"1.0\">\n";
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if(iss::arch::traits<ARCH>::XLEN == 32)
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oss << "<architecture>riscv:rv32</architecture>\n";
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else if(iss::arch::traits<ARCH>::XLEN == 64)
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oss << " <architectureriscv:rv64</architecture>\n";
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oss << " <feature name=\"org.gnu.gdb.riscv.cpu\">\n";
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auto reg_base_num = iss::arch::traits<ARCH>::X0;
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for(auto i = 0U; i < iss::arch::traits<ARCH>::RFS; ++i) {
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oss << " <reg name=\"x" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i]
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<< "\" type=\"int\" regnum=\"" << i << "\"/>\n";
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}
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oss << " <reg name=\"pc\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[iss::arch::traits<ARCH>::PC]
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<< "\" type=\"code_ptr\" regnum=\"" << 32U << "\"/>\n";
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oss << " </feature>\n";
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if(iss::arch::traits<ARCH>::FLEN > 0) {
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oss << " <feature name=\"org.gnu.gdb.riscv.fpu\">\n";
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auto reg_base_num = get_f0_offset<ARCH>();
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auto type = iss::arch::traits<ARCH>::FLEN == 32 ? "ieee_single" : "riscv_double";
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for(auto i = 0U; i < 32; ++i) {
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oss << " <reg name=\"f" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i]
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<< "\" type=\"" << type << "\" regnum=\"" << i + 33 << "\"/>\n";
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}
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oss << " <reg name=\"fcsr\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"103\" type int/>\n";
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oss << " <reg name=\"fflags\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"101\" type int/>\n";
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oss << " <reg name=\"frm\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"102\" type int/>\n";
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oss << " </feature>\n";
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}
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oss << " <feature name=\"org.gnu.gdb.riscv.csr\">\n";
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std::vector<uint8_t> data;
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std::vector<uint8_t> avail;
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data.resize(sizeof(typename traits<ARCH>::reg_t));
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|
avail.resize(sizeof(typename traits<ARCH>::reg_t));
|
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for(auto i = 0U; i < 4096; ++i) {
|
|
typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, i);
|
|
std::fill(avail.begin(), avail.end(), 0xff);
|
|
auto res = core->read(a, data.size(), data.data());
|
|
if(res == iss::Ok) {
|
|
oss << " <reg name=\"" << get_csr_name(i) << "\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN
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<< "\" type=\"int\" regnum=\"" << (i + csr_offset) << "\"/>\n";
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|
}
|
|
}
|
|
oss << " </feature>\n";
|
|
oss << "</target>\n";
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}
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|
out_buf = csr_xml;
|
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return Ok;
|
|
}
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} // namespace debugger
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} // namespace iss
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#endif /* _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */
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