DBT-RISE
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DBT-RISE-TGC
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125 Commits

Author SHA1 Message Date
Eyck-Alexander Jentzsch 1720bd4aaa adds support for compressed instructions 2022-05-20 15:17:58 +02:00
Eyck Jentzsch df16378605 update template for changed code generator 2022-05-18 19:10:34 +02:00
Eyck Jentzsch 1438f0f373 add backannotation to pc trace plugin 2022-05-17 15:29:04 +02:00
Eyck Jentzsch 766f3ba9ee fix assertion in compressed pctrace writer 2022-05-13 12:38:12 +02:00
Eyck Jentzsch e382217e04 update vm_tgc_c due reworked CoreDSL generator 2022-05-11 18:52:15 +02:00
Eyck Jentzsch 9db4e3fd87 fix assertion 2022-05-10 16:13:21 +02:00
Eyck-Alexander Jentzsch bb658be3b4 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2022-05-08 15:25:56 +02:00
Eyck-Alexander Jentzsch 6579780dc9 add call column in output 2022-05-08 15:24:26 +02:00
Eyck Jentzsch e56bc12788 fix non-lz4 build of plugin 2022-05-07 17:27:11 +02:00
Eyck Jentzsch e88f309ea2 add lz4 compression to pctrace 2022-05-07 17:22:06 +02:00
Eyck Jentzsch 03bec27376 implement extended instrumentation interface 2022-04-26 17:14:33 +02:00
Eyck Jentzsch 9d9008a3a2 fix pointer mess 2022-04-26 15:35:17 +02:00
Stanislaw Kaushanski 5f6d462973 check that no interrupts are pending before entering the wfi wait 2022-04-26 13:58:20 +02:00
Eyck Jentzsch a92b84bef4 add code word access for ISS plugins 2022-04-25 14:18:19 +02:00
Eyck Jentzsch c054d75717 update to latest coredsl description 2022-04-10 18:55:44 +02:00
Eyck Jentzsch 8e4e702cb9 Merge remote-tracking branch 'origin/feature/reduced_output' into develop 2022-03-28 14:09:06 +02:00
Eyck-Alexander Jentzsch 58311b37db Merge branch 'feature/reduced_output' of 
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into
feature/reduced_output
 2022-03-28 11:16:09 +02:00
Eyck Jentzsch b0cb997009 add TGC_X with DMR 2022-03-26 10:48:21 +01:00
Eyck Jentzsch 30ae743361 add pctrace plugin to iss 2022-03-20 17:41:54 +01:00
Eyck Jentzsch d91f5f9df4 fix compiler warning for reduced number of registers 2022-03-14 15:38:05 +01:00
Eyck Jentzsch 2e670c4d03 change interpreter structure 2022-03-06 15:11:38 +01:00
Eyck Jentzsch 521f40a3d6 refactored interpreter backend structure 2022-03-05 20:59:17 +01:00
Eyck-Alexander Jentzsch 2bba5645c3 adds functionality to reduce the output 2022-02-16 10:13:29 +01:00
Eyck-Alexander Jentzsch 4c363f4073 adds additional functionality by fetching delay information 2022-02-11 11:28:00 +01:00
Eyck Jentzsch ac86f14a54 add tgc_c_xrb_nn to tgc-sim 2022-02-02 21:33:42 +01:00
Eyck Jentzsch 09b0f0d0c8 fix cycle estimation plugin 2022-02-01 21:14:50 +01:00
Eyck Jentzsch 98b418ff43 fix JSON reading 2022-02-01 19:28:11 +01:00
Eyck Jentzsch 059bd0d371 rework cycle estimation 2022-02-01 19:03:45 +01:00
Eyck-Alexander Jentzsch 7578906310 adds coverage plugin 2022-01-31 21:38:18 +01:00
Eyck Jentzsch afe8905ac9 fix else-ambiguity in CoreDSL description 2022-01-31 20:30:46 +01:00
Eyck-Alexander Jentzsch ecc6091d1e cleans up source code to remove clang compiler warnings 2022-01-19 08:01:15 +01:00
Eyck Jentzsch 07d5af1dde fix stand-alone ISS compilation to include all generated cores 2021-11-26 17:56:40 +01:00
Eyck Jentzsch 6f8595759e make tgc-sim include all available ISS 2021-11-25 20:00:27 +01:00
Eyck Jentzsch f90c48e881 adapt to changed define names 2021-11-11 08:33:35 +01:00
Eyck Jentzsch c42e336509 fix proper debug mode handling (#267 & #268) 2021-11-07 17:48:44 +01:00
Stanislaw Kaushanski a89f00da19 fix plugins parameter utilization 2021-11-02 11:03:17 +01:00
Eyck Jentzsch 1616f0ac90 remove deprecated functions 2021-10-30 12:57:08 +02:00
Eyck Jentzsch 334d3fb296 adapt to SCC changes 2021-10-21 22:53:16 +02:00
Eyck Jentzsch eb2ca33e5a remove unused sources 2021-10-12 15:17:56 +02:00
Eyck Jentzsch 0ea4cba1ca add dynamic plugin loading 2021-10-12 14:24:55 +02:00
Eyck Jentzsch 1d13c8196e fix wrong PGMASK usage 2021-10-11 10:40:01 +02:00
Eyck Jentzsch ee6e1d4092 Merge remote-tracking branch 'origin/msvc_compat' into develop 
Conflicts:
	src/sysc/core_complex.cpp
 2021-10-11 09:42:40 +02:00
Eyck Jentzsch c8679fca85 remove MSVC warning 2021-10-10 19:56:33 +02:00
Eyck Jentzsch f0ada1ba8c add MSVC 16 compatibility 2021-10-10 19:06:41 +02:00
Eyck Jentzsch 2f15d9676e fix unaligned instr fetch behavior 2021-09-30 19:27:46 +02:00
Eyck Jentzsch 17ee7b138d update generated TGC-C VM 2021-09-29 00:44:17 +02:00
Eyck Jentzsch 438e598a4a remove clutter from core descriptions, added instr alignment setting 2021-09-29 00:03:11 +02:00
Eyck Jentzsch 174259155d add support for non-compressed ISA 2021-09-23 21:09:52 +02:00
Eyck Jentzsch 65b4db5eca remove mcounteren in M-mode only platform 2021-09-18 11:40:00 +02:00
Eyck Jentzsch 0fd82f1f3c add tgc_d_xrb_mac to SC and C++ ISS 2021-09-04 13:04:34 +02:00