DBT-RISE/DBT-RISE-TGC
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adapt to SCC changes

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This commit is contained in:
Eyck Jentzsch
2021-10-17 12:25:13 +02:00
parent eb2ca33e5a
commit 334d3fb296
3 changed files with 17 additions and 8 deletions
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18
src/vm/interp/vm_tgc_c.cpp
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@ -30,21 +30,23 @@
*
*******************************************************************************/
// clang-format off
#include "../fp_functions.h"
#include <iss/arch/tgc_c.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
#include <iss/arch/tgc_c.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/interp/vm_base.h>
#include "../fp_functions.h"
#include <util/logging.h>
#include <sstream>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
#include <fmt/format.h>
#include <array>
#include <iss/debugger/riscv_target_adapter.h>
// clang-format on
namespace iss {
namespace interp {
@ -90,7 +92,10 @@ protected:
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
enum {
LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)),
LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16))
};
std::array<compile_func, LUT_SIZE> lut;
@ -4098,6 +4103,7 @@ private:
return pc;
}
//static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
auto phys_pc = this->core.v2p(pc);
//if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary