adds missing ehrenberg devices

updates ehrenberg devices and BSP
update include path
2024-06-10 12:21:20 +02:00 · 2024-06-10 10:13:07 +02:00 · 2024-05-31 09:21:57 +02:00 · 2024-05-31 08:58:05 +02:00 · 2024-05-31 08:56:21 +02:00 · 2024-05-30 18:33:53 +02:00
42 changed files with 2165 additions and 648 deletions
--- a/.gitignore
+++ b/.gitignore
@ -151,3 +151,4 @@ compile_commands.json
 CTestTestfile.cmake
 *.dump

+/doc/
--- a/env/common-gcc.mk
+++ b/env/common-gcc.mk
@ -4,7 +4,7 @@ _MK_COMMON := # defined
 TL_TARGET?=all

 .PHONY: $(TL_TARGET)
-$(TL_TARGET): $(TARGET)
+$(TL_TARGET): $(TARGET).elf

 ENV_DIR:=$(dir $(lastword $(MAKEFILE_LIST)))
 BSP_BASE=$(ENV_DIR)/..
@ -63,8 +63,7 @@ OBJDUMP := $(TOOL_DIR)$(TRIPLET)-objdump
 OBJCOPY := $(TOOL_DIR)$(TRIPLET)-objcopy

 ifndef NO_DEFAULT_LINK
-$(TARGET): $(LINK_OBJS) $(LINK_DEPS)
-	echo LINK_OBJS: $(LINK_OBJS)
+$(TARGET).elf: $(LINK_OBJS) $(LINK_DEPS)
 	$(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP_LDFLAGS) $(LIBWRAP) $(LD_SCRIPT) -o $@
 	$(OBJDUMP) -d -S $@ > $(TARGET).dis
 endif
--- a/env/ehrenberg/platform.h
+++ b/env/ehrenberg/platform.h
@ -17,8 +17,10 @@
 #include "ehrenberg/devices/uart.h"
 #include "ehrenberg/devices/timer.h"
 #include "ehrenberg/devices/aclint.h"
-#include "ehrenberg/devices/interrupt.h"
 #include "ehrenberg/devices/qspi.h"
+#include "ehrenberg/devices/i2s.h"
+#include "ehrenberg/devices/camera.h"
+#include "ehrenberg/devices/dma.h"

 #define PERIPH(TYPE, ADDR) ((volatile TYPE*) (ADDR))

@ -30,6 +32,10 @@
 #define aclint      PERIPH(aclint_t,    APB_BASE+0x30000)
 #define irq         PERIPH(irq_t,       APB_BASE+0x40000)
 #define qspi        PERIPH(qspi_t,      APB_BASE+0x50000)
+#define i2s         PERIPH(i2s_t,       APB_BASE+0x90000)
+#define camera      PERIPH(camera_t,    APB_BASE+0xA0000)
+#define sdma        PERIPH(simpledma_t, APB_BASE+0xB0000)
+

 #define XIP_START_LOC 0xE0040000

--- a/env/ehrenberg/rom.lds
+++ b/env/ehrenberg/rom.lds
@ -0,0 +1,170 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 1k
+  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32k
+}
+
+PHDRS
+{
+  rom PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+  .init ORIGIN(rom)        :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >rom AT>rom :rom
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >rom AT>rom :rom
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >rom AT>rom :rom
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >rom AT>rom :rom
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >rom AT>rom :rom
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >rom AT>rom :rom
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >rom AT>rom :rom
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >rom AT>rom :rom
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >rom AT>rom :rom
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >rom AT>rom :rom
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>rom :ram_init
+
+  .data          :
+  {
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+  } >ram AT>rom :ram_init
+
+  .srodata        :
+  {
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>rom :ram_init
+
+  .sdata          :
+  {
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>rom :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+
+  PROVIDE( tohost = 0xfffffff0 );
+  PROVIDE( fromhost = 0xfffffff8 );
+}
--- a/env/start.S
+++ b/env/start.S
@ -37,11 +37,11 @@ _start:
 2:

 	/* Call global constructors */
-//#ifdef HAVE_INIT_FINI
+#ifndef HAVE_NO_INIT_FINI
 	la a0, __libc_fini_array
 	call atexit
 	call __libc_init_array
-//#endif
+#endif
 #ifndef __riscv_float_abi_soft
 	/* Enable FPU */
 	li t0, MSTATUS_FS
--- a/include/ehrenberg/devices/aclint.h
+++ b/include/ehrenberg/devices/aclint.h
@ -1,10 +1,9 @@
-#ifndef _BSP_ACLINT_H
-#define _BSP_ACLINT_H
+#ifndef _DEVICES_ACLINT_H
+#define _DEVICES_ACLINT_H

 #include <stdint.h>
-#include "gen/Apb3AClint.h"
+#include "gen/aclint.h"

-#define aclint_t apb3aclint_t

 static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value){
    set_aclint_mtime_hi(reg, (uint32_t)(value >> 32));
@ -26,4 +25,4 @@ static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg){
    return value;
 }

-#endif /* _BSP_ACLINT_H */
+#endif /* _DEVICES_ACLINT_H */
--- a/include/ehrenberg/devices/camera.h
+++ b/include/ehrenberg/devices/camera.h
@ -0,0 +1,6 @@
+#ifndef _BSP_CAM_H
+#define _BSP_CAM_H
+
+#include "gen/camera.h"
+
+#endif /* _BSP_CAM_H */
--- a/include/ehrenberg/devices/dma.h
+++ b/include/ehrenberg/devices/dma.h
@ -0,0 +1,6 @@
+#ifndef _BSP_DMA_H
+#define _BSP_DMA_H
+
+#include "gen/simpledma.h"
+
+#endif /* _BSP_DMA_H */
--- a/include/ehrenberg/devices/gen/Apb3AClint.h
+++ b/include/ehrenberg/devices/gen/Apb3AClint.h
@ -1,53 +0,0 @@
-/*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Generated at 2024-02-19 14:24:37 UTC 
-* by peakrdl_mnrs version 1.2.2
-*/
-
-#ifndef _BSP_APB3ACLINT_H
-#define _BSP_APB3ACLINT_H
-
-#include <stdint.h>
-
-typedef struct __attribute((__packed__)) {
-    volatile uint32_t MSIP0;
-    volatile uint32_t MTIMECMP0LO;
-    volatile uint32_t MTIMECMP0HI;
-    volatile uint32_t MTIME_LO;
-    volatile uint32_t MTIME_HI;
-}apb3aclint_t;
-
-inline uint32_t get_aclint_msip0(volatile apb3aclint_t *reg){
-    return (reg->MSIP0 >> 0) & 0x1;
-}
-inline void set_aclint_msip0(volatile apb3aclint_t *reg, uint8_t value){
-    reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
-}
-inline uint32_t get_aclint_mtimecmp0lo(volatile apb3aclint_t *reg){
-    return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
-}
-inline void set_aclint_mtimecmp0lo(volatile apb3aclint_t *reg, uint32_t value){
-    reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
-}
-inline uint32_t get_aclint_mtimecmp0hi(volatile apb3aclint_t *reg){
-    return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
-}
-inline void set_aclint_mtimecmp0hi(volatile apb3aclint_t *reg, uint32_t value){
-    reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
-}
-inline uint32_t get_aclint_mtime_lo(volatile apb3aclint_t *reg){
-    return (reg->MTIME_LO >> 0) & 0xffffffff;
-}
-inline void set_aclint_mtime_lo(volatile apb3aclint_t *reg, uint32_t value){
-    reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
-}
-inline uint32_t get_aclint_mtime_hi(volatile apb3aclint_t *reg){
-    return (reg->MTIME_HI >> 0) & 0xffffffff;
-}
-inline void set_aclint_mtime_hi(volatile apb3aclint_t *reg, uint32_t value){
-    reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
-}
-#endif /* _BSP_APB3ACLINT_H */
--- a/include/ehrenberg/devices/gen/Apb3Gpio.h
+++ b/include/ehrenberg/devices/gen/Apb3Gpio.h
@ -1,36 +0,0 @@
-/*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Generated at 2024-02-19 14:24:37 UTC 
-* by peakrdl_mnrs version 1.2.2
-*/
-
-#ifndef _BSP_APB3GPIO_H
-#define _BSP_APB3GPIO_H
-
-#include <stdint.h>
-
-typedef struct __attribute((__packed__)) {
-    volatile uint32_t VALUE;
-    volatile uint32_t WRITE;
-    volatile uint32_t WRITEENABLE;
-}apb3gpio_t;
-
-inline uint32_t get_gpio_value(volatile apb3gpio_t *reg){
-    return (reg->VALUE >> 0) & 0xffffffff;
-}
-inline uint32_t get_gpio_write(volatile apb3gpio_t *reg){
-    return (reg->WRITE >> 0) & 0xffffffff;
-}
-inline void set_gpio_write(volatile apb3gpio_t *reg, uint32_t value){
-    reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
-}
-inline uint32_t get_gpio_writeEnable(volatile apb3gpio_t *reg){
-    return (reg->WRITEENABLE >> 0) & 0xffffffff;
-}
-inline void set_gpio_writeEnable(volatile apb3gpio_t *reg, uint32_t value){
-    reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
-}
-#endif /* _BSP_APB3GPIO_H */
--- a/include/ehrenberg/devices/gen/Apb3IrqCtrl.h
+++ b/include/ehrenberg/devices/gen/Apb3IrqCtrl.h
@ -1,32 +0,0 @@
-/*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Generated at 2024-02-19 14:24:37 UTC 
-* by peakrdl_mnrs version 1.2.2
-*/
-
-#ifndef _BSP_APB3IRQCTRL_H
-#define _BSP_APB3IRQCTRL_H
-
-#include <stdint.h>
-
-typedef struct __attribute((__packed__)) {
-    volatile uint32_t PENDINGSREG;
-    volatile uint32_t MASKSREG;
-}apb3irqctrl_t;
-
-inline uint32_t get_irq_pendingsReg(volatile apb3irqctrl_t *reg){
-    return (reg->PENDINGSREG >> 0) & 0xf;
-}
-inline void set_irq_pendingsReg(volatile apb3irqctrl_t *reg, uint8_t value){
-    reg->PENDINGSREG = (reg->PENDINGSREG & ~(0xfU << 0)) | (value << 0);
-}
-inline uint32_t get_irq_masksReg(volatile apb3irqctrl_t *reg){
-    return (reg->MASKSREG >> 0) & 0xf;
-}
-inline void set_irq_masksReg(volatile apb3irqctrl_t *reg, uint8_t value){
-    reg->MASKSREG = (reg->MASKSREG & ~(0xfU << 0)) | (value << 0);
-}
-#endif /* _BSP_APB3IRQCTRL_H */
--- a/include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h
+++ b/include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h
@ -1,214 +0,0 @@
-/*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Generated at 2024-02-19 14:24:37 UTC 
-* by peakrdl_mnrs version 1.2.2
-*/
-
-#ifndef _BSP_APB3SPIXDRMASTERCTRL_H
-#define _BSP_APB3SPIXDRMASTERCTRL_H
-
-#include <stdint.h>
-
-typedef struct __attribute((__packed__)) {
-    volatile uint32_t DATA;
-    volatile uint32_t STATUS;
-    volatile uint32_t CONFIG;
-    volatile uint32_t INTR;
-    uint32_t fill0[4];
-    volatile uint32_t SCLK_CONFIG;
-    volatile uint32_t SSGEN_SETUP;
-    volatile uint32_t SSGEN_HOLD;
-    volatile uint32_t SSGEN_DISABLE;
-    volatile uint32_t SSGEN_ACTIVE_HIGH;
-    uint32_t fill1[3];
-    volatile uint32_t XIP_ENABLE;
-    volatile uint32_t XIP_CONFIG;
-    volatile uint32_t XIP_MODE;
-    uint32_t fill2[1];
-    volatile uint32_t XIP_WRITE;
-    volatile uint32_t XIP_READ_WRITE;
-    volatile uint32_t XIP_READ;
-}apb3spixdrmasterctrl_t;
-
-#define SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
-#define SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
-#define SPI_XIP_CONFIG_INSTRUCTION(V) ((V & SPI_XIP_CONFIG_INSTRUCTION_MASK) << SPI_XIP_CONFIG_INSTRUCTION_OFFS)
-
-#define SPI_XIP_CONFIG_ENABLE_OFFS 8
-#define SPI_XIP_CONFIG_ENABLE_MASK 1
-#define SPI_XIP_CONFIG_ENABLE(V) ((V & SPI_XIP_CONFIG_ENABLE_MASK) << SPI_XIP_CONFIG_ENABLE_OFFS)
-
-#define SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
-#define SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
-#define SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
-
-#define SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
-#define SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
-#define SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
-
-inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_data_write(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->DATA >> 8) & 0x1;
-}
-inline void set_spi_data_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
-}
-inline uint32_t get_spi_data_read(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->DATA >> 9) & 0x1;
-}
-inline void set_spi_data_read(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
-}
-inline uint32_t get_spi_data_kind(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->DATA >> 11) & 0x1;
-}
-inline void set_spi_data_kind(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
-}
-inline uint32_t get_spi_data_rx_data_invalid(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->DATA >> 31) & 0x1;
-}
-inline uint32_t get_spi_status_tx_free(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->STATUS >> 0) & 0x3f;
-}
-inline uint32_t get_spi_status_rx_avail(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->STATUS >> 16) & 0x3f;
-}
-inline uint32_t get_spi_config_kind(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->CONFIG >> 0) & 0x3;
-}
-inline void set_spi_config_kind(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
-}
-inline uint32_t get_spi_config_mode(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->CONFIG >> 4) & 0x7;
-}
-inline void set_spi_config_mode(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x7U << 4)) | (value << 4);
-}
-inline uint32_t get_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->INTR >> 0) & 0x1;
-}
-inline void set_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
-}
-inline uint32_t get_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->INTR >> 1) & 0x1;
-}
-inline void set_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
-}
-inline uint32_t get_spi_intr_tx_ip(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->INTR >> 8) & 0x1;
-}
-inline uint32_t get_spi_intr_rx_ip(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->INTR >> 9) & 0x1;
-}
-inline uint32_t get_spi_intr_tx_active(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->INTR >> 16) & 0x1;
-}
-inline uint32_t get_spi_sclk_config(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->SCLK_CONFIG >> 0) & 0xfff;
-}
-inline void set_spi_sclk_config(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
-    reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->SSGEN_SETUP >> 0) & 0xfff;
-}
-inline void set_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
-    reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->SSGEN_HOLD >> 0) & 0xfff;
-}
-inline void set_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
-    reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->SSGEN_DISABLE >> 0) & 0xfff;
-}
-inline void set_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
-    reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
-}
-inline void set_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
-}
-inline uint32_t get_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_ENABLE >> 0) & 0x1;
-}
-inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
-}
-inline uint32_t get_spi_xip_config(volatile apb3spixdrmasterctrl_t *reg){
-    return reg->XIP_CONFIG;
-}
-inline void set_spi_xip_config(volatile apb3spixdrmasterctrl_t *reg, uint32_t value){
-    reg->XIP_CONFIG = value;
-}
-inline uint32_t get_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_CONFIG >> 0) & 0xff;
-}
-inline void set_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_CONFIG >> 8) & 0x1;
-}
-inline void set_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
-}
-inline uint32_t get_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_CONFIG >> 16) & 0xff;
-}
-inline void set_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
-}
-inline uint32_t get_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_CONFIG >> 24) & 0xf;
-}
-inline void set_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
-}
-inline uint32_t get_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_MODE >> 0) & 0x7;
-}
-inline void set_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 0)) | (value << 0);
-}
-inline uint32_t get_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_MODE >> 8) & 0x7;
-}
-inline void set_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 8)) | (value << 8);
-}
-inline uint32_t get_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_MODE >> 16) & 0x7;
-}
-inline void set_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 16)) | (value << 16);
-}
-inline uint32_t get_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_MODE >> 24) & 0x7;
-}
-inline void set_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 24)) | (value << 24);
-}
-inline void set_spi_xip_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
-}
-inline void set_spi_xip_read_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_READ >> 0) & 0xff;
-}
-#endif /* _BSP_APB3SPIXDRMASTERCTRL_H */
--- a/include/ehrenberg/devices/gen/Apb3Timer.h
+++ b/include/ehrenberg/devices/gen/Apb3Timer.h
@ -1,73 +0,0 @@
-/*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Generated at 2024-02-19 14:24:37 UTC 
-* by peakrdl_mnrs version 1.2.2
-*/
-
-#ifndef _BSP_APB3TIMER_H
-#define _BSP_APB3TIMER_H
-
-#include <stdint.h>
-
-typedef struct __attribute((__packed__)) {
-    volatile uint32_t PRESCALER;
-    volatile uint32_t T0_CTRL;
-    volatile uint32_t T0_OVERFLOW;
-    volatile uint32_t T0_VALUE;
-    volatile uint32_t T1_CTRL;
-    volatile uint32_t T1_OVERFLOW;
-    volatile uint32_t T1_VALUE;
-}apb3timer_t;
-
-inline uint32_t get_timer_prescaler(volatile apb3timer_t *reg){
-    return (reg->PRESCALER >> 0) & 0xffff;
-}
-inline void set_timer_prescaler(volatile apb3timer_t *reg, uint16_t value){
-    reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
-}
-inline uint32_t get_timer_t0_ctrl_enable(volatile apb3timer_t *reg){
-    return (reg->T0_CTRL >> 0) & 0x7;
-}
-inline void set_timer_t0_ctrl_enable(volatile apb3timer_t *reg, uint8_t value){
-    reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
-}
-inline uint32_t get_timer_t0_ctrl_clear(volatile apb3timer_t *reg){
-    return (reg->T0_CTRL >> 3) & 0x3;
-}
-inline void set_timer_t0_ctrl_clear(volatile apb3timer_t *reg, uint8_t value){
-    reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
-}
-inline uint32_t get_timer_t0_overflow(volatile apb3timer_t *reg){
-    return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
-}
-inline void set_timer_t0_overflow(volatile apb3timer_t *reg, uint32_t value){
-    reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
-}
-inline uint32_t get_timer_t0_value(volatile apb3timer_t *reg){
-    return (reg->T0_VALUE >> 0) & 0xffffffff;
-}
-inline uint32_t get_timer_t1_ctrl_enable(volatile apb3timer_t *reg){
-    return (reg->T1_CTRL >> 0) & 0x7;
-}
-inline void set_timer_t1_ctrl_enable(volatile apb3timer_t *reg, uint8_t value){
-    reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
-}
-inline uint32_t get_timer_t1_ctrl_clear(volatile apb3timer_t *reg){
-    return (reg->T1_CTRL >> 3) & 0x3;
-}
-inline void set_timer_t1_ctrl_clear(volatile apb3timer_t *reg, uint8_t value){
-    reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
-}
-inline uint32_t get_timer_t1_overflow(volatile apb3timer_t *reg){
-    return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
-}
-inline void set_timer_t1_overflow(volatile apb3timer_t *reg, uint32_t value){
-    reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
-}
-inline uint32_t get_timer_t1_value(volatile apb3timer_t *reg){
-    return (reg->T1_VALUE >> 0) & 0xffffffff;
-}
-#endif /* _BSP_APB3TIMER_H */
--- a/include/ehrenberg/devices/gen/Apb3Uart.h
+++ b/include/ehrenberg/devices/gen/Apb3Uart.h
@ -1,104 +0,0 @@
-/*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Generated at 2024-02-19 14:24:37 UTC 
-* by peakrdl_mnrs version 1.2.2
-*/
-
-#ifndef _BSP_APB3UART_H
-#define _BSP_APB3UART_H
-
-#include <stdint.h>
-
-typedef struct __attribute((__packed__)) {
-    volatile uint32_t RX_TX_REG;
-    volatile uint32_t INT_CTRL_REG;
-    volatile uint32_t CLK_DIVIDER_REG;
-    volatile uint32_t FRAME_CONFIG_REG;
-    volatile uint32_t STATUS_REG;
-}apb3uart_t;
-
-inline uint32_t get_uart_rx_tx_reg_data(volatile apb3uart_t *reg){
-    return (reg->RX_TX_REG >> 0) & 0xff;
-}
-inline void set_uart_rx_tx_reg_data(volatile apb3uart_t *reg, uint8_t value){
-    reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
-}
-inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile apb3uart_t *reg){
-    return (reg->RX_TX_REG >> 14) & 0x1;
-}
-inline uint32_t get_uart_rx_tx_reg_tx_free(volatile apb3uart_t *reg){
-    return (reg->RX_TX_REG >> 15) & 0x1;
-}
-inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t *reg){
-    return (reg->INT_CTRL_REG >> 0) & 0x1;
-}
-inline void set_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t *reg, uint8_t value){
-    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
-}
-inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t *reg){
-    return (reg->INT_CTRL_REG >> 1) & 0x1;
-}
-inline void set_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t *reg, uint8_t value){
-    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
-}
-inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile apb3uart_t *reg){
-    return (reg->INT_CTRL_REG >> 8) & 0x1;
-}
-inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile apb3uart_t *reg){
-    return (reg->INT_CTRL_REG >> 9) & 0x1;
-}
-inline uint32_t get_uart_clk_divider_reg(volatile apb3uart_t *reg){
-    return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
-}
-inline void set_uart_clk_divider_reg(volatile apb3uart_t *reg, uint32_t value){
-    reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
-}
-inline uint32_t get_uart_frame_config_reg_data_lenght(volatile apb3uart_t *reg){
-    return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
-}
-inline void set_uart_frame_config_reg_data_lenght(volatile apb3uart_t *reg, uint8_t value){
-    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
-}
-inline uint32_t get_uart_frame_config_reg_parity(volatile apb3uart_t *reg){
-    return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
-}
-inline void set_uart_frame_config_reg_parity(volatile apb3uart_t *reg, uint8_t value){
-    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
-}
-inline uint32_t get_uart_frame_config_reg_stop_bit(volatile apb3uart_t *reg){
-    return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
-}
-inline void set_uart_frame_config_reg_stop_bit(volatile apb3uart_t *reg, uint8_t value){
-    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
-}
-inline uint32_t get_uart_status_reg_read_error(volatile apb3uart_t *reg){
-    return (reg->STATUS_REG >> 0) & 0x1;
-}
-inline uint32_t get_uart_status_reg_stall(volatile apb3uart_t *reg){
-    return (reg->STATUS_REG >> 1) & 0x1;
-}
-inline uint32_t get_uart_status_reg_break(volatile apb3uart_t *reg){
-    return (reg->STATUS_REG >> 8) & 0x1;
-}
-inline uint32_t get_uart_status_reg_break_detected(volatile apb3uart_t *reg){
-    return (reg->STATUS_REG >> 9) & 0x1;
-}
-inline void set_uart_status_reg_break_detected(volatile apb3uart_t *reg, uint8_t value){
-    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
-}
-inline uint32_t get_uart_status_reg_set_break(volatile apb3uart_t *reg){
-    return (reg->STATUS_REG >> 10) & 0x1;
-}
-inline void set_uart_status_reg_set_break(volatile apb3uart_t *reg, uint8_t value){
-    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
-}
-inline uint32_t get_uart_status_reg_clear_break(volatile apb3uart_t *reg){
-    return (reg->STATUS_REG >> 11) & 0x1;
-}
-inline void set_uart_status_reg_clear_break(volatile apb3uart_t *reg, uint8_t value){
-    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
-}
-#endif /* _BSP_APB3UART_H */
--- a/include/ehrenberg/devices/gen/aclint.h
+++ b/include/ehrenberg/devices/gen/aclint.h
@ -0,0 +1,85 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-06-08 13:20:02 UTC 
+* by peakrdl_mnrs version 1.2.5
+*/
+
+#ifndef _BSP_ACLINT_H
+#define _BSP_ACLINT_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t MSIP0;
+    uint8_t fill0[16380];
+    volatile uint32_t MTIMECMP0LO;
+    volatile uint32_t MTIMECMP0HI;
+    uint8_t fill1[32752];
+    volatile uint32_t MTIME_LO;
+    volatile uint32_t MTIME_HI;
+}aclint_t;
+
+#define ACLINT_MSIP0_OFFS 0
+#define ACLINT_MSIP0_MASK 0x1
+#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
+
+#define ACLINT_MTIMECMP0LO_OFFS 0
+#define ACLINT_MTIMECMP0LO_MASK 0xffffffff
+#define ACLINT_MTIMECMP0LO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
+
+#define ACLINT_MTIMECMP0HI_OFFS 0
+#define ACLINT_MTIMECMP0HI_MASK 0xffffffff
+#define ACLINT_MTIMECMP0HI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
+
+#define ACLINT_MTIME_LO_OFFS 0
+#define ACLINT_MTIME_LO_MASK 0xffffffff
+#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
+
+#define ACLINT_MTIME_HI_OFFS 0
+#define ACLINT_MTIME_HI_MASK 0xffffffff
+#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
+
+//ACLINT_MSIP0
+inline uint32_t get_aclint_msip0(volatile aclint_t* reg){
+    return (reg->MSIP0 >> 0) & 0x1;
+}
+inline void set_aclint_msip0(volatile aclint_t* reg, uint8_t value){
+    reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
+}
+
+//ACLINT_MTIMECMP0LO
+inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg){
+    return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value){
+    reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//ACLINT_MTIMECMP0HI
+inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg){
+    return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value){
+    reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//ACLINT_MTIME_LO
+inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg){
+    return (reg->MTIME_LO >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value){
+    reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//ACLINT_MTIME_HI
+inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg){
+    return (reg->MTIME_HI >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value){
+    reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_ACLINT_H */
--- a/include/ehrenberg/devices/gen/apb3spi.h
+++ b/include/ehrenberg/devices/gen/apb3spi.h
@ -0,0 +1,382 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-06-08 13:20:02 UTC 
+* by peakrdl_mnrs version 1.2.5
+*/
+
+#ifndef _BSP_APB3SPI_H
+#define _BSP_APB3SPI_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t DATA;
+    volatile uint32_t STATUS;
+    volatile uint32_t CONFIG;
+    volatile uint32_t INTR;
+    uint8_t fill0[16];
+    volatile uint32_t SCLK_CONFIG;
+    volatile uint32_t SSGEN_SETUP;
+    volatile uint32_t SSGEN_HOLD;
+    volatile uint32_t SSGEN_DISABLE;
+    volatile uint32_t SSGEN_ACTIVE_HIGH;
+    uint8_t fill1[12];
+    volatile uint32_t XIP_ENABLE;
+    volatile uint32_t XIP_CONFIG;
+    volatile uint32_t XIP_MODE;
+    uint8_t fill2[4];
+    volatile uint32_t XIP_WRITE;
+    volatile uint32_t XIP_READ_WRITE;
+    volatile uint32_t XIP_READ;
+}apb3spi_t;
+
+#define APB3SPI_DATA_DATA_OFFS 0
+#define APB3SPI_DATA_DATA_MASK 0xff
+#define APB3SPI_DATA_DATA(V) ((V & APB3SPI_DATA_DATA_MASK) << APB3SPI_DATA_DATA_OFFS)
+
+#define APB3SPI_DATA_WRITE_OFFS 8
+#define APB3SPI_DATA_WRITE_MASK 0x1
+#define APB3SPI_DATA_WRITE(V) ((V & APB3SPI_DATA_WRITE_MASK) << APB3SPI_DATA_WRITE_OFFS)
+
+#define APB3SPI_DATA_READ_OFFS 9
+#define APB3SPI_DATA_READ_MASK 0x1
+#define APB3SPI_DATA_READ(V) ((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS)
+
+#define APB3SPI_DATA_KIND_OFFS 11
+#define APB3SPI_DATA_KIND_MASK 0x1
+#define APB3SPI_DATA_KIND(V) ((V & APB3SPI_DATA_KIND_MASK) << APB3SPI_DATA_KIND_OFFS)
+
+#define APB3SPI_DATA_RX_DATA_INVALID_OFFS 31
+#define APB3SPI_DATA_RX_DATA_INVALID_MASK 0x1
+#define APB3SPI_DATA_RX_DATA_INVALID(V) ((V & APB3SPI_DATA_RX_DATA_INVALID_MASK) << APB3SPI_DATA_RX_DATA_INVALID_OFFS)
+
+#define APB3SPI_STATUS_TX_FREE_OFFS 0
+#define APB3SPI_STATUS_TX_FREE_MASK 0x3f
+#define APB3SPI_STATUS_TX_FREE(V) ((V & APB3SPI_STATUS_TX_FREE_MASK) << APB3SPI_STATUS_TX_FREE_OFFS)
+
+#define APB3SPI_STATUS_RX_AVAIL_OFFS 16
+#define APB3SPI_STATUS_RX_AVAIL_MASK 0x3f
+#define APB3SPI_STATUS_RX_AVAIL(V) ((V & APB3SPI_STATUS_RX_AVAIL_MASK) << APB3SPI_STATUS_RX_AVAIL_OFFS)
+
+#define APB3SPI_CONFIG_KIND_OFFS 0
+#define APB3SPI_CONFIG_KIND_MASK 0x3
+#define APB3SPI_CONFIG_KIND(V) ((V & APB3SPI_CONFIG_KIND_MASK) << APB3SPI_CONFIG_KIND_OFFS)
+
+#define APB3SPI_CONFIG_MODE_OFFS 4
+#define APB3SPI_CONFIG_MODE_MASK 0x3
+#define APB3SPI_CONFIG_MODE(V) ((V & APB3SPI_CONFIG_MODE_MASK) << APB3SPI_CONFIG_MODE_OFFS)
+
+#define APB3SPI_INTR_TX_IE_OFFS 0
+#define APB3SPI_INTR_TX_IE_MASK 0x1
+#define APB3SPI_INTR_TX_IE(V) ((V & APB3SPI_INTR_TX_IE_MASK) << APB3SPI_INTR_TX_IE_OFFS)
+
+#define APB3SPI_INTR_RX_IE_OFFS 1
+#define APB3SPI_INTR_RX_IE_MASK 0x1
+#define APB3SPI_INTR_RX_IE(V) ((V & APB3SPI_INTR_RX_IE_MASK) << APB3SPI_INTR_RX_IE_OFFS)
+
+#define APB3SPI_INTR_TX_IP_OFFS 8
+#define APB3SPI_INTR_TX_IP_MASK 0x1
+#define APB3SPI_INTR_TX_IP(V) ((V & APB3SPI_INTR_TX_IP_MASK) << APB3SPI_INTR_TX_IP_OFFS)
+
+#define APB3SPI_INTR_RX_IP_OFFS 9
+#define APB3SPI_INTR_RX_IP_MASK 0x1
+#define APB3SPI_INTR_RX_IP(V) ((V & APB3SPI_INTR_RX_IP_MASK) << APB3SPI_INTR_RX_IP_OFFS)
+
+#define APB3SPI_INTR_TX_ACTIVE_OFFS 16
+#define APB3SPI_INTR_TX_ACTIVE_MASK 0x1
+#define APB3SPI_INTR_TX_ACTIVE(V) ((V & APB3SPI_INTR_TX_ACTIVE_MASK) << APB3SPI_INTR_TX_ACTIVE_OFFS)
+
+#define APB3SPI_SCLK_CONFIG_OFFS 0
+#define APB3SPI_SCLK_CONFIG_MASK 0xfff
+#define APB3SPI_SCLK_CONFIG(V) ((V & APB3SPI_SCLK_CONFIG_MASK) << APB3SPI_SCLK_CONFIG_OFFS)
+
+#define APB3SPI_SSGEN_SETUP_OFFS 0
+#define APB3SPI_SSGEN_SETUP_MASK 0xfff
+#define APB3SPI_SSGEN_SETUP(V) ((V & APB3SPI_SSGEN_SETUP_MASK) << APB3SPI_SSGEN_SETUP_OFFS)
+
+#define APB3SPI_SSGEN_HOLD_OFFS 0
+#define APB3SPI_SSGEN_HOLD_MASK 0xfff
+#define APB3SPI_SSGEN_HOLD(V) ((V & APB3SPI_SSGEN_HOLD_MASK) << APB3SPI_SSGEN_HOLD_OFFS)
+
+#define APB3SPI_SSGEN_DISABLE_OFFS 0
+#define APB3SPI_SSGEN_DISABLE_MASK 0xfff
+#define APB3SPI_SSGEN_DISABLE(V) ((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS)
+
+#define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0
+#define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
+#define APB3SPI_SSGEN_ACTIVE_HIGH(V) ((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS)
+
+#define APB3SPI_XIP_ENABLE_OFFS 0
+#define APB3SPI_XIP_ENABLE_MASK 0x1
+#define APB3SPI_XIP_ENABLE(V) ((V & APB3SPI_XIP_ENABLE_MASK) << APB3SPI_XIP_ENABLE_OFFS)
+
+#define APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
+#define APB3SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
+#define APB3SPI_XIP_CONFIG_INSTRUCTION(V) ((V & APB3SPI_XIP_CONFIG_INSTRUCTION_MASK) << APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS)
+
+#define APB3SPI_XIP_CONFIG_ENABLE_OFFS 8
+#define APB3SPI_XIP_CONFIG_ENABLE_MASK 0x1
+#define APB3SPI_XIP_CONFIG_ENABLE(V) ((V & APB3SPI_XIP_CONFIG_ENABLE_MASK) << APB3SPI_XIP_CONFIG_ENABLE_OFFS)
+
+#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
+#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
+#define APB3SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
+
+#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
+#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
+#define APB3SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
+
+#define APB3SPI_XIP_MODE_INSTRUCTION_OFFS 0
+#define APB3SPI_XIP_MODE_INSTRUCTION_MASK 0x3
+#define APB3SPI_XIP_MODE_INSTRUCTION(V) ((V & APB3SPI_XIP_MODE_INSTRUCTION_MASK) << APB3SPI_XIP_MODE_INSTRUCTION_OFFS)
+
+#define APB3SPI_XIP_MODE_ADDRESS_OFFS 8
+#define APB3SPI_XIP_MODE_ADDRESS_MASK 0x3
+#define APB3SPI_XIP_MODE_ADDRESS(V) ((V & APB3SPI_XIP_MODE_ADDRESS_MASK) << APB3SPI_XIP_MODE_ADDRESS_OFFS)
+
+#define APB3SPI_XIP_MODE_DUMMY_OFFS 16
+#define APB3SPI_XIP_MODE_DUMMY_MASK 0x3
+#define APB3SPI_XIP_MODE_DUMMY(V) ((V & APB3SPI_XIP_MODE_DUMMY_MASK) << APB3SPI_XIP_MODE_DUMMY_OFFS)
+
+#define APB3SPI_XIP_MODE_PAYLOAD_OFFS 24
+#define APB3SPI_XIP_MODE_PAYLOAD_MASK 0x3
+#define APB3SPI_XIP_MODE_PAYLOAD(V) ((V & APB3SPI_XIP_MODE_PAYLOAD_MASK) << APB3SPI_XIP_MODE_PAYLOAD_OFFS)
+
+#define APB3SPI_XIP_WRITE_OFFS 0
+#define APB3SPI_XIP_WRITE_MASK 0xff
+#define APB3SPI_XIP_WRITE(V) ((V & APB3SPI_XIP_WRITE_MASK) << APB3SPI_XIP_WRITE_OFFS)
+
+#define APB3SPI_XIP_READ_WRITE_OFFS 0
+#define APB3SPI_XIP_READ_WRITE_MASK 0xff
+#define APB3SPI_XIP_READ_WRITE(V) ((V & APB3SPI_XIP_READ_WRITE_MASK) << APB3SPI_XIP_READ_WRITE_OFFS)
+
+#define APB3SPI_XIP_READ_OFFS 0
+#define APB3SPI_XIP_READ_MASK 0xff
+#define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS)
+
+//APB3SPI_DATA
+inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg){
+     return reg->DATA;
+}
+inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value){
+     reg->DATA = value;
+}
+inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg){
+    return (reg->DATA >> 8) & 0x1;
+}
+inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
+}
+inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg){
+    return (reg->DATA >> 9) & 0x1;
+}
+inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
+}
+inline uint32_t get_apb3spi_data_kind(volatile apb3spi_t* reg){
+    return (reg->DATA >> 11) & 0x1;
+}
+inline void set_apb3spi_data_kind(volatile apb3spi_t* reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
+}
+inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg){
+    return (reg->DATA >> 31) & 0x1;
+}
+
+//APB3SPI_STATUS
+inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg){
+     return reg->STATUS;
+}
+inline void set_apb3spi_status(volatile apb3spi_t* reg, uint32_t value){
+     reg->STATUS = value;
+}
+inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg){
+    return (reg->STATUS >> 0) & 0x3f;
+}
+inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg){
+    return (reg->STATUS >> 16) & 0x3f;
+}
+
+//APB3SPI_CONFIG
+inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg){
+     return reg->CONFIG;
+}
+inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value){
+     reg->CONFIG = value;
+}
+inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg){
+    return (reg->CONFIG >> 0) & 0x3;
+}
+inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg){
+    return (reg->CONFIG >> 4) & 0x3;
+}
+inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
+}
+
+//APB3SPI_INTR
+inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg){
+     return reg->INTR;
+}
+inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value){
+     reg->INTR = value;
+}
+inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg){
+    return (reg->INTR >> 0) & 0x1;
+}
+inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value){
+    reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg){
+    return (reg->INTR >> 1) & 0x1;
+}
+inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value){
+    reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
+}
+inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg){
+    return (reg->INTR >> 8) & 0x1;
+}
+inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg){
+    return (reg->INTR >> 9) & 0x1;
+}
+inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg){
+    return (reg->INTR >> 16) & 0x1;
+}
+
+//APB3SPI_SCLK_CONFIG
+inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg){
+    return (reg->SCLK_CONFIG >> 0) & 0xfff;
+}
+inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint16_t value){
+    reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
+}
+
+//APB3SPI_SSGEN_SETUP
+inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg){
+    return (reg->SSGEN_SETUP >> 0) & 0xfff;
+}
+inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint16_t value){
+    reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
+}
+
+//APB3SPI_SSGEN_HOLD
+inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg){
+    return (reg->SSGEN_HOLD >> 0) & 0xfff;
+}
+inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint16_t value){
+    reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
+}
+
+//APB3SPI_SSGEN_DISABLE
+inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg){
+    return (reg->SSGEN_DISABLE >> 0) & 0xfff;
+}
+inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint16_t value){
+    reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
+}
+
+//APB3SPI_SSGEN_ACTIVE_HIGH
+inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg){
+    return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
+}
+inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint8_t value){
+    reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
+}
+
+//APB3SPI_XIP_ENABLE
+inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg){
+    return (reg->XIP_ENABLE >> 0) & 0x1;
+}
+inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
+}
+
+//APB3SPI_XIP_CONFIG
+inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg){
+     return reg->XIP_CONFIG;
+}
+inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value){
+     reg->XIP_CONFIG = value;
+}
+inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg){
+    return (reg->XIP_CONFIG >> 0) & 0xff;
+}
+inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg){
+    return (reg->XIP_CONFIG >> 8) & 0x1;
+}
+inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
+}
+inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg){
+    return (reg->XIP_CONFIG >> 16) & 0xff;
+}
+inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
+}
+inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg){
+    return (reg->XIP_CONFIG >> 24) & 0xf;
+}
+inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
+}
+
+//APB3SPI_XIP_MODE
+inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg){
+     return reg->XIP_MODE;
+}
+inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value){
+     reg->XIP_MODE = value;
+}
+inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg){
+    return (reg->XIP_MODE >> 0) & 0x3;
+}
+inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg){
+    return (reg->XIP_MODE >> 8) & 0x3;
+}
+inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
+}
+inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg){
+    return (reg->XIP_MODE >> 16) & 0x3;
+}
+inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
+}
+inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg){
+    return (reg->XIP_MODE >> 24) & 0x3;
+}
+inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
+}
+
+//APB3SPI_XIP_WRITE
+inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
+}
+
+//APB3SPI_XIP_READ_WRITE
+inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
+}
+
+//APB3SPI_XIP_READ
+inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg){
+    return (reg->XIP_READ >> 0) & 0xff;
+}
+
+#endif /* _BSP_APB3SPI_H */
--- a/include/ehrenberg/devices/gen/camera.h
+++ b/include/ehrenberg/devices/gen/camera.h
@ -0,0 +1,145 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-06-08 13:20:02 UTC 
+* by peakrdl_mnrs version 1.2.5
+*/
+
+#ifndef _BSP_CAMERA_H
+#define _BSP_CAMERA_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t PIXEL;
+    volatile uint32_t CONTROL;
+    volatile uint32_t STATUS;
+    volatile uint32_t CAMERA_CLOCK_CTRL;
+    volatile uint32_t IE;
+    volatile uint32_t IP;
+}camera_t;
+
+#define CAMERA_PIXEL_OFFS 0
+#define CAMERA_PIXEL_MASK 0x7ff
+#define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS)
+
+#define CAMERA_CONTROL_OFFS 0
+#define CAMERA_CONTROL_MASK 0x1
+#define CAMERA_CONTROL(V) ((V & CAMERA_CONTROL_MASK) << CAMERA_CONTROL_OFFS)
+
+#define CAMERA_STATUS_ENABLED_OFFS 0
+#define CAMERA_STATUS_ENABLED_MASK 0x1
+#define CAMERA_STATUS_ENABLED(V) ((V & CAMERA_STATUS_ENABLED_MASK) << CAMERA_STATUS_ENABLED_OFFS)
+
+#define CAMERA_STATUS_ACTIVE_OFFS 1
+#define CAMERA_STATUS_ACTIVE_MASK 0x1
+#define CAMERA_STATUS_ACTIVE(V) ((V & CAMERA_STATUS_ACTIVE_MASK) << CAMERA_STATUS_ACTIVE_OFFS)
+
+#define CAMERA_STATUS_PIXEL_AVAIL_OFFS 2
+#define CAMERA_STATUS_PIXEL_AVAIL_MASK 0x1
+#define CAMERA_STATUS_PIXEL_AVAIL(V) ((V & CAMERA_STATUS_PIXEL_AVAIL_MASK) << CAMERA_STATUS_PIXEL_AVAIL_OFFS)
+
+#define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0
+#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfffff
+#define CAMERA_CAMERA_CLOCK_CTRL(V) ((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS)
+
+#define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0
+#define CAMERA_IE_EN_PIXEL_AVAIL_MASK 0x1
+#define CAMERA_IE_EN_PIXEL_AVAIL(V) ((V & CAMERA_IE_EN_PIXEL_AVAIL_MASK) << CAMERA_IE_EN_PIXEL_AVAIL_OFFS)
+
+#define CAMERA_IE_EN_FRAME_FINISHED_OFFS 1
+#define CAMERA_IE_EN_FRAME_FINISHED_MASK 0x1
+#define CAMERA_IE_EN_FRAME_FINISHED(V) ((V & CAMERA_IE_EN_FRAME_FINISHED_MASK) << CAMERA_IE_EN_FRAME_FINISHED_OFFS)
+
+#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS 0
+#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK 0x1
+#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND(V) ((V & CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK) << CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS)
+
+#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS 1
+#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1
+#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS)
+
+//CAMERA_PIXEL
+inline uint32_t get_camera_pixel(volatile camera_t* reg){
+    return (reg->PIXEL >> 0) & 0x7ff;
+}
+inline void set_camera_pixel(volatile camera_t* reg, uint16_t value){
+    reg->PIXEL = (reg->PIXEL & ~(0x7ffU << 0)) | (value << 0);
+}
+
+//CAMERA_CONTROL
+inline uint32_t get_camera_control(volatile camera_t* reg){
+    return (reg->CONTROL >> 0) & 0x1;
+}
+inline void set_camera_control(volatile camera_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
+}
+
+//CAMERA_STATUS
+inline uint32_t get_camera_status(volatile camera_t* reg){
+     return reg->STATUS;
+}
+inline void set_camera_status(volatile camera_t* reg, uint32_t value){
+     reg->STATUS = value;
+}
+inline uint32_t get_camera_status_enabled(volatile camera_t* reg){
+    return (reg->STATUS >> 0) & 0x1;
+}
+inline uint32_t get_camera_status_active(volatile camera_t* reg){
+    return (reg->STATUS >> 1) & 0x1;
+}
+inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg){
+    return (reg->STATUS >> 2) & 0x1;
+}
+
+//CAMERA_CAMERA_CLOCK_CTRL
+inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg){
+    return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfffff;
+}
+inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value){
+    reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
+}
+
+//CAMERA_IE
+inline uint32_t get_camera_ie(volatile camera_t* reg){
+     return reg->IE;
+}
+inline void set_camera_ie(volatile camera_t* reg, uint32_t value){
+     reg->IE = value;
+}
+inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg){
+    return (reg->IE >> 0) & 0x1;
+}
+inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg){
+    return (reg->IE >> 1) & 0x1;
+}
+inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
+}
+
+//CAMERA_IP
+inline uint32_t get_camera_ip(volatile camera_t* reg){
+     return reg->IP;
+}
+inline void set_camera_ip(volatile camera_t* reg, uint32_t value){
+     reg->IP = value;
+}
+inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg){
+    return (reg->IP >> 0) & 0x1;
+}
+inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value){
+    reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg){
+    return (reg->IP >> 1) & 0x1;
+}
+inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value){
+    reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
+}
+
+#endif /* _BSP_CAMERA_H */
--- a/include/ehrenberg/devices/gen/gpio.h
+++ b/include/ehrenberg/devices/gen/gpio.h
@ -0,0 +1,54 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-06-08 13:20:02 UTC 
+* by peakrdl_mnrs version 1.2.5
+*/
+
+#ifndef _BSP_GPIO_H
+#define _BSP_GPIO_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t VALUE;
+    volatile uint32_t WRITE;
+    volatile uint32_t WRITEENABLE;
+}gpio_t;
+
+#define GPIO_VALUE_OFFS 0
+#define GPIO_VALUE_MASK 0xffffffff
+#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS)
+
+#define GPIO_WRITE_OFFS 0
+#define GPIO_WRITE_MASK 0xffffffff
+#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS)
+
+#define GPIO_WRITEENABLE_OFFS 0
+#define GPIO_WRITEENABLE_MASK 0xffffffff
+#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
+
+//GPIO_VALUE
+inline uint32_t get_gpio_value(volatile gpio_t* reg){
+    return (reg->VALUE >> 0) & 0xffffffff;
+}
+
+//GPIO_WRITE
+inline uint32_t get_gpio_write(volatile gpio_t* reg){
+    return (reg->WRITE >> 0) & 0xffffffff;
+}
+inline void set_gpio_write(volatile gpio_t* reg, uint32_t value){
+    reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_WRITEENABLE
+inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg){
+    return (reg->WRITEENABLE >> 0) & 0xffffffff;
+}
+inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value){
+    reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_GPIO_H */
--- a/include/ehrenberg/devices/gen/i2s.h
+++ b/include/ehrenberg/devices/gen/i2s.h
@ -0,0 +1,225 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-06-08 13:20:02 UTC 
+* by peakrdl_mnrs version 1.2.5
+*/
+
+#ifndef _BSP_I2S_H
+#define _BSP_I2S_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t LEFT_CH;
+    volatile uint32_t RIGHT_CH;
+    volatile uint32_t CONTROL;
+    volatile uint32_t STATUS;
+    volatile uint32_t I2S_CLOCK_CTRL;
+    volatile uint32_t PDM_CLOCK_CTRL;
+    volatile uint32_t IE;
+    volatile uint32_t IP;
+}i2s_t;
+
+#define I2S_LEFT_CH_OFFS 0
+#define I2S_LEFT_CH_MASK 0xffffffff
+#define I2S_LEFT_CH(V) ((V & I2S_LEFT_CH_MASK) << I2S_LEFT_CH_OFFS)
+
+#define I2S_RIGHT_CH_OFFS 0
+#define I2S_RIGHT_CH_MASK 0xffffffff
+#define I2S_RIGHT_CH(V) ((V & I2S_RIGHT_CH_MASK) << I2S_RIGHT_CH_OFFS)
+
+#define I2S_CONTROL_MODE_OFFS 0
+#define I2S_CONTROL_MODE_MASK 0x3
+#define I2S_CONTROL_MODE(V) ((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS)
+
+#define I2S_CONTROL_DISABLE_LEFT_OFFS 2
+#define I2S_CONTROL_DISABLE_LEFT_MASK 0x1
+#define I2S_CONTROL_DISABLE_LEFT(V) ((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS)
+
+#define I2S_CONTROL_DISABLE_RIGHT_OFFS 3
+#define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1
+#define I2S_CONTROL_DISABLE_RIGHT(V) ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS)
+
+#define I2S_CONTROL_ACTIVE_CLOCK_OFFS 4
+#define I2S_CONTROL_ACTIVE_CLOCK_MASK 0x1
+#define I2S_CONTROL_ACTIVE_CLOCK(V) ((V & I2S_CONTROL_ACTIVE_CLOCK_MASK) << I2S_CONTROL_ACTIVE_CLOCK_OFFS)
+
+#define I2S_CONTROL_PDM_SCALE_OFFS 5
+#define I2S_CONTROL_PDM_SCALE_MASK 0x7
+#define I2S_CONTROL_PDM_SCALE(V) ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS)
+
+#define I2S_STATUS_ENABLED_OFFS 0
+#define I2S_STATUS_ENABLED_MASK 0x1
+#define I2S_STATUS_ENABLED(V) ((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS)
+
+#define I2S_STATUS_ACTIVE_OFFS 1
+#define I2S_STATUS_ACTIVE_MASK 0x1
+#define I2S_STATUS_ACTIVE(V) ((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS)
+
+#define I2S_STATUS_LEFT_AVAIL_OFFS 2
+#define I2S_STATUS_LEFT_AVAIL_MASK 0x1
+#define I2S_STATUS_LEFT_AVAIL(V) ((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS)
+
+#define I2S_STATUS_RIGHT_AVAIL_OFFS 3
+#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
+#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
+
+#define I2S_STATUS_BOTH_AVAIL_OFFS 4
+#define I2S_STATUS_BOTH_AVAIL_MASK 0x1
+#define I2S_STATUS_BOTH_AVAIL(V) ((V & I2S_STATUS_BOTH_AVAIL_MASK) << I2S_STATUS_BOTH_AVAIL_OFFS)
+
+#define I2S_I2S_CLOCK_CTRL_OFFS 0
+#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
+#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
+
+#define I2S_PDM_CLOCK_CTRL_OFFS 0
+#define I2S_PDM_CLOCK_CTRL_MASK 0x3ff
+#define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)
+
+#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0
+#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS)
+
+#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS 1
+#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS)
+
+#define I2S_IP_LEFT_SAMPLE_AVAIL_OFFS 0
+#define I2S_IP_LEFT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IP_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS)
+
+#define I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS 1
+#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
+
+//I2S_LEFT_CH
+inline uint32_t get_i2s_left_ch(volatile i2s_t* reg){
+    return (reg->LEFT_CH >> 0) & 0xffffffff;
+}
+inline void set_i2s_left_ch(volatile i2s_t* reg, uint32_t value){
+    reg->LEFT_CH = (reg->LEFT_CH & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//I2S_RIGHT_CH
+inline uint32_t get_i2s_right_ch(volatile i2s_t* reg){
+    return (reg->RIGHT_CH >> 0) & 0xffffffff;
+}
+inline void set_i2s_right_ch(volatile i2s_t* reg, uint32_t value){
+    reg->RIGHT_CH = (reg->RIGHT_CH & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//I2S_CONTROL
+inline uint32_t get_i2s_control(volatile i2s_t* reg){
+     return reg->CONTROL;
+}
+inline void set_i2s_control(volatile i2s_t* reg, uint32_t value){
+     reg->CONTROL = value;
+}
+inline uint32_t get_i2s_control_mode(volatile i2s_t* reg){
+    return (reg->CONTROL >> 0) & 0x3;
+}
+inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg){
+    return (reg->CONTROL >> 2) & 0x1;
+}
+inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
+}
+inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg){
+    return (reg->CONTROL >> 3) & 0x1;
+}
+inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
+}
+inline uint32_t get_i2s_control_active_clock(volatile i2s_t* reg){
+    return (reg->CONTROL >> 4) & 0x1;
+}
+inline void set_i2s_control_active_clock(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
+}
+inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg){
+    return (reg->CONTROL >> 5) & 0x7;
+}
+inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x7U << 5)) | (value << 5);
+}
+
+//I2S_STATUS
+inline uint32_t get_i2s_status(volatile i2s_t* reg){
+     return reg->STATUS;
+}
+inline void set_i2s_status(volatile i2s_t* reg, uint32_t value){
+     reg->STATUS = value;
+}
+inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){
+    return (reg->STATUS >> 0) & 0x1;
+}
+inline uint32_t get_i2s_status_active(volatile i2s_t* reg){
+    return (reg->STATUS >> 1) & 0x1;
+}
+inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){
+    return (reg->STATUS >> 2) & 0x1;
+}
+inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
+    return (reg->STATUS >> 3) & 0x1;
+}
+inline uint32_t get_i2s_status_both_avail(volatile i2s_t* reg){
+    return (reg->STATUS >> 4) & 0x1;
+}
+
+//I2S_I2S_CLOCK_CTRL
+inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){
+    return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
+}
+inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value){
+    reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
+}
+
+//I2S_PDM_CLOCK_CTRL
+inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg){
+    return (reg->PDM_CLOCK_CTRL >> 0) & 0x3ff;
+}
+inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint16_t value){
+    reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0x3ffU << 0)) | (value << 0);
+}
+
+//I2S_IE
+inline uint32_t get_i2s_ie(volatile i2s_t* reg){
+     return reg->IE;
+}
+inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value){
+     reg->IE = value;
+}
+inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg){
+    return (reg->IE >> 0) & 0x1;
+}
+inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg){
+    return (reg->IE >> 1) & 0x1;
+}
+inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
+}
+
+//I2S_IP
+inline uint32_t get_i2s_ip(volatile i2s_t* reg){
+     return reg->IP;
+}
+inline void set_i2s_ip(volatile i2s_t* reg, uint32_t value){
+     reg->IP = value;
+}
+inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg){
+    return (reg->IP >> 0) & 0x1;
+}
+inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg){
+    return (reg->IP >> 1) & 0x1;
+}
+
+#endif /* _BSP_I2S_H */
--- a/include/ehrenberg/devices/gen/simpledma.h
+++ b/include/ehrenberg/devices/gen/simpledma.h
@ -0,0 +1,187 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-06-08 13:20:02 UTC 
+* by peakrdl_mnrs version 1.2.5
+*/
+
+#ifndef _BSP_SIMPLEDMA_H
+#define _BSP_SIMPLEDMA_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t CONTROL;
+    volatile uint32_t STATUS;
+    volatile uint32_t EVENT_SEL;
+    volatile uint32_t IE;
+    volatile uint32_t IP;
+    volatile uint32_t TRANSFER;
+    volatile uint32_t SRC_START_ADDR;
+    volatile uint32_t SRC_STRIDE;
+    volatile uint32_t DST_START_ADDR;
+    volatile uint32_t DST_STRIDE;
+}simpledma_t;
+
+#define SIMPLEDMA_CONTROL_OFFS 0
+#define SIMPLEDMA_CONTROL_MASK 0x1
+#define SIMPLEDMA_CONTROL(V) ((V & SIMPLEDMA_CONTROL_MASK) << SIMPLEDMA_CONTROL_OFFS)
+
+#define SIMPLEDMA_STATUS_OFFS 0
+#define SIMPLEDMA_STATUS_MASK 0x1
+#define SIMPLEDMA_STATUS(V) ((V & SIMPLEDMA_STATUS_MASK) << SIMPLEDMA_STATUS_OFFS)
+
+#define SIMPLEDMA_EVENT_SEL_OFFS 0
+#define SIMPLEDMA_EVENT_SEL_MASK 0x3
+#define SIMPLEDMA_EVENT_SEL(V) ((V & SIMPLEDMA_EVENT_SEL_MASK) << SIMPLEDMA_EVENT_SEL_OFFS)
+
+#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_OFFS 0
+#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_MASK 0x1
+#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_OFFS)
+
+#define SIMPLEDMA_IE_EN_TRANSFER_DONE_OFFS 1
+#define SIMPLEDMA_IE_EN_TRANSFER_DONE_MASK 0x1
+#define SIMPLEDMA_IE_EN_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_EN_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_EN_TRANSFER_DONE_OFFS)
+
+#define SIMPLEDMA_IP_SEG_TRANSFER_DONE_OFFS 0
+#define SIMPLEDMA_IP_SEG_TRANSFER_DONE_MASK 0x1
+#define SIMPLEDMA_IP_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_SEG_TRANSFER_DONE_OFFS)
+
+#define SIMPLEDMA_IP_TRANSFER_DONE_OFFS 1
+#define SIMPLEDMA_IP_TRANSFER_DONE_MASK 0x1
+#define SIMPLEDMA_IP_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_TRANSFER_DONE_OFFS)
+
+#define SIMPLEDMA_TRANSFER_LENGTH_OFFS 0
+#define SIMPLEDMA_TRANSFER_LENGTH_MASK 0x3ff
+#define SIMPLEDMA_TRANSFER_LENGTH(V) ((V & SIMPLEDMA_TRANSFER_LENGTH_MASK) << SIMPLEDMA_TRANSFER_LENGTH_OFFS)
+
+#define SIMPLEDMA_TRANSFER_COUNT_OFFS 12
+#define SIMPLEDMA_TRANSFER_COUNT_MASK 0xfffff
+#define SIMPLEDMA_TRANSFER_COUNT(V) ((V & SIMPLEDMA_TRANSFER_COUNT_MASK) << SIMPLEDMA_TRANSFER_COUNT_OFFS)
+
+#define SIMPLEDMA_SRC_START_ADDR_OFFS 0
+#define SIMPLEDMA_SRC_START_ADDR_MASK 0xffffffff
+#define SIMPLEDMA_SRC_START_ADDR(V) ((V & SIMPLEDMA_SRC_START_ADDR_MASK) << SIMPLEDMA_SRC_START_ADDR_OFFS)
+
+#define SIMPLEDMA_SRC_STRIDE_OFFS 0
+#define SIMPLEDMA_SRC_STRIDE_MASK 0xffffffff
+#define SIMPLEDMA_SRC_STRIDE(V) ((V & SIMPLEDMA_SRC_STRIDE_MASK) << SIMPLEDMA_SRC_STRIDE_OFFS)
+
+#define SIMPLEDMA_DST_START_ADDR_OFFS 0
+#define SIMPLEDMA_DST_START_ADDR_MASK 0xffffffff
+#define SIMPLEDMA_DST_START_ADDR(V) ((V & SIMPLEDMA_DST_START_ADDR_MASK) << SIMPLEDMA_DST_START_ADDR_OFFS)
+
+#define SIMPLEDMA_DST_STRIDE_OFFS 0
+#define SIMPLEDMA_DST_STRIDE_MASK 0xffffffff
+#define SIMPLEDMA_DST_STRIDE(V) ((V & SIMPLEDMA_DST_STRIDE_MASK) << SIMPLEDMA_DST_STRIDE_OFFS)
+
+//SIMPLEDMA_CONTROL
+inline uint32_t get_simpledma_control(volatile simpledma_t* reg){
+    return (reg->CONTROL >> 0) & 0x1;
+}
+inline void set_simpledma_control(volatile simpledma_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
+}
+
+//SIMPLEDMA_STATUS
+inline uint32_t get_simpledma_status(volatile simpledma_t* reg){
+    return (reg->STATUS >> 0) & 0x1;
+}
+
+//SIMPLEDMA_EVENT_SEL
+inline uint32_t get_simpledma_event_sel(volatile simpledma_t* reg){
+    return (reg->EVENT_SEL >> 0) & 0x3;
+}
+inline void set_simpledma_event_sel(volatile simpledma_t* reg, uint8_t value){
+    reg->EVENT_SEL = (reg->EVENT_SEL & ~(0x3U << 0)) | (value << 0);
+}
+
+//SIMPLEDMA_IE
+inline uint32_t get_simpledma_ie(volatile simpledma_t* reg){
+     return reg->IE;
+}
+inline void set_simpledma_ie(volatile simpledma_t* reg, uint32_t value){
+     reg->IE = value;
+}
+inline uint32_t get_simpledma_ie_en_seg_transfer_done(volatile simpledma_t* reg){
+    return (reg->IE >> 0) & 0x1;
+}
+inline void set_simpledma_ie_en_seg_transfer_done(volatile simpledma_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_simpledma_ie_en_transfer_done(volatile simpledma_t* reg){
+    return (reg->IE >> 1) & 0x1;
+}
+inline void set_simpledma_ie_en_transfer_done(volatile simpledma_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
+}
+
+//SIMPLEDMA_IP
+inline uint32_t get_simpledma_ip(volatile simpledma_t* reg){
+     return reg->IP;
+}
+inline void set_simpledma_ip(volatile simpledma_t* reg, uint32_t value){
+     reg->IP = value;
+}
+inline uint32_t get_simpledma_ip_seg_transfer_done(volatile simpledma_t* reg){
+    return (reg->IP >> 0) & 0x1;
+}
+inline uint32_t get_simpledma_ip_transfer_done(volatile simpledma_t* reg){
+    return (reg->IP >> 1) & 0x1;
+}
+
+//SIMPLEDMA_TRANSFER
+inline uint32_t get_simpledma_transfer(volatile simpledma_t* reg){
+     return reg->TRANSFER;
+}
+inline void set_simpledma_transfer(volatile simpledma_t* reg, uint32_t value){
+     reg->TRANSFER = value;
+}
+inline uint32_t get_simpledma_transfer_length(volatile simpledma_t* reg){
+    return (reg->TRANSFER >> 0) & 0x3ff;
+}
+inline void set_simpledma_transfer_length(volatile simpledma_t* reg, uint16_t value){
+    reg->TRANSFER = (reg->TRANSFER & ~(0x3ffU << 0)) | (value << 0);
+}
+inline uint32_t get_simpledma_transfer_count(volatile simpledma_t* reg){
+    return (reg->TRANSFER >> 12) & 0xfffff;
+}
+inline void set_simpledma_transfer_count(volatile simpledma_t* reg, uint32_t value){
+    reg->TRANSFER = (reg->TRANSFER & ~(0xfffffU << 12)) | (value << 12);
+}
+
+//SIMPLEDMA_SRC_START_ADDR
+inline uint32_t get_simpledma_src_start_addr(volatile simpledma_t* reg){
+    return (reg->SRC_START_ADDR >> 0) & 0xffffffff;
+}
+inline void set_simpledma_src_start_addr(volatile simpledma_t* reg, uint32_t value){
+    reg->SRC_START_ADDR = (reg->SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//SIMPLEDMA_SRC_STRIDE
+inline uint32_t get_simpledma_src_stride(volatile simpledma_t* reg){
+    return (reg->SRC_STRIDE >> 0) & 0xffffffff;
+}
+inline void set_simpledma_src_stride(volatile simpledma_t* reg, uint32_t value){
+    reg->SRC_STRIDE = (reg->SRC_STRIDE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//SIMPLEDMA_DST_START_ADDR
+inline uint32_t get_simpledma_dst_start_addr(volatile simpledma_t* reg){
+    return (reg->DST_START_ADDR >> 0) & 0xffffffff;
+}
+inline void set_simpledma_dst_start_addr(volatile simpledma_t* reg, uint32_t value){
+    reg->DST_START_ADDR = (reg->DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//SIMPLEDMA_DST_STRIDE
+inline uint32_t get_simpledma_dst_stride(volatile simpledma_t* reg){
+    return (reg->DST_STRIDE >> 0) & 0xffffffff;
+}
+inline void set_simpledma_dst_stride(volatile simpledma_t* reg, uint32_t value){
+    reg->DST_STRIDE = (reg->DST_STRIDE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_SIMPLEDMA_H */
--- a/include/ehrenberg/devices/gen/timercounter.h
+++ b/include/ehrenberg/devices/gen/timercounter.h
@ -0,0 +1,135 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-06-08 13:20:02 UTC 
+* by peakrdl_mnrs version 1.2.5
+*/
+
+#ifndef _BSP_TIMERCOUNTER_H
+#define _BSP_TIMERCOUNTER_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t PRESCALER;
+    volatile uint32_t T0_CTRL;
+    volatile uint32_t T0_OVERFLOW;
+    volatile uint32_t T0_VALUE;
+    volatile uint32_t T1_CTRL;
+    volatile uint32_t T1_OVERFLOW;
+    volatile uint32_t T1_VALUE;
+}timercounter_t;
+
+#define TIMERCOUNTER_PRESCALER_OFFS 0
+#define TIMERCOUNTER_PRESCALER_MASK 0xffff
+#define TIMERCOUNTER_PRESCALER(V) ((V & TIMERCOUNTER_PRESCALER_MASK) << TIMERCOUNTER_PRESCALER_OFFS)
+
+#define TIMERCOUNTER_T0_CTRL_ENABLE_OFFS 0
+#define TIMERCOUNTER_T0_CTRL_ENABLE_MASK 0x7
+#define TIMERCOUNTER_T0_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T0_CTRL_ENABLE_MASK) << TIMERCOUNTER_T0_CTRL_ENABLE_OFFS)
+
+#define TIMERCOUNTER_T0_CTRL_CLEAR_OFFS 3
+#define TIMERCOUNTER_T0_CTRL_CLEAR_MASK 0x3
+#define TIMERCOUNTER_T0_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T0_CTRL_CLEAR_MASK) << TIMERCOUNTER_T0_CTRL_CLEAR_OFFS)
+
+#define TIMERCOUNTER_T0_OVERFLOW_OFFS 0
+#define TIMERCOUNTER_T0_OVERFLOW_MASK 0xffffffff
+#define TIMERCOUNTER_T0_OVERFLOW(V) ((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS)
+
+#define TIMERCOUNTER_T0_VALUE_OFFS 0
+#define TIMERCOUNTER_T0_VALUE_MASK 0xffffffff
+#define TIMERCOUNTER_T0_VALUE(V) ((V & TIMERCOUNTER_T0_VALUE_MASK) << TIMERCOUNTER_T0_VALUE_OFFS)
+
+#define TIMERCOUNTER_T1_CTRL_ENABLE_OFFS 0
+#define TIMERCOUNTER_T1_CTRL_ENABLE_MASK 0x7
+#define TIMERCOUNTER_T1_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T1_CTRL_ENABLE_MASK) << TIMERCOUNTER_T1_CTRL_ENABLE_OFFS)
+
+#define TIMERCOUNTER_T1_CTRL_CLEAR_OFFS 3
+#define TIMERCOUNTER_T1_CTRL_CLEAR_MASK 0x3
+#define TIMERCOUNTER_T1_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T1_CTRL_CLEAR_MASK) << TIMERCOUNTER_T1_CTRL_CLEAR_OFFS)
+
+#define TIMERCOUNTER_T1_OVERFLOW_OFFS 0
+#define TIMERCOUNTER_T1_OVERFLOW_MASK 0xffffffff
+#define TIMERCOUNTER_T1_OVERFLOW(V) ((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS)
+
+#define TIMERCOUNTER_T1_VALUE_OFFS 0
+#define TIMERCOUNTER_T1_VALUE_MASK 0xffffffff
+#define TIMERCOUNTER_T1_VALUE(V) ((V & TIMERCOUNTER_T1_VALUE_MASK) << TIMERCOUNTER_T1_VALUE_OFFS)
+
+//TIMERCOUNTER_PRESCALER
+inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg){
+    return (reg->PRESCALER >> 0) & 0xffff;
+}
+inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint16_t value){
+    reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
+}
+
+//TIMERCOUNTER_T0_CTRL
+inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg){
+     return reg->T0_CTRL;
+}
+inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value){
+     reg->T0_CTRL = value;
+}
+inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg){
+    return (reg->T0_CTRL >> 0) & 0x7;
+}
+inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
+    reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg){
+    return (reg->T0_CTRL >> 3) & 0x3;
+}
+inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
+    reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
+}
+
+//TIMERCOUNTER_T0_OVERFLOW
+inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg){
+    return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
+}
+inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value){
+    reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//TIMERCOUNTER_T0_VALUE
+inline uint32_t get_timercounter_t0_value(volatile timercounter_t* reg){
+    return (reg->T0_VALUE >> 0) & 0xffffffff;
+}
+
+//TIMERCOUNTER_T1_CTRL
+inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg){
+     return reg->T1_CTRL;
+}
+inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value){
+     reg->T1_CTRL = value;
+}
+inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg){
+    return (reg->T1_CTRL >> 0) & 0x7;
+}
+inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
+    reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg){
+    return (reg->T1_CTRL >> 3) & 0x3;
+}
+inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
+    reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
+}
+
+//TIMERCOUNTER_T1_OVERFLOW
+inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg){
+    return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
+}
+inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value){
+    reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//TIMERCOUNTER_T1_VALUE
+inline uint32_t get_timercounter_t1_value(volatile timercounter_t* reg){
+    return (reg->T1_VALUE >> 0) & 0xffffffff;
+}
+
+#endif /* _BSP_TIMERCOUNTER_H */
--- a/include/ehrenberg/devices/gen/uart.h
+++ b/include/ehrenberg/devices/gen/uart.h
@ -0,0 +1,230 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-06-08 13:20:02 UTC 
+* by peakrdl_mnrs version 1.2.5
+*/
+
+#ifndef _BSP_UART_H
+#define _BSP_UART_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t RX_TX_REG;
+    volatile uint32_t INT_CTRL_REG;
+    volatile uint32_t CLK_DIVIDER_REG;
+    volatile uint32_t FRAME_CONFIG_REG;
+    volatile uint32_t STATUS_REG;
+}uart_t;
+
+#define UART_RX_TX_REG_DATA_OFFS 0
+#define UART_RX_TX_REG_DATA_MASK 0xff
+#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
+
+#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
+#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
+#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
+
+#define UART_RX_TX_REG_TX_FREE_OFFS 15
+#define UART_RX_TX_REG_TX_FREE_MASK 0x1
+#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
+
+#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
+#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
+#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
+
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2
+#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
+
+#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
+#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
+
+#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10
+#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS)
+
+#define UART_CLK_DIVIDER_REG_OFFS 0
+#define UART_CLK_DIVIDER_REG_MASK 0xfffff
+#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
+
+#define UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS 0
+#define UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK 0x7
+#define UART_FRAME_CONFIG_REG_DATA_LENGHT(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS)
+
+#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
+#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
+#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
+
+#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
+#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
+#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
+
+#define UART_STATUS_REG_READ_ERROR_OFFS 0
+#define UART_STATUS_REG_READ_ERROR_MASK 0x1
+#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
+
+#define UART_STATUS_REG_STALL_OFFS 1
+#define UART_STATUS_REG_STALL_MASK 0x1
+#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
+
+#define UART_STATUS_REG_BREAK_LINE_OFFS 8
+#define UART_STATUS_REG_BREAK_LINE_MASK 0x1
+#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
+
+#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
+#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
+#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
+
+#define UART_STATUS_REG_SET_BREAK_OFFS 10
+#define UART_STATUS_REG_SET_BREAK_MASK 0x1
+#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
+
+#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
+#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
+#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
+
+//UART_RX_TX_REG
+inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg){
+     return reg->RX_TX_REG;
+}
+inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value){
+     reg->RX_TX_REG = value;
+}
+inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg){
+    return (reg->RX_TX_REG >> 0) & 0xff;
+}
+inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value){
+    reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
+}
+inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg){
+    return (reg->RX_TX_REG >> 14) & 0x1;
+}
+inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){
+    return (reg->RX_TX_REG >> 15) & 0x1;
+}
+inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg){
+    return (reg->RX_TX_REG >> 16) & 0x1;
+}
+
+//UART_INT_CTRL_REG
+inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){
+     return reg->INT_CTRL_REG;
+}
+inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value){
+     reg->INT_CTRL_REG = value;
+}
+inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 0) & 0x1;
+}
+inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 1) & 0x1;
+}
+inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
+}
+inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 2) & 0x1;
+}
+inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
+}
+inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 8) & 0x1;
+}
+inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 9) & 0x1;
+}
+inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 10) & 0x1;
+}
+
+//UART_CLK_DIVIDER_REG
+inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg){
+    return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
+}
+inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value){
+    reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
+}
+
+//UART_FRAME_CONFIG_REG
+inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg){
+     return reg->FRAME_CONFIG_REG;
+}
+inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value){
+     reg->FRAME_CONFIG_REG = value;
+}
+inline uint32_t get_uart_frame_config_reg_data_lenght(volatile uart_t* reg){
+    return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
+}
+inline void set_uart_frame_config_reg_data_lenght(volatile uart_t* reg, uint8_t value){
+    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg){
+    return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
+}
+inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value){
+    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
+}
+inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg){
+    return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
+}
+inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value){
+    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
+}
+
+//UART_STATUS_REG
+inline uint32_t get_uart_status_reg(volatile uart_t* reg){
+     return reg->STATUS_REG;
+}
+inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value){
+     reg->STATUS_REG = value;
+}
+inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 0) & 0x1;
+}
+inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 1) & 0x1;
+}
+inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 8) & 0x1;
+}
+inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 9) & 0x1;
+}
+inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value){
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
+}
+inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 10) & 0x1;
+}
+inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value){
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
+}
+inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 11) & 0x1;
+}
+inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value){
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
+}
+
+#endif /* _BSP_UART_H */
--- a/include/ehrenberg/devices/gpio.h
+++ b/include/ehrenberg/devices/gpio.h
@ -1,14 +1,12 @@
-#ifndef _BSP_GPIO_H
-#define _BSP_GPIO_H
+#ifndef _DEVICES_GPIO_H
+#define _DEVICES_GPIO_H

 #include <stdint.h>
-#include "gen/Apb3Gpio.h"
+#include "gen/gpio.h"

-#define gpio_t apb3gpio_t
-
-inline void gpio_init(gpio_t* reg) {
+inline void gpio_init(volatile gpio_t* reg) {
    set_gpio_write(reg, 0);
    set_gpio_writeEnable(reg, 0);
 }

-#endif /* _BSP_GPIO_H */
+#endif /* _DEVICES_GPIO_H */
--- a/include/ehrenberg/devices/i2s.h
+++ b/include/ehrenberg/devices/i2s.h
@ -0,0 +1,6 @@
+#ifndef _BSP_IIS_H
+#define _BSP_IIS_H
+
+#include "gen/i2s.h"
+
+#endif /* _BSP_IIS_H */
--- a/include/ehrenberg/devices/interrupt.h
+++ b/include/ehrenberg/devices/interrupt.h
@ -2,13 +2,10 @@
 #define _BSP_INTERRUPT_H

 #include <stdint.h>
-#include "gen/Apb3IrqCtrl.h"

-#define irq_t apb3irqctrl_t
+#define irq_t void*

-inline void irq_init(irq_t* reg){
-    set_irq_masksReg(reg, 0);
-    set_irq_pendingsReg(reg, 0xff);
+inline void irq_init(volatile irq_t* reg){
 }

 #endif /* _BSP_INTERRUPT_H */
--- a/include/ehrenberg/devices/qspi.h
+++ b/include/ehrenberg/devices/qspi.h
@ -2,9 +2,9 @@
 #define _BSP_QSPI_H

 #include <stdint.h>
-#include "gen/Apb3SpiXdrMasterCtrl.h"
+#include "gen/apb3spi.h"

-#define qspi_t apb3spixdrmasterctrl_t
+#define qspi_t apb3spi_t
 typedef struct {
    uint32_t cpol;
    uint32_t cpha;
--- a/include/ehrenberg/devices/timer.h
+++ b/include/ehrenberg/devices/timer.h
@ -1,19 +1,19 @@
-#ifndef _BSP_TIMER_H
-#define _BSP_TIMER_H
+#ifndef _DEVICES_TIMER_H
+#define _DEVICES_TIMER_H

-#include "gen/Apb3Timer.h"
 #include <stdint.h>
+#include "gen/timercounter.h"

-inline void prescaler_init(apb3timer_t *reg, uint16_t value) {
-  set_timer_prescaler(reg, value);
+inline void prescaler_init(timercounter_t* reg, uint16_t value){
+    set_timercounter_prescaler(reg, value);
 }

-inline void timer_t0__init(apb3timer_t *reg) {
-  set_timer_t0_overflow(reg, 0xffffffff);
+inline void timer_t0__init(timercounter_t *reg){
+    set_timercounter_t0_overflow(reg, 0xffffffff);
 }

-inline void timer_t1__init(apb3timer_t *reg) {
-  set_timer_t1_overflow(reg, 0xffffffff);
+inline void timer_t1__init(timercounter_t *reg){
+    set_timercounter_t1_overflow(reg, 0xffffffff);
 }

-#endif /* _BSP_TIMER_H */
+#endif /* _DEVICES_TIMER_H */
--- a/include/ehrenberg/devices/uart.h
+++ b/include/ehrenberg/devices/uart.h
@ -1,28 +1,30 @@
-#ifndef _BSP_UART_H
-#define _BSP_UART_H
+#ifndef _DEVICES_UART_H
+#define _DEVICES_UART_H

 #include <stdint.h>
-#include "gen/Apb3Uart.h"
+#include "gen/uart.h"

-#define uart_t apb3uart_t
-
-static inline uint32_t uart_get_tx_free(volatile uart_t *reg){
-    return (reg->STATUS_REG >> 16) & 0xFF;
+static inline uint32_t uart_get_tx_free(volatile uart_t* reg){
+    return get_uart_rx_tx_reg_tx_free(reg);
 }

-static inline uint32_t uart_get_rx_avail(volatile uart_t *reg){
-    return reg->STATUS_REG >> 24;
+static inline uint32_t uart_get_tx_empty(volatile uart_t* reg){
+    return get_uart_rx_tx_reg_tx_empty(reg);
 }

-static inline void uart_write(volatile uart_t *reg, uint8_t data){
+static inline uint32_t uart_get_rx_avail(volatile uart_t* reg){
+    return get_uart_rx_tx_reg_rx_avail(reg);
+}
+
+static inline void uart_write(volatile uart_t* reg, uint8_t data){
    while(get_uart_rx_tx_reg_tx_free(reg) == 0);
    set_uart_rx_tx_reg_data(reg, data);
 }

-static inline inline uint8_t uart_read(volatile uart_t *reg){
+static inline inline uint8_t uart_read(volatile uart_t* reg){
    uint32_t res = get_uart_rx_tx_reg_data(reg);
    while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
    return res;
 }

-#endif /* _BSP_UART_H */
+#endif /* _DEVICES_UART_H */
--- a/libwrap/CMakeLists.txt
+++ b/libwrap/CMakeLists.txt
@ -0,0 +1,55 @@
+
+IF(NOT DEFINED _MK_LIBWRAP)
+
+SET(_MK_LIBWRAP TRUE)
+
+SET(LIBWRAP_DIR ${CMAKE_CURRENT_LIST_DIR})
+
+SET(LIBWRAP_SRCS
+    ${LIBWRAP_DIR}/stdlib/malloc.c
+    ${LIBWRAP_DIR}/sys/open.c
+    ${LIBWRAP_DIR}/sys/lseek.c
+    ${LIBWRAP_DIR}/sys/read.c
+    ${LIBWRAP_DIR}/sys/write.c
+    ${LIBWRAP_DIR}/sys/fstat.c
+    ${LIBWRAP_DIR}/sys/stat.c
+    ${LIBWRAP_DIR}/sys/close.c
+    ${LIBWRAP_DIR}/sys/link.c
+    ${LIBWRAP_DIR}/sys/unlink.c
+    ${LIBWRAP_DIR}/sys/execve.c
+    ${LIBWRAP_DIR}/sys/fork.c
+    ${LIBWRAP_DIR}/sys/getpid.c
+    ${LIBWRAP_DIR}/sys/kill.c
+    ${LIBWRAP_DIR}/sys/wait.c
+    ${LIBWRAP_DIR}/sys/isatty.c
+    ${LIBWRAP_DIR}/sys/times.c
+    ${LIBWRAP_DIR}/sys/sbrk.c
+    ${LIBWRAP_DIR}/sys/_exit.c
+    ${LIBWRAP_DIR}/misc/write_hex.c
+    ${LIBWRAP_DIR}/sys/printf.c
+    ${LIBWRAP_DIR}/sys/puts.c
+)
+IF(${SEMIHOSTING})
+    SET(LIBWRAP_SRCS ${LIBWRAP_SRCS} ${LIBWRAP_DIR}/semihosting/semihosting.c ${LIBWRAP_DIR}/semihosting/trap.c)
+ENDIF()
+
+SET(LIBWRAP_SYMS malloc free open lseek read write fstat stat close link unlink execve fork getpid jukk wait isatty times sbrk _exit printf puts)
+# Includes
+INCLUDE_DIRECTORIES(
+    ${LIBWRAP_DIR}
+    ${LIBWRAP_DIR}/../include
+    ${LIBWRAP_DIR}/../drivers
+    ${LIBWRAP_DIR}/../env
+    ${LIBWRAP_DIR}/../env/iss
+)
+
+ADD_LIBRARY(LIBWRAP_TGC STATIC ${LIBWRAP_SRCS})
+TARGET_COMPILE_OPTIONS(LIBWRAP_TGC PRIVATE -march=${RISCV_ARCH}_zicsr_zifencei -mabi=${RISCV_ABI} "-DBOARD_${BOARD}")
+
+FOREACH(SYM ${LIBWRAP_SYMS})
+    LIST(APPEND WRAP_LDFLAGS "-Wl,--wrap=${SYM}")
+ENDFOREACH()
+
+SET(LIBWRAP_TGC_LDFLAGS ${WRAP_LDFLAGS} "-Wl,--start-group" "-Wl,--end-group" "-L. -lLIBWRAP_TGC")
+
+ENDIF(NOT DEFINED _MK_LIBWRAP)
--- a/libwrap/semihosting/semihosting.c
+++ b/libwrap/semihosting/semihosting.c
@ -0,0 +1,195 @@
+#include <stdarg.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+#include <sys/types.h>
+
+#include "semihosting.h"
+
+#define SEMIHOSTING_SYS_OPEN 0x01
+#define SEMIHOSTING_SYS_CLOSE 0x02
+#define SEMIHOSTING_SYS_WRITEC 0x03
+#define SEMIHOSTING_SYS_WRITE0 0x04
+#define SEMIHOSTING_SYS_WRITE 0x05
+#define SEMIHOSTING_SYS_READ 0x06
+#define SEMIHOSTING_SYS_READC 0x07
+#define SEMIHOSTING_SYS_ISERROR 0x08
+#define SEMIHOSTING_SYS_ISTTY 0x09
+#define SEMIHOSTING_SYS_SEEK 0x0A
+#define SEMIHOSTING_SYS_FLEN 0x0C
+#define SEMIHOSTING_SYS_TMPNAM 0x0D
+#define SEMIHOSTING_SYS_REMOVE 0x0E
+#define SEMIHOSTING_SYS_RENAME 0x0F
+#define SEMIHOSTING_SYS_CLOCK 0x10
+#define SEMIHOSTING_SYS_TIME 0x11
+#define SEMIHOSTING_SYS_SYSTEM 0x12
+#define SEMIHOSTING_SYS_ERRNO 0x13
+#define SEMIHOSTING_SYS_GET_CMDLINE 0x15
+#define SEMIHOSTING_SYS_HEAPINFO 0x16
+#define SEMIHOSTING_EnterSVC 0x17
+#define SEMIHOSTING_SYS_EXIT 0x18
+#define SEMIHOSTING_SYS_EXIT_EXTENDED 0x20
+#define SEMIHOSTING_SYS_ELAPSED 0x30
+#define SEMIHOSTING_SYS_TICKFREQ 0x31
+
+#define RISCV_SEMIHOSTING_CALL_NUMBER 7
+
+typedef struct {
+  char *str;
+  int mode;
+  size_t length;
+} OpenVector;
+
+typedef struct {
+  char *old;
+  int old_len;
+  char *new;
+  int new_len;
+} RenameVector;
+
+typedef struct {
+  char *path;
+  size_t len;
+} RemoveVector;
+
+typedef struct {
+  int fd;
+  off_t pos;
+} SeekVector;
+
+static inline int __attribute__((always_inline))
+call_host(int reason, void *arg) {
+#if 1
+  // This must always be set back to 0 to cover the case where a host wasn't
+  // initially present, but only connected while the program was already up and
+  // running. In that case, trap() suddenly won't be called anymore, so we have
+  // to clear this variable *before* EBREAK is called.
+  sh_missing_host = 0;
+
+  register int value asm("a0") = reason;
+  register void *ptr asm("a1") = arg;
+  asm volatile(
+      // Workaround for RISC-V lack of multiple EBREAKs.
+      " .option push \n"
+      " .option norvc \n"
+      // Force 16-byte alignment to make sure that the 3 instruction fall
+      // within the same virtual page. If you the instruction straddle a page
+      // boundary the debugger fetching the instructions could lead to a page
+      // fault. Note: align 4 means, align by 2 to the power of 4!
+      " .align 4 \n"
+      " slli x0, x0, 0x1f \n"
+      " ebreak \n"
+      " srai x0, x0, 0x07 \n"
+      " .option pop \n"
+
+      : "=r"(value) /* Outputs */
+      : "0"(value),
+        "r"(ptr), [swi] "i"(RISCV_SEMIHOSTING_CALL_NUMBER) /* Inputs */
+      : "memory"                                           /* Clobbers */
+  );
+  return value;
+#else
+  return 0;
+#endif
+}
+
+int sh_errno(void) { return call_host(SEMIHOSTING_SYS_ERRNO, (void *)NULL); }
+
+int sh_time(void) { return call_host(SEMIHOSTING_SYS_TIME, (void *)NULL); }
+
+int sh_remove(char *path) {
+  size_t len = strlen(path);
+  RemoveVector vec = {path, len};
+  return call_host(SEMIHOSTING_SYS_REMOVE, &vec);
+}
+
+void sh_seek(int file_handle, off_t pos) {
+  SeekVector vec = {file_handle, pos};
+  call_host(SEMIHOSTING_SYS_SEEK, &vec);
+  return;
+}
+
+void sh_write(char *str, int file_handle) {
+  size_t length = strlen(str);
+  OpenVector vec = {str, file_handle, length};
+  call_host(SEMIHOSTING_SYS_WRITE, &vec);
+  return;
+}
+
+int sh_close(int file_handle) {
+  return call_host(SEMIHOSTING_SYS_CLOSE, file_handle);
+}
+
+void sh_exit(void) {
+  call_host(SEMIHOSTING_SYS_EXIT, (void *)NULL);
+  return;
+}
+
+void sh_exit_extended(void) {
+  call_host(SEMIHOSTING_SYS_EXIT_EXTENDED, (void *)NULL);
+  return;
+}
+
+int sh_flen(int file_handle) {
+  return call_host(SEMIHOSTING_SYS_FLEN, file_handle);
+}
+
+int sh_iserror(int num) { return call_host(SEMIHOSTING_SYS_ISERROR, num); }
+
+int sh_istty(int file_handle) {
+  return call_host(SEMIHOSTING_SYS_ISTTY, file_handle);
+}
+/*
+int sh_remove(char* path) {
+    size_t len = strlen(path);
+    RemoveVector vec = {path, len};
+    return call_host(SEMIHOSTING_SYS_REMOVE, &vec);
+}*/
+
+void sh_rename(char *old, char *new) {
+  int old_len = strlen(old);
+  int new_len = strlen(new);
+  RenameVector vec = {old, old_len, new, new_len};
+  call_host(SEMIHOSTING_SYS_RENAME, &vec);
+  return;
+}
+
+void sh_write0(const char *buf) {
+  // Print zero-terminated string
+  call_host(SEMIHOSTING_SYS_WRITE0, (void *)buf);
+}
+
+void sh_writec(char c) {
+  // Print single character
+  call_host(SEMIHOSTING_SYS_WRITEC, (void *)&c);
+}
+
+char sh_readc(void) {
+  // Read character from keyboard. (Blocking operation!)
+  char c = call_host(SEMIHOSTING_SYS_READC, (void *)NULL);
+  return c;
+}
+
+int sh_open(char *str, int mode) {
+  // mode = 0;
+  // int length = 44;
+  size_t length = strlen(str);
+  OpenVector vec = {str, mode, length};
+  return call_host(SEMIHOSTING_SYS_OPEN, &vec);
+}
+
+int sh_read(char *buf, int file_handle, size_t length) {
+  OpenVector vec = {buf, file_handle, length};
+  int i = call_host(SEMIHOSTING_SYS_READ, &vec);
+  return i;
+}
+
+int sh_clock(void) {
+  int clock = call_host(SEMIHOSTING_SYS_CLOCK, (void *)NULL);
+  return clock;
+}
+
+/*
+void sh_write(char* str, int file_handle) {
+    return;
+}*/
--- a/libwrap/semihosting/semihosting.h
+++ b/libwrap/semihosting/semihosting.h
@ -0,0 +1,31 @@
+#ifndef SEMIHOSTING_H
+#define SEMIHOSTING_H
+
+#include <sys/types.h>
+#include <unistd.h>
+// int32_t trace_write(const char* buf, uint32_t nbyte);
+
+void sh_seek(int, off_t);
+void sh_write0(const char *buf);
+void sh_writec(char c);
+char sh_readc(void);
+int sh_clock(void);
+int sh_read(char *, int, size_t);
+void sh_write(char *, int);
+int sh_open(char *, int);
+void sh_rename(char *, char *);
+int sh_remove(char *);
+int sh_istty(int);
+int sh_iserror(int);
+int sh_flen(int);
+void sh_exit(void);
+void sh_exit_extended(void);
+int sh_close(int);
+int sh_time(void);
+int sh_errno(void);
+
+int getchar(void);
+
+extern int sh_missing_host;
+
+#endif
--- a/libwrap/semihosting/trap.c
+++ b/libwrap/semihosting/trap.c
@ -0,0 +1,60 @@
+#include <math.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "encoding.h"
+
+#if defined(SEMIHOSTING)
+#define EBREAK_OPCODE 0x00100073
+#define EBREAK_MCAUSE 0x00000003
+
+#define SLLI_X0_X0_0X1F_OPCODE 0x01f01013
+#define SRAI_X0_X0_0X07_OPCODE 0x40705013
+
+int sh_missing_host = 0;
+
+void trap() { // ToDo: Check why macro CSR_MEPC and others are not
+              // resolved
+  uint32_t mepc = read_csr(0x341);   // Address of trap
+  uint32_t mtval = read_csr(0x343);  // Instruction value of trap
+  uint32_t mcause = read_csr(0x342); // Reason for the trap
+
+  if (mcause == EBREAK_MCAUSE && mtval == EBREAK_OPCODE) {
+    // This trap was caused by an EBREAK...
+
+    int aligned = ((mepc - 4) & 0x0f) == 0;
+    if (aligned && *(uint32_t *)mepc == EBREAK_OPCODE &&
+        *(uint32_t *)(mepc - 4) == SLLI_X0_X0_0X1F_OPCODE &&
+        *(uint32_t *)(mepc + 4) == SRAI_X0_X0_0X07_OPCODE) {
+      // The EBREAK was part of the semihosting call. (See semihosting.c)
+      //
+      // If a debugger were connected, this would have resulted in a CPU halt,
+      // and the debugger would have serviced the the semihosting call.
+      //
+      // However, the semihosting function was called without a debugger being
+      // attached. The best course of action is to simply return from the trap
+      // and let the semihosting function continue after the call to EBREAK to
+      // prevent the CPU from hanging in the trap handler.
+      write_csr(mepc, mepc + 4);
+
+      // Set a global variable to tell the semihosting code the the semihosting
+      // call
+      // didn't execute on the host.
+      sh_missing_host = 1;
+
+      return;
+    }
+
+    // EBREAK was not part of a semihosting call. This should not have happened.
+    // Hang forever.
+    while (1)
+      ;
+  }
+
+  // Trap was issued for another reason than an EBREAK.
+  // Replace the code below with whatever trap handler you'd normally use. (e.g.
+  // interrupt processing.)
+  while (1)
+    ;
+}
+#endif
--- a/libwrap/sys/_exit.c
+++ b/libwrap/sys/_exit.c
@ -1,8 +1,11 @@
 /* See LICENSE of license details. */

-#include <unistd.h>
 #include "platform.h"
 #include "weak_under_alias.h"
+#include <unistd.h>
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

 #if defined(BOARD_hifive1)
 static volatile uint32_t tohost;
@ -14,17 +17,21 @@ extern volatile uint32_t fromhost;

 void write_hex(int fd, uint32_t hex);

-void __wrap_exit(int code)
-{
-//volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET);
+void __wrap_exit(int code) {
+  /*#if defined(SEMIHOSTING)
+    sh_exit();
+    return;
+  #endif*/
+  // volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET);
  const char message[] = "\nProgam has exited with code:";
-//*leds = (~(code));
+  //*leds = (~(code));

  write(STDERR_FILENO, message, sizeof(message) - 1);
  write_hex(STDERR_FILENO, code);
  write(STDERR_FILENO, "\n", 1);
-  tohost = code+1;
+  tohost = code + 1;
  write(STDERR_FILENO, "\x04", 1);
-  for (;;);
+  for (;;)
+    ;
 }
 weak_under_alias(exit);
--- a/libwrap/sys/close.c
+++ b/libwrap/sys/close.c
@ -1,13 +1,18 @@
 /* See LICENSE of license details. */

-#include <errno.h>
 #include "stub.h"
 #include "weak_under_alias.h"
+#include <errno.h>
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

-int __wrap_close(int fd)
-{
+int __wrap_close(int fd) {
+#if defined(SEMIHOTING)
+  int i = sh_close(fd);
+  return i;
+#endif
  return _stub(EBADF);
 }

 weak_under_alias(close);
-
--- a/libwrap/sys/isatty.c
+++ b/libwrap/sys/isatty.c
@ -1,10 +1,16 @@
 /* See LICENSE of license details. */

-#include <unistd.h>
 #include "weak_under_alias.h"
+#include <unistd.h>
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

-int __wrap_isatty(int fd)
-{
+int __wrap_isatty(int fd) {
+#if defined(SEMIHOSTING)
+  int i = sh_istty(fd);
+  return i;
+#endif
  if (fd == STDOUT_FILENO || fd == STDERR_FILENO)
    return 1;

--- a/libwrap/sys/lseek.c
+++ b/libwrap/sys/lseek.c
@ -1,13 +1,21 @@
 /* See LICENSE of license details. */

-#include <errno.h>
-#include <unistd.h>
-#include <sys/types.h>
 #include "stub.h"
 #include "weak_under_alias.h"
+#include <errno.h>
+#include <sys/types.h>
+#include <unistd.h>
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

-off_t __wrap_lseek(int fd, off_t ptr, int dir)
-{
+off_t __wrap_lseek(int fd, off_t ptr, int dir) {
+#if defined(SEMIHOSTING)
+  if (sh_istty(fd))
+    return 0;
+  sh_seek(fd, ptr);
+  return ptr;
+#endif
  if (isatty(fd))
    return 0;

@ -15,4 +23,3 @@ off_t __wrap_lseek(int fd, off_t ptr, int dir)
 }

 weak_under_alias(lseek);
-
--- a/libwrap/sys/open.c
+++ b/libwrap/sys/open.c
@ -1,11 +1,17 @@
 /* See LICENSE of license details. */

-#include <errno.h>
 #include "stub.h"
 #include "weak_under_alias.h"
+#include <errno.h>
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

-int __wrap_open(const char* name, int flags, int mode)
-{
+int __wrap_open(const char *name, int flags, int mode) {
+#if defined(SEMIHOSTING)
+  int fd = sh_open(name, mode);
+  return fd;
+#endif
  return _stub(ENOENT);
 }
 weak_under_alias(open);
--- a/libwrap/sys/printf.c
+++ b/libwrap/sys/printf.c
@ -3,59 +3,49 @@

 #include <stdarg.h>
 #include <stddef.h>
-#include <stdio.h>
 #include <stdint.h>
+#include <stdio.h>
 #include <string.h>
 #include <unistd.h>

 #undef putchar
-int putchar(int ch)
-{
-  return write(STDOUT_FILENO, &ch, 1) == 1 ? ch : -1;
-}
+int putchar(int ch) { return write(STDOUT_FILENO, &ch, 1) == 1 ? ch : -1; }

-size_t strnlen (const char *str, size_t n)
-{
+size_t strnlen(const char *str, size_t n) {
  const char *start = str;
-  while (n-- > 0 && *str) str++;
+  while (n-- > 0 && *str)
+    str++;
  return str - start;
 }

-static void fprintf_putch(int ch, void** data)
-{
-  putchar(ch);
-}
-static void sprintf_putch(int ch, void** data)
-{
-  char** pstr = (char**)data;
+static void fprintf_putch(int ch, void **data) { putchar(ch); }
+static void sprintf_putch(int ch, void **data) {
+  char **pstr = (char **)data;
  **pstr = ch;
  (*pstr)++;
 }

-static unsigned long getuint(va_list *ap, int lflag)
-{
+static unsigned long getuint(va_list *ap, int lflag) {
  if (lflag)
    return va_arg(*ap, unsigned long);
  else
    return va_arg(*ap, unsigned int);
 }

-static long getint(va_list *ap, int lflag)
-{
+static long getint(va_list *ap, int lflag) {
  if (lflag)
    return va_arg(*ap, long);
  else
    return va_arg(*ap, int);
 }

-static inline void printnum(void (*putch)(int, void**), void **putdat,
-                    unsigned long num, unsigned base, int width, int padc)
-{
-  unsigned digs[sizeof(num)*8];
+static inline void printnum(void (*putch)(int, void **), void **putdat,
+                            unsigned long num, unsigned base, int width,
+                            int padc) {
+  unsigned digs[sizeof(num) * 8];
  int pos = 0;

-  while (1)
-  {
+  while (1) {
    digs[pos++] = num % base;
    if (num < base)
      break;
@ -69,9 +59,8 @@ static inline void printnum(void (*putch)(int, void**), void **putdat,
    putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat);
 }

-static inline void print_double(void (*putch)(int, void**), void **putdat,
-                                double num, int width, int prec)
-{
+static inline void print_double(void (*putch)(int, void **), void **putdat,
+                                double num, int width, int prec) {
  union {
    double d;
    uint64_t u;
@ -87,30 +76,30 @@ static inline void print_double(void (*putch)(int, void**), void **putdat,
    u.d *= 10;

  char buf[32], *pbuf = buf;
-  printnum(sprintf_putch, (void**)&pbuf, (unsigned long)u.d, 10, 0, 0);
+  printnum(sprintf_putch, (void **)&pbuf, (unsigned long)u.d, 10, 0, 0);
  if (prec > 0) {
    for (int i = 0; i < prec; i++) {
-      pbuf[-i] = pbuf[-i-1];
+      pbuf[-i] = pbuf[-i - 1];
    }
    pbuf[-prec] = '.';
    pbuf++;
  }

-  for (char* p = buf; p < pbuf; p++)
+  for (char *p = buf; p < pbuf; p++)
    putch(*p, putdat);
 }

-static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap)
-{
-  register const char* p;
-  const char* last_fmt;
+static void vprintfmt(void (*putch)(int, void **), void **putdat,
+                      const char *fmt, va_list ap) {
+  register const char *p;
+  const char *last_fmt;
  register int ch;
  unsigned long num;
  int base, lflag, width, precision;
  char padc;

  while (1) {
-    while ((ch = *(const char *) fmt) != '%') {
+    while ((ch = *(const char *)fmt) != '%') {
      if (ch == '\0')
        return;
      fmt++;
@ -125,13 +114,13 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
    precision = -1;
    lflag = 0;
  reswitch:
-    switch (ch = *(const char *) fmt++) {
+    switch (ch = *(const char *)fmt++) {

    // flag to pad on the right
    case '-':
      padc = '-';
      goto reswitch;
-      
+
    // flag to pad with 0's instead of spaces
    case '0':
      padc = '0';
@ -147,7 +136,7 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
    case '7':
    case '8':
    case '9':
-      for (precision = 0; ; ++fmt) {
+      for (precision = 0;; ++fmt) {
        precision = precision * 10 + ch - '0';
        ch = *fmt;
        if (ch < '0' || ch > '9')
@ -172,61 +161,62 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
        width = precision, precision = -1;
      goto reswitch;

-    case 'l':    // long flag
+    case 'l': // long flag
      if (lflag)
        goto bad;
      goto reswitch;
-    case 'c':    // character
+    case 'c': // character
      putch(va_arg(ap, int), putdat);
      break;
-    case 'f':    // double
+    case 'f': // double
      print_double(putch, putdat, va_arg(ap, double), width, precision);
      break;
-    case 's':    // string
+    case 's': // string
      if ((p = va_arg(ap, char *)) == NULL)
        p = "(null)";
      if (width > 0 && padc != '-')
        for (width -= strnlen(p, precision); width > 0; width--)
          putch(padc, putdat);
-      for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) {
+      for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0);
+           width--) {
        putch(ch, putdat);
        p++;
      }
      for (; width > 0; width--)
        putch(' ', putdat);
      break;
-    case 'd':    // (signed) decimal
+    case 'd': // (signed) decimal
      num = getint(&ap, lflag);
-      if ((long) num < 0) {
+      if ((long)num < 0) {
        putch('-', putdat);
-        num = -(long) num;
+        num = -(long)num;
      }
      base = 10;
      goto signed_number;
-    case 'u':    // unsigned decimal
+    case 'u': // unsigned decimal
      base = 10;
      goto unsigned_number;
    case 'o': // (unsigned) octal
      // should do something with padding so it's always 3 octits
      base = 8;
      goto unsigned_number;
-    case 'p':// pointer
+    case 'p': // pointer
      lflag = 1;
      putch('0', putdat);
      putch('x', putdat);
      /* fall through to 'x' */
      __attribute__((fallthrough));
-    case 'x':    // (unsigned) hexadecimal
+    case 'x': // (unsigned) hexadecimal
      base = 16;
-      unsigned_number:
+    unsigned_number:
      num = getuint(&ap, lflag);
-      signed_number:
+    signed_number:
      printnum(putch, putdat, num, base, width, padc);
      break;
-    case '%':    // escaped '%' character
+    case '%': // escaped '%' character
      putch(ch, putdat);
      break;
-    default:    // unrecognized escape sequence - just print it literally
+    default: // unrecognized escape sequence - just print it literally
    bad:
      putch('%', putdat);
      fmt = last_fmt;
@ -235,8 +225,7 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
  }
 }

-int __wrap_printf(const char* fmt, ...)
-{
+int __wrap_printf(const char *fmt, ...) {
  va_list ap;
  va_start(ap, fmt);

@ -246,13 +235,12 @@ int __wrap_printf(const char* fmt, ...)
  return 0; // incorrect return value, but who cares, anyway?
 }

-int __wrap_sprintf(char* str, const char* fmt, ...)
-{
+int __wrap_sprintf(char *str, const char *fmt, ...) {
  va_list ap;
-  char* str0 = str;
+  char *str0 = str;
  va_start(ap, fmt);

-  vprintfmt(sprintf_putch, (void**)&str, fmt, ap);
+  vprintfmt(sprintf_putch, (void **)&str, fmt, ap);
  *str = 0;

  va_end(ap);
--- a/libwrap/sys/puts.c
+++ b/libwrap/sys/puts.c
@ -8,8 +8,15 @@
 #include "platform.h"
 #include "stub.h"
 #include "weak_under_alias.h"
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

 int __wrap_puts(const char *s) {
+#if defined(SEMIHOSTING)
+  sh_write0(s);
+  return 0;
+#endif
  while (*s != '\0') {
 #if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
    while (get_uart_rx_tx_reg_tx_free(uart) == 0)
--- a/libwrap/sys/read.c
+++ b/libwrap/sys/read.c
@ -1,15 +1,23 @@
 /* See LICENSE of license details. */

-#include "platform.h"
-#include "stub.h"
-#include "weak_under_alias.h"
 #include <errno.h>
 #include <stdint.h>
 #include <sys/types.h>
 #include <unistd.h>

+#include "platform.h"
+#include "stub.h"
+#include "weak_under_alias.h"
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif
+
 ssize_t __wrap_read(int fd, void *ptr, size_t len) {
  uint8_t *current = (uint8_t *)ptr;
+#if defined(SEMIHOSTING)
+  int i = sh_read(current, fd, len);
+  return i;
+#endif
 #if defined(BOARD_hifive1)
  volatile uint32_t *uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
  volatile uint8_t *uart_rx_cnt =
--- a/libwrap/sys/unlink.c
+++ b/libwrap/sys/unlink.c
@ -1,11 +1,16 @@
 /* See LICENSE of license details. */

-#include <errno.h>
 #include "stub.h"
 #include "weak_under_alias.h"
+#include <errno.h>
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

-int __wrap_unlink(const char* name)
-{
+int __wrap_unlink(const char *name) {
+#if defined(SEMIHOSTING)
+  return sh_remove(name);
+#endif
  return _stub(ENOENT);
 }
 weak_under_alias(unlink);
--- a/libwrap/sys/write.c
+++ b/libwrap/sys/write.c
@ -8,8 +8,24 @@
 #include "platform.h"
 #include "stub.h"
 #include "weak_under_alias.h"
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif
+
 ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
  const uint8_t *current = (const uint8_t *)ptr;
+#if defined(SEMIHOSTING)
+  if (isatty(fd)) {
+    for (size_t jj = 0; jj < len; jj++) {
+      sh_writec(current[jj]);
+    }
+    return len;
+  } else {
+    sh_write(current, fd);
+    return len;
+  }
+  // return len;
+#endif
  if (isatty(fd)) {
    for (size_t jj = 0; jj < len; jj++) {
 #if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
Author	SHA1	Message	Date
Eyck Jentzsch	daa1ed184d	adds missing ehrenberg devices	2024-06-10 12:21:20 +02:00
Eyck Jentzsch	231366cc94	updates ehrenberg devices and BSP	2024-06-10 10:13:07 +02:00
Gabriel Konecny	c94eb7c61a	update include path	2024-05-31 09:21:57 +02:00
Gabriel Konecny	9407d2cec5	Merge branch 'develop' of https://git.minres.com/Firmware/MNRS-BM-BSP into develop	2024-05-31 08:58:05 +02:00
Gabriel Konecny	092f0fdfd3	update include paths	2024-05-31 08:56:21 +02:00
Eyck Jentzsch	05062c5be4	updates Ehrenberg register description	2024-05-30 18:33:53 +02:00
Eyck Jentzsch	442384574b	Merge branch 'develop' of https://git.minres.com/Firmware/MNRS-BM-BSP.git into develop	2024-05-30 18:33:35 +02:00
Gabriel Konecny	ff8b3bb39c	merge semihosting and bsp	2024-04-30 08:56:57 +02:00
Gabriel Konecny	9aaf428620	further semihosting support	2024-04-30 08:48:44 +02:00
Gabriel Konecny	e83f7996bc	Adding semihosting support for bmsp	2024-04-08 14:36:22 +02:00
Gabriel Konecny	39ee91af7d	first semihosting integration	2024-02-26 20:41:15 +01:00