Eyck-Alexander Jentzsch
|
c6b99cd155
|
introduces new decoder to interp backend
|
2024-07-24 12:28:35 +02:00 |
Eyck-Alexander Jentzsch
|
b1306c3a47
|
improves instruction decoding by avoiding copying, replaces .size()
|
2024-07-24 08:54:37 +02:00 |
Eyck-Alexander Jentzsch
|
0d6bf924ed
|
changes jh.globals from map to vector
|
2024-07-23 15:45:51 +02:00 |
Eyck-Alexander Jentzsch
|
86de536c8f
|
changes jh globals to seperate riscv specifics
|
2024-07-23 14:35:31 +02:00 |
Eyck-Alexander Jentzsch
|
051dd5e2d3
|
updates templates for decoder in seperate class, adds again generated templates
|
2024-07-23 13:46:10 +02:00 |
Eyck-Alexander Jentzsch
|
e3942be776
|
Introduces decoder in a seperate class
|
2024-07-23 13:08:53 +02:00 |
Eyck-Alexander Jentzsch
|
6ee484a771
|
moves instruction decoder into own class
|
2024-07-23 11:30:33 +02:00 |
Eyck-Alexander Jentzsch
|
60808c8649
|
corrects template since util fns are no longer vm_base members
|
2024-07-23 11:29:56 +02:00 |
Eyck-Alexander Jentzsch
|
0432803d82
|
updates templates and vm impls for better LAST_BRANCH handling
|
2024-07-22 09:04:17 +02:00 |
Eyck-Alexander Jentzsch
|
d42d2ce533
|
corrects illegal instruction for llvm
|
2024-07-18 14:04:23 +02:00 |
Eyck-Alexander Jentzsch
|
236d12d7f5
|
integrates gen_bool for Conditions (was truncation) into llvm
|
2024-07-18 13:30:42 +02:00 |
Eyck-Alexander Jentzsch
|
e1b6cab890
|
removes setting of NEXT_PC to max when trapping in llvm and asmjit, adds default disass to llvm
|
2024-07-18 12:02:40 +02:00 |
Eyck-Alexander Jentzsch
|
8361f88718
|
removes setting of NEXT_PC to max if trap
|
2024-07-18 11:37:53 +02:00 |
Eyck-Alexander Jentzsch
|
2ec7ea4b41
|
removes leftover gen_sync in asmjit
|
2024-07-17 22:39:12 +02:00 |
Eyck-Alexander Jentzsch
|
b24965d321
|
corrects gen_sync update order, improves illegal instruction
|
2024-07-17 20:52:01 +02:00 |
Eyck-Alexander Jentzsch
|
244bf6d2f2
|
corrects gen_sync before trap check, improves illegal_instruction
|
2024-07-17 20:25:49 +02:00 |
Eyck-Alexander Jentzsch
|
1a4465a371
|
changes template: adds correct illegal instruction, reorders gen_sync to allow correct instr id eve when trapping, adds newly generated vm
|
2024-07-17 19:59:01 +02:00 |
Eyck-Alexander Jentzsch
|
11a30caae8
|
integrates generator changes to canPrecompute
|
2024-07-17 15:14:13 +02:00 |
Eyck-Alexander Jentzsch
|
ac1a26a10c
|
integrates new tval changes into llvm
|
2024-07-17 14:17:02 +02:00 |
Eyck-Alexander Jentzsch
|
7a199e122d
|
integrates new tval changes into asmjit
|
2024-07-17 09:42:12 +02:00 |
Eyck-Alexander Jentzsch
|
d8c3d2e19c
|
integrates new tval changes into tcc
|
2024-07-16 17:35:23 +02:00 |
Eyck-Alexander Jentzsch
|
375755999a
|
integrates new tval changes
|
2024-07-16 15:32:35 +02:00 |
Stanislaw Kaushanski
|
9996fd4833
|
change cache line size to 64
|
2024-07-11 14:03:58 +02:00 |
Eyck-Alexander Jentzsch
|
149b3136d2
|
updates generated files
|
2024-07-10 12:55:36 +02:00 |
Eyck-Alexander Jentzsch
|
ac8f8b0539
|
updates vms with fixed Zc in tgc5c.core_desc
|
2024-07-10 12:51:59 +02:00 |
Eyck-Alexander Jentzsch
|
b2cbf90d0b
|
updates generated files
|
2024-07-10 12:51:59 +02:00 |
Eyck-Alexander Jentzsch
|
373145478e
|
updats file because of generator changes
|
2024-07-10 12:51:59 +02:00 |
Eyck-Alexander Jentzsch
|
55b0cea94f
|
changes vm_base util API
|
2024-07-10 12:51:59 +02:00 |
Eyck-Alexander Jentzsch
|
5b17599aa2
|
allows usage of std::variants
|
2024-07-10 12:51:59 +02:00 |
Eyck-Alexander Jentzsch
|
4cfb15c7cd
|
Asmjit and interp working
|
2024-07-10 12:51:31 +02:00 |
Eyck Jentzsch
|
63da7f8d57
|
applies clang-format
|
2024-07-09 13:57:11 +02:00 |
Eyck Jentzsch
|
fb4012fbd1
|
moves likely annotation
|
2024-07-09 13:52:10 +02:00 |
Eyck Jentzsch
|
24449f1c0f
|
fixes some elf load issue
|
2024-07-05 12:18:36 +02:00 |
Eyck Jentzsch
|
fd303c8343
|
fixes asmjit deprecation warning
|
2024-07-05 07:51:37 +02:00 |
Eyck Jentzsch
|
346b177a87
|
extends finishing conditions
|
2024-07-05 05:52:29 +02:00 |
Stanislaw Kaushanski
|
d4ec131fa7
|
change COUNT_LIMIT to ICOUNT_LIMIT
|
2024-07-04 10:46:24 +02:00 |
Eyck-Alexander Jentzsch
|
48370a4555
|
asmjit passes backend with new CoreDSL
|
2024-06-22 09:28:26 +02:00 |
Eyck Jentzsch
|
8460f4ab7f
|
updates templates to re-enable interactive debugging of generator
|
2024-06-21 10:46:11 +02:00 |
Eyck Jentzsch
|
3fd51cc68c
|
fixes templates
|
2024-06-14 19:54:33 +02:00 |
Eyck Jentzsch
|
551822916c
|
applies clang-format
|
2024-06-14 17:43:12 +02:00 |
Eyck-Alexander Jentzsch
|
e2da306eee
|
fixes semihosting cb registration
|
2024-05-31 10:45:28 +02:00 |
Eyck-Alexander Jentzsch
|
41051f8f34
|
fixes tohost handling
|
2024-05-31 10:43:38 +02:00 |
gabriel
|
a6c48ceaac
|
Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop
|
2024-05-31 09:42:13 +02:00 |
gabriel
|
ed793471bb
|
adding semhosting
|
2024-05-31 07:27:47 +02:00 |
Eyck-Alexander Jentzsch
|
58fb815f32
|
fixes gen_raise in tcc
|
2024-05-20 10:34:23 +02:00 |
Eyck-Alexander Jentzsch
|
3cc8bd0854
|
adds reformat bc of verilog literals
|
2024-05-18 21:01:05 +02:00 |
Eyck-Alexander Jentzsch
|
a27850f841
|
adds verilog literal and illegal_instr to asmjit
|
2024-05-18 21:00:21 +02:00 |
Eyck-Alexander Jentzsch
|
fb330cddea
|
llvm passes act
|
2024-05-18 19:33:57 +02:00 |
Eyck-Alexander Jentzsch
|
b76c5bf0d6
|
adds flush to fence_i
|
2024-05-11 15:25:49 +02:00 |
Eyck-Alexander Jentzsch
|
001c6349f7
|
removes tcc sim stop when writing to tohost
|
2024-05-11 15:16:46 +02:00 |