 Stanislaw Kaushanski
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b25b7848c6
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fix formatting
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2024-03-19 11:47:12 +01:00 |
 Eyck-Alexander Jentzsch
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6c986d38d8
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Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop
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2024-03-19 11:02:17 +01:00 |
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Eyck-Alexander Jentzsch
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a1ebd83d2a
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adds riscv_hart_common and signature output
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2024-03-19 11:02:03 +01:00 |
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Stanislaw Kaushanski
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8aed551813
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Add a new LOG macro in SCC to avoid conflicts with other libraries.
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2024-03-14 09:43:08 +01:00 |
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Eyck-Alexander Jentzsch
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207f778ee6
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adds initial semihosting host capabilities
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2024-01-08 17:17:59 +01:00 |
 Eyck Jentzsch
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bc4ea30815
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apply clang-format 10 fixes
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2023-12-01 14:50:54 +01:00 |
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Eyck Jentzsch
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e921201f7b
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applies clang-format fixes
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2023-11-30 11:51:49 +01:00 |
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Eyck Jentzsch
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e6aa6e5842
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adds handling of variable number of clic interrupts
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2023-11-22 11:47:31 +01:00 |
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Eyck-Alexander Jentzsch
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0eb1db0e7e
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adds functionality, adds working asmjit
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2023-11-20 11:45:52 +01:00 |
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Eyck Jentzsch
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759061b569
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applies clang-format changes
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2023-10-29 17:06:56 +01:00 |
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Stanislaw Kaushanski
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9180ad1f9c
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debugger memory accesses should never lead to traps
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2023-10-06 21:39:48 +02:00 |
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Eyck-Alexander Jentzsch
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212fb1c8ff
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adds tracing functionality
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2023-09-22 12:40:35 +02:00 |
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Eyck-Alexander Jentzsch
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de45d06878
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adds initial working version of llvm backend
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2023-09-19 16:26:07 +02:00 |
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Eyck Jentzsch
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20e920338c
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removes v2p function
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2023-08-04 13:08:10 +02:00 |
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Eyck-Alexander Jentzsch
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87b4082633
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Merge branch 'tmp' into develop
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2023-07-03 14:22:50 +02:00 |
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Eyck Jentzsch
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4dbc7433a5
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fixes cause CSR handling
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2023-06-12 17:38:56 +02:00 |
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Eyck Jentzsch
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0b5de90fb1
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changes [m|u]cause rd/wr handling
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2023-06-11 18:29:58 +02:00 |
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Eyck-Alexander Jentzsch
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11c481cec2
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adds verbosity to error
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2023-06-05 15:17:16 +02:00 |
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Eyck Jentzsch
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a123beb301
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fixes duplicate variable declaration and templates
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2023-05-27 10:20:49 +02:00 |
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Eyck Jentzsch
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aa70d8a54a
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fixes CLIC to match clicinfo description in CLIC spec 11.04.2023
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2023-05-02 17:22:13 +02:00 |
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Eyck Jentzsch
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d990f1cf5d
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fixes reading of 64bit CSR register
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2023-05-01 22:23:35 +02:00 |
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Eyck Jentzsch
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1672b01e62
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adds WT cache functionality as mixin
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2023-04-28 20:38:07 +02:00 |
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Eyck Jentzsch
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00b0f101ac
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adapts to changes of instrumentation interface in dbt-rise-core
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2023-04-28 20:38:07 +02:00 |
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Eyck Jentzsch
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98dd329833
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fixes CSR access rights
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2023-04-04 09:23:08 +02:00 |
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Eyck Jentzsch
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6213445bc4
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fixes 64bit behavior of CSR regs
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2023-03-27 12:04:43 +02:00 |
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Eyck Jentzsch
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2e4faa4d50
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fixes mstatus mask
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2023-03-25 09:14:56 +01:00 |
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Eyck Jentzsch
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8e1951f298
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adds 64bit mstatus
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2023-03-23 07:47:21 +01:00 |
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Eyck Jentzsch
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7efa924510
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fixes m/uintstatus read
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2023-03-17 10:51:39 +01:00 |
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Eyck Jentzsch
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febbc4fff0
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fixes m/uintstatus read
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2023-03-17 10:23:05 +01:00 |
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Eyck Jentzsch
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39b2788b7e
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implements and fixes CLIC CSR behavior
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2023-03-17 09:09:09 +01:00 |
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Eyck Jentzsch
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a943dd3bdf
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fixes wrong array size which led to unintended CSR definitions
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2023-03-15 14:16:08 +01:00 |
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Eyck Jentzsch
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fedbff5971
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fixes xcause and u-mode clic CSRs
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2023-03-15 12:27:39 +01:00 |
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Eyck Jentzsch
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c2758e8321
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removes mscratchcsw from CLIC feature
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2023-03-15 09:07:00 +01:00 |
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Eyck Jentzsch
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8be5fe71df
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fixes template name typo
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2023-03-12 07:42:09 +01:00 |
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Eyck Jentzsch
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3f7ce41b9d
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fixes CLIC mtvt register behavior
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2023-03-11 14:03:03 +01:00 |
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Eyck Jentzsch
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ad1cbedf00
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adds back missing max irq functions
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2023-03-11 12:47:10 +01:00 |
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Eyck Jentzsch
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83f54b5074
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fixes CLICCFG settings
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2023-03-11 08:48:03 +01:00 |
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Eyck Jentzsch
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a83928fd8c
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fixes CSR/CLIC implementation
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2023-03-10 20:40:21 +01:00 |
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Eyck Jentzsch
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62c118e501
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fixes CSR to match latest fast interrupts spec
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2023-01-20 16:21:04 +01:00 |
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Eyck Jentzsch
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1a0fc4bd5d
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fixes wrong mcounteren in M-mode only priv wrapper
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2022-10-10 08:59:27 +02:00 |
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Eyck Jentzsch
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40d1966e9a
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fixes pending irq within irq hander behavior
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2022-10-08 11:20:52 +02:00 |
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Eyck Jentzsch
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a977200284
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cleans up priv wrappers
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2022-10-05 08:58:57 +02:00 |
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Eyck Jentzsch
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57347ae4d9
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fixes cppcheck flagged issues
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2022-07-23 13:49:10 +02:00 |
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Eyck Jentzsch
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966d1616c5
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change source code to unified layout
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2022-05-21 11:55:24 +02:00 |