 Eyck Jentzsch
|
00b0f101ac
|
adapts to changes of instrumentation interface in dbt-rise-core
|
2023-04-28 20:38:07 +02:00 |
Rocco Jonack
|
54f75f92ea
|
improved testbench import; added prebuild FW for testing
|
2023-04-24 08:44:12 -07:00 |
|
Rocco Jonack
|
0304aac9e5
|
fixed some issues in import script; added README for reference; added initial testbench script(to be improved)
|
2023-04-19 05:20:58 -07:00 |
|
Eyck Jentzsch
|
8ff55d7b92
|
updates CWR dependent core_complex definition
|
2023-04-14 19:34:41 +02:00 |
|
Eyck Jentzsch
|
f626ee2684
|
fixes privilege wrapper for M/U to cope with 64bit
|
2023-04-05 15:38:25 +02:00 |
|
Eyck Jentzsch
|
a8a2782329
|
adds changes from latest CoreDSL description
|
2023-04-04 16:10:12 +02:00 |
|
Eyck Jentzsch
|
98dd329833
|
fixes CSR access rights
|
2023-04-04 09:23:08 +02:00 |
|
Eyck Jentzsch
|
6213445bc4
|
fixes 64bit behavior of CSR regs
|
2023-03-27 12:04:43 +02:00 |
|
Eyck Jentzsch
|
c5465bf9e2
|
fixes according to fixed generator
|
2023-03-26 14:44:15 +02:00 |
|
Eyck Jentzsch
|
d881cb6e63
|
fix data width of generated code
|
2023-03-26 12:12:34 +02:00 |
|
Eyck Jentzsch
|
2e4faa4d50
|
fixes mstatus mask
|
2023-03-25 09:14:56 +01:00 |
|
Eyck Jentzsch
|
8e1951f298
|
adds 64bit mstatus
|
2023-03-23 07:47:21 +01:00 |
|
Eyck Jentzsch
|
7efa924510
|
fixes m/uintstatus read
|
2023-03-17 10:51:39 +01:00 |
|
Eyck Jentzsch
|
febbc4fff0
|
fixes m/uintstatus read
|
2023-03-17 10:23:05 +01:00 |
|
Eyck Jentzsch
|
39b2788b7e
|
implements and fixes CLIC CSR behavior
|
2023-03-17 09:09:09 +01:00 |
|
Eyck Jentzsch
|
a943dd3bdf
|
fixes wrong array size which led to unintended CSR definitions
|
2023-03-15 14:16:08 +01:00 |
|
Eyck Jentzsch
|
fedbff5971
|
fixes xcause and u-mode clic CSRs
|
2023-03-15 12:27:39 +01:00 |
|
Eyck Jentzsch
|
c2758e8321
|
removes mscratchcsw from CLIC feature
|
2023-03-15 09:07:00 +01:00 |
|
Eyck Jentzsch
|
8be5fe71df
|
fixes template name typo
|
2023-03-12 07:42:09 +01:00 |
|
Eyck Jentzsch
|
3f7ce41b9d
|
fixes CLIC mtvt register behavior
|
2023-03-11 14:03:03 +01:00 |
|
Eyck Jentzsch
|
ad1cbedf00
|
adds back missing max irq functions
|
2023-03-11 12:47:10 +01:00 |
|
Eyck Jentzsch
|
83f54b5074
|
fixes CLICCFG settings
|
2023-03-11 08:48:03 +01:00 |
|
Eyck Jentzsch
|
a83928fd8c
|
fixes CSR/CLIC implementation
|
2023-03-10 20:40:21 +01:00 |
|
Eyck Jentzsch
|
ec55efd322
|
adds generator changed files
|
2023-02-17 06:36:34 +01:00 |
|
Eyck Jentzsch
|
8c3709f92a
|
adds generator changed files
|
2023-02-17 06:29:27 +01:00 |
|
Eyck Jentzsch
|
207dbf1071
|
fixes out of range access for register alias names
|
2023-02-17 06:28:30 +01:00 |
|
Eyck Jentzsch
|
62c118e501
|
fixes CSR to match latest fast interrupts spec
|
2023-01-20 16:21:04 +01:00 |
|
Eyck Jentzsch
|
65dca13b42
|
fixes WFI miss of interrupt
|
2023-01-14 17:40:21 +01:00 |
|
Eyck Jentzsch
|
3187cbdfe2
|
removes CONAN_PKG from build system
|
2022-12-12 02:55:44 +01:00 |
|
Eyck Jentzsch
|
8c701d55c1
|
adapt to latest changes in SCC
|
2022-12-05 09:15:48 +01:00 |
|
Eyck Jentzsch
|
f585489ff5
|
fixes pin naming
|
2022-10-26 17:21:44 +02:00 |
|
Eyck Jentzsch
|
7113683ee0
|
moves pending interrupt check before handling trap thus saving 1 cycle
|
2022-10-15 10:47:35 +02:00 |
|
Eyck Jentzsch
|
1a0fc4bd5d
|
fixes wrong mcounteren in M-mode only priv wrapper
|
2022-10-10 08:59:27 +02:00 |
|
Eyck Jentzsch
|
40d1966e9a
|
fixes pending irq within irq hander behavior
|
2022-10-08 11:20:52 +02:00 |
|
Eyck Jentzsch
|
a977200284
|
cleans up priv wrappers
|
2022-10-05 08:58:57 +02:00 |
|
Eyck Jentzsch
|
b20fd3eba5
|
fix static build
|
2022-09-28 19:37:47 +02:00 |
|
Eyck Jentzsch
|
b20daa1ac2
|
fixes wrong path in install
|
2022-09-27 09:11:41 +02:00 |
|
Eyck Jentzsch
|
b1a18459e7
|
adds more flexible use of availabel targets
|
2022-09-26 13:57:24 +02:00 |
|
Eyck Jentzsch
|
6ba7c82f80
|
fixes wrapper definitions for hwl cores
|
2022-09-26 13:31:46 +02:00 |
|
Eyck Jentzsch
|
ad7bb28b4c
|
fixes write mask of clic memory mapped registers
|
2022-09-17 12:15:19 +02:00 |
|
Eyck Jentzsch
|
fa7eda0889
|
fixes wrong check for exception
|
2022-08-31 11:45:53 +02:00 |
|
Eyck Jentzsch
|
00e02bf565
|
adds support for different branch types in tracing
|
2022-08-08 06:30:37 +02:00 |
|
Eyck Jentzsch
|
1ad66a71d8
|
extends supported break point types
|
2022-08-06 09:53:24 +02:00 |
|
Eyck Jentzsch
|
e60fa3d5e6
|
adaptes to changes in dbt-rise-core
|
2022-08-06 09:49:32 +02:00 |
|
Eyck Jentzsch
|
8407f6287f
|
replaces core_complex socket
|
2022-07-24 20:52:28 +02:00 |
|
Eyck Jentzsch
|
0833198d34
|
aads missing windows compat firx to template
|
2022-07-23 14:36:23 +02:00 |
|
Eyck Jentzsch
|
57347ae4d9
|
fixes cppcheck flagged issues
|
2022-07-23 13:49:10 +02:00 |
|
Eyck Jentzsch
|
4876f18ba9
|
adds windows compatibility fixes
|
2022-07-18 11:43:42 +02:00 |
|
Eyck Jentzsch
|
a53ee42e13
|
updates TGC_C according to CoreDSL description update
|
2022-07-12 22:34:22 +02:00 |
|
Eyck Jentzsch
|
12ccfc055a
|
updates generate tgc_c definition
|
2022-07-11 22:58:10 +02:00 |