MNRS-BM-BSP

446af340c8 fpga_spn: use separate reset for DMA Johannes Wirth 2021-11-10 09:51:19 +0100
89ea594399 Update FPGA Firmware for bigger batch sizes Johannes Wirth 2021-07-13 10:51:28 +0200
a70f5bb09c add wait for both spn interrupts Stanislaw Kaushanski 2021-05-17 11:54:37 +0200
1b09899d2a XSPN hybrid simulation passed in MINRES environment Stanislaw Kaushanski 2021-04-22 14:50:21 +0200
5ba7d5dd24 extend spn_checker to comapre the results from 2nd XSPN accelerator Stanislaw Kaushanski 2021-04-20 20:36:00 +0200
26d7560891 add second XSPN partition Stanislaw Kaushanski 2021-04-20 08:30:39 +0200
96de37dbc2 increase XSPN load Stanislaw Kaushanski 2021-04-14 08:45:21 +0200
d0eff8c08d longer simulation Stanislaw Kaushanski 2021-04-12 13:12:04 +0200
2a9ce332c7 fix hello-world init Stanislaw Kaushanski 2021-04-09 11:19:05 +0200
9578bcfa45 Use spn_checker in fpga_spn firmware Johannes Wirth 2021-03-31 16:22:08 +0200
f5e0d13891 move data handling into snp_checker vp Stanislaw Kaushanski 2021-03-26 10:36:15 +0100
b03f1bff4f create snp result checker to enable parallel spn calculation and result comparison Stanislaw Kaushanski 2021-03-25 09:36:16 +0100
8c0211f945 Cleanup SPN firmwares Johannes Wirth 2021-03-19 11:56:13 +0100
3743cbfecd enable result check in raven_spn fw Stanislaw Kaushanski 2021-03-10 12:05:23 +0100
6bfe684e73 Create separate xspn-fpga FW Add xspn data for different accelerators Johannes Wirth 2021-03-04 11:19:35 +0100
7f8ddf3201 re-implement wait_for_interrupt and get rid of multiplication in check_results for better performance Stanislaw Kaushanski 2021-01-08 09:30:47 +0100
685f25e2ce Passed multi-thread-xspn-vp simulation Stanislaw Kaushanski 2021-01-06 17:27:58 +0100
3d93e4b9a5 Give XSPN the address of the input_data array Stanislaw Kaushanski 2021-01-05 12:56:31 +0100
62cdc0c7b9 error exit Stanislaw Kaushanski 2020-12-30 11:37:06 +0100
4dbbb73f01 restructure for parallel execution Stanislaw Kaushanski 2020-12-14 12:52:05 +0100
0d0d12edff wait for interrupt instead of time delay Stanislaw Kaushanski 2020-12-14 08:43:11 +0100
db22ccbce5 run 10000 XSPN samples Stanislaw Kaushanski 2020-12-11 17:01:35 +0100
06cc727883 200 XSPN samples passed Stanislaw Kaushanski 2020-12-10 15:38:25 +0100
50428965e9 Compile XSPN input and ref data in flash memory. Stanislaw Kaushanski 2020-12-08 17:07:21 +0100
afb8a677f1 check first XSPN result value in FW, add gcc_except_table, replace self-made printf with one from the lib. Stanislaw Kaushanski 2020-12-07 12:55:10 +0100
1d46ef5fea fix raven_spn cdt project Stanislaw Kaushanski 2020-12-07 08:42:38 +0100
01cfbd34fe 1st successful XSPN run. Insert few samples and get one result Stanislaw Kaushanski 2020-12-04 12:34:49 +0100
8249a0417e First configuration of the XSPNController Stanislaw Kaushanski 2020-11-04 17:41:56 +0100
4720c923cd add SPN configuration Stanislaw Kaushanski 2020-10-02 12:10:43 +0200
7d5de86015 start implementing FW to control SPN HW Stanislaw Kaushanski 2020-10-01 17:18:29 +0200
62da6407d8 delay instead of sync Stanislaw Kaushanski 2020-09-17 15:39:30 +0200
0773f51fd3 fix synchronization Stanislaw Kaushanski 2020-09-17 15:19:14 +0200
9e9b644e29 remove unused timer interrupt handler Stanislaw Kaushanski 2020-09-16 15:12:21 +0200
9157a42042 raven FW with data and interrupt transfer (based on bldc project) Stanislaw Kaushanski 2020-09-16 10:28:54 +0200
4c790f8810 add eclipse project Stanislaw Kaushanski 2020-09-09 08:43:20 +0200
ba27721c4d run different code depending on the MHARTID reg value Stanislaw Kaushanski 2020-09-04 12:56:12 +0200
e15e299968 initial FW setup for Raven validation Stanislaw Kaushanski 2020-09-03 11:13:37 +0200
ce24b0f2f2 build hello fw with GCC Toolchain v2020.04.1 (set GPIO_IOF_EN). Remove obsolete function write_hex Stanislaw Kaushanski 2020-09-02 09:13:01 +0200
830c1382b9 add CDT project files, update binaries Eyck Jentzsch 2020-06-18 12:32:41 +0200
27cad2f819 add a few more fw examples Eyck Jentzsch 2020-06-18 12:15:52 +0200
a96cb14dcf Added doxygen comments and refactored a few functions Eyck Jentzsch 2018-10-21 22:48:57 +0200
188bd2b5dd Changed delay calculation for open loop commutation Eyck Jentzsch 2018-10-21 22:29:45 +0200
458c75c5e4 some renaming Eyck Jentzsch 2018-10-21 00:14:14 +0200
9f9088a110 Changed naming of constants and formatting Eyck Jentzsch 2018-10-16 18:51:48 +0200
d6db5f7e04 Fixed rxwm setting as it defines the maximum number of received bytes *before* the interrupt Eyck Jentzsch 2018-10-05 12:23:39 +0200
2a45030414 Added binary for easy jump start Eyck Jentzsch 2018-09-26 09:09:23 +0200
2ebe9541d5 Working version Eyck Jentzsch 2018-09-26 08:07:48 +0200
a4bfa4e679 cleanup of makefiles Eyck Jentzsch 2018-09-25 20:32:56 +0200
038c199c0a cleanup and rename of files Eyck Jentzsch 2018-09-25 19:17:28 +0200
3512206d77 Added hello world project Eyck Jentzsch 2018-09-25 18:31:29 +0200
215767a724 Sync commit Eyck Jentzsch 2018-09-14 14:03:20 +0200
250fa831d0 Initial version of riscv-bldc-forced-communication Eyck Jentzsch 2018-08-08 20:59:10 +0200
42b87091a4 Initial commit DVCon2018 2018-06-23 10:17:35 +0000

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