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619be720d3
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tohost is not required in hifive1 env
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2023-10-16 13:04:11 +02:00 |
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4c86ddd9fb
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removes malloc from default wrapping
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2023-10-10 09:24:06 +02:00 |
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abfde888fb
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merge main into hifive1
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2023-10-04 09:07:16 +02:00 |
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b082091db2
|
adds missing files
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2023-09-30 20:31:58 +02:00 |
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eeb17437ee
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adds missing symbols and sources for libwrap
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2023-09-28 11:51:20 +02:00 |
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cffa693e29
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setup ultra_trail fw based on bare-metal-bsp
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2023-09-27 11:27:02 +02:00 |
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9c0047b3ea
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updates linker script for rtl env
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2023-08-30 15:07:56 +02:00 |
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ca1adccb2b
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fixes TGC5L settings
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2023-08-28 10:01:06 +02:00 |
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3217871752
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extends build system to propagate more settings
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2023-08-20 16:45:54 +02:00 |
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9dd7dcb4ce
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adds TGC5L environment
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2023-08-20 16:39:20 +02:00 |
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3403edcde9
|
adds CMakeLists.txt
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2023-08-20 15:50:00 +02:00 |
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3a3cbf38c3
|
re-adds coremark as submodule
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2023-08-20 15:23:05 +02:00 |
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822696ae0d
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cleanup
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2023-08-20 15:20:39 +02:00 |
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314ceeb072
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rework structure
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2023-08-20 15:00:51 +02:00 |
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4c2208c1ac
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fix wrong exit call
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2022-11-06 17:33:39 +01:00 |
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36a6de6dc0
|
remove raven dirs
|
2022-05-02 13:21:12 +02:00 |
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d2cb78724a
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move RAVEN FW into Validation-VP repo
|
2022-05-02 13:19:36 +02:00 |
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0de438dc52
|
avoid interrupts while printing
|
2022-05-02 09:51:05 +02:00 |
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5f44f8df98
|
Improve wait for interrupt routines
|
2022-04-28 19:20:32 +02:00 |
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02ce96eed8
|
improve interrupt handling
|
2022-04-26 15:29:49 +02:00 |
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46f197c287
|
Add additional registers for input to FW
(number of XSPNs, batch size, iterations)
|
2022-03-11 14:21:25 +01:00 |
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43e2a299db
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fpga_spn: add check if input-/ref-data fits into memory
|
2022-03-10 14:17:52 +01:00 |
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8450f85c93
|
raven_spn: add check if input-/ref-data fits into memory
|
2022-03-10 13:11:10 +01:00 |
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a14ff554b0
|
Move XSPN input and ref data to Validation-VP
|
2022-03-10 13:09:11 +01:00 |
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588ca3c7ba
|
Merge pull request 'Add allocate+free functionality for fpga' (#1) from feature/fpga-alloc-free into master
Reviewed-on: VP/Firmwares#1
|
2022-02-11 16:12:21 +01:00 |
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91f28e9f2b
|
Add allocate+free functionality for fpga
|
2022-01-20 18:22:21 +01:00 |
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446af340c8
|
fpga_spn: use separate reset for DMA
|
2021-11-10 09:51:19 +01:00 |
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89ea594399
|
Update FPGA Firmware for bigger batch sizes
|
2021-07-13 10:51:28 +02:00 |
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a70f5bb09c
|
add wait for both spn interrupts
|
2021-05-17 11:54:37 +02:00 |
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1b09899d2a
|
XSPN hybrid simulation passed in MINRES environment
|
2021-04-22 14:50:21 +02:00 |
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5ba7d5dd24
|
extend spn_checker to comapre the results from 2nd XSPN accelerator
|
2021-04-20 20:36:00 +02:00 |
|
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26d7560891
|
add second XSPN partition
|
2021-04-20 08:30:39 +02:00 |
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|
96de37dbc2
|
increase XSPN load
|
2021-04-14 08:45:21 +02:00 |
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d0eff8c08d
|
longer simulation
|
2021-04-12 13:12:04 +02:00 |
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2a9ce332c7
|
fix hello-world init
|
2021-04-09 11:19:05 +02:00 |
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9578bcfa45
|
Use spn_checker in fpga_spn firmware
|
2021-03-31 16:22:08 +02:00 |
|
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|
f5e0d13891
|
move data handling into snp_checker vp
|
2021-03-26 10:36:15 +01:00 |
|
|
|
b03f1bff4f
|
create snp result checker to enable parallel spn calculation and result comparison
|
2021-03-25 09:36:16 +01:00 |
|
|
|
8c0211f945
|
Cleanup SPN firmwares
|
2021-03-19 11:56:13 +01:00 |
|
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|
3743cbfecd
|
enable result check in raven_spn fw
|
2021-03-10 12:05:23 +01:00 |
|
|
|
6bfe684e73
|
Create separate xspn-fpga FW
Add xspn data for different accelerators
|
2021-03-04 11:19:35 +01:00 |
|
|
|
7f8ddf3201
|
re-implement wait_for_interrupt and get rid of multiplication in
check_results for better performance
|
2021-01-08 09:30:47 +01:00 |
|
|
|
685f25e2ce
|
Passed multi-thread-xspn-vp simulation
|
2021-01-06 17:27:58 +01:00 |
|
|
|
3d93e4b9a5
|
Give XSPN the address of the input_data array
|
2021-01-05 12:56:31 +01:00 |
|
|
|
62cdc0c7b9
|
error exit
Trigger err_exit module to stop the SystemC simualtion if the data check
fails
|
2020-12-30 11:37:06 +01:00 |
|
|
|
4dbbb73f01
|
restructure for parallel execution
|
2020-12-14 12:52:05 +01:00 |
|
|
|
0d0d12edff
|
wait for interrupt instead of time delay
|
2020-12-14 08:43:11 +01:00 |
|
|
|
db22ccbce5
|
run 10000 XSPN samples
|
2020-12-11 17:01:35 +01:00 |
|
|
|
06cc727883
|
200 XSPN samples passed
|
2020-12-10 15:38:25 +01:00 |
|
|
|
50428965e9
|
Compile XSPN input and ref data in flash memory.
Comparison of first 15 samples passed.
|
2020-12-08 17:07:21 +01:00 |
|
