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• f3dc9aea54 adds wrap for scanf in dhrystone develop Eyck Jentzsch 2024-08-28 18:13:40 +0200
• 2f675e9bdd fixes tgc_vp setup in coremark Eyck Jentzsch 2024-06-30 17:26:58 +0200
• 3114cb265a Merge remote-tracking branch 'origin/main' into develop Eyck Jentzsch 2024-06-30 07:54:36 +0200
• 48cfa8d868 appendage main Eyck-Alexander Jentzsch 2024-06-17 18:40:12 +0200
• 64d6045d43 expands README Eyck-Alexander Jentzsch 2024-06-17 18:38:55 +0200
• 095f0ef72f appendage visualize Eyck-Alexander Jentzsch 2024-06-17 18:40:12 +0200
• adb66cfe6e expands README Eyck-Alexander Jentzsch 2024-06-17 18:38:55 +0200
• 765f48e85a fixes target naming Eyck Jentzsch 2024-06-14 20:46:09 +0200
• 1ce18ee1f6 serialzes FW build in cmake build flow Eyck Jentzsch 2024-06-14 17:34:53 +0200
• b4a3a36b2e cleans up Makefile Eyck-Alexander Jentzsch 2024-06-14 12:05:55 +0000
• 2a541997a4 benchmarks/dhrystone/Makefile aktualisiert Eyck Jentzsch 2024-06-14 13:50:22 +0200
• 70d94c1051 CMakeLists.txt aktualisiert Eyck Jentzsch 2024-06-14 13:38:31 +0200
• 0df111f945 cleans up CMakeLists Eyck-Alexander Jentzsch 2024-06-14 10:11:30 +0200
• 9105f5fb14 update include paths gabi_cleanup gabriel 2024-05-31 08:55:49 +0200
• 13fdeb7c36 adds new branch for some benchmark scripts Eyck-Alexander Jentzsch 2024-05-19 17:11:40 +0200
• 4cc156e0d0 Merge branch 'main' of https://git.minres.com/Firmware/Firmwares into main gabriel 2024-04-30 08:46:13 +0200
• 6d33f6b29d merge develop to main in bare-metal-bsp Stanislaw Kaushanski 2024-04-17 08:35:43 +0200
• 48b2f773d0 updates submodule and Jenkins accordingly Eyck-Alexander Jentzsch 2024-04-15 12:19:53 +0200
• cfb5038196 Adds instructions for bear Eyck-Alexander Jentzsch 2024-04-09 10:58:52 +0000
• 877672a5a4 fixes iterations count for benchmarks Eyck Jentzsch 2024-03-25 10:56:34 +0100
• 45b6f24dfc changes coremark build system to use BSP Eyck Jentzsch 2024-03-24 21:10:19 +0100
• 749fab2c01 WIP Eyck Jentzsch 2024-03-24 19:16:24 +0100
• 70ee11ad3d fixes coremark linker setting Eyck Jentzsch 2024-03-21 07:32:20 +0100
• a04e6d3c5b fixes TGCP settings in coremark port Eyck Jentzsch 2024-03-20 12:53:35 +0100
• fca9f04264 Merge remote-tracking branch 'origin/main' into develop Eyck Jentzsch 2024-03-20 12:29:57 +0100
• 06add2e20d reduces dhrystone iterations to 20000 for reasonable RTL sim times Eyck Jentzsch 2024-03-20 12:24:57 +0100
• 2fb5920348 updates coremark portable part to match BSP Eyck Jentzsch 2024-03-20 11:55:48 +0100
• 6d33d0b066 fixes wrone use of bsp in coremark Eyck Jentzsch 2024-03-20 07:46:42 +0100
• d5c672c288 updates coremark build system to use BSP definitions Eyck Jentzsch 2024-03-20 07:38:40 +0100
• fabf7cc588 fixes env name for TGCP Eyck Jentzsch 2024-03-19 14:25:58 +0100
• 34764d3149 updates BSP Eyck Jentzsch 2024-03-14 08:13:10 +0100
• 6498091bfb removes unused file Eyck Jentzsch 2024-03-14 07:58:48 +0100
• aeef0f314a updates bare-metal-bsp Eyck Jentzsch 2024-03-02 16:11:24 +0100
• 5955f54a4d first semihosting integration gabriel 2024-02-26 20:41:13 +0100
• 542e448f17 adds new bsp, updates stubs for mrns vp Eyck-Alexander Jentzsch 2024-02-22 17:11:58 +0100
• 6a6c2007d9 add Jenkinsfile gabriel 2024-01-30 10:08:15 +0100
• 3381b01ec1 replaces bare-metal-bsp with submodule Eyck Jentzsch 2024-01-13 15:33:18 +0100
• 51c8a93336 fixes march definitions for dhrystone and coremark Eyck Jentzsch 2023-12-09 16:38:45 +0100
• fe1136c7ce fixes ISA handling Eyck Jentzsch 2023-12-06 10:00:33 +0100
• 6ff0161882 adds some consistency fixes for variable ISA settings Eyck Jentzsch 2023-12-02 17:41:14 +0100
• 8c1c2766e8 Merge branch 'develop' into main Eyck Jentzsch 2023-12-02 16:27:30 +0100
• 1b8f78fe78 makes build more configurable by CLI Eyck Jentzsch 2023-11-27 10:13:22 +0100
• d20582d7aa fix prci build Stanislaw Kaushanski 2023-11-24 13:06:31 +0100
• 0188d404de fixes hifive1 build feature/hifive1_new Eyck Jentzsch 2023-11-24 11:39:23 +0100
• 77ca8a01b4 add hifive1 Stanislaw Kaushanski 2023-11-24 09:36:53 +0100
• db53376533 Merge branch 'develop' into main Eyck Jentzsch 2023-11-23 18:30:43 +0100
• 41f204e304 adds wrapping to all clib symbols Eyck Jentzsch 2023-11-23 18:29:26 +0100
• acf20a4818 adds missing files Eyck Jentzsch 2023-09-30 20:31:58 +0200
• aab4d1f2a0 adds missing symbols and sources for libwrap Eyck Jentzsch 2023-09-28 11:51:20 +0200
• e91ce0148b adds build targets Eyck Jentzsch 2023-10-30 07:51:59 +0100
• 7093e47c08 adds a CMakeLists.txt message to indicate board selection Eyck Jentzsch 2023-10-27 22:16:21 +0200
• 63f57b9ba1 extends eclipse build configs Eyck Jentzsch 2023-10-26 06:11:12 +0200
• af3a154882 adds tgc-vp environment Eyck Jentzsch 2023-10-25 20:35:44 +0200
• 619be720d3 tohost is not required in hifive1 env feature/hifive1 Stanislaw Kaushanski 2023-10-16 13:04:11 +0200
• 4c86ddd9fb removes malloc from default wrapping Eyck Jentzsch 2023-10-10 09:24:06 +0200
• abfde888fb merge main into hifive1 Stanislaw Kaushanski 2023-10-04 09:07:16 +0200
• b082091db2 adds missing files Eyck Jentzsch 2023-09-30 20:31:58 +0200
• eeb17437ee adds missing symbols and sources for libwrap Eyck Jentzsch 2023-09-28 11:51:20 +0200
• cffa693e29 setup ultra_trail fw based on bare-metal-bsp Stanislaw Kaushanski 2023-09-27 11:27:02 +0200
• 9c0047b3ea updates linker script for rtl env Eyck Jentzsch 2023-08-30 15:07:56 +0200
• ca1adccb2b fixes TGC5L settings Eyck Jentzsch 2023-08-28 10:01:06 +0200
• 3217871752 extends build system to propagate more settings Eyck Jentzsch 2023-08-20 16:45:54 +0200
• 9dd7dcb4ce adds TGC5L environment Eyck Jentzsch 2023-08-20 16:39:20 +0200
• 3403edcde9 adds CMakeLists.txt Eyck Jentzsch 2023-08-20 15:50:00 +0200
• 3a3cbf38c3 re-adds coremark as submodule Eyck Jentzsch 2023-08-20 15:23:05 +0200
• 822696ae0d cleanup Eyck Jentzsch 2023-08-20 15:20:39 +0200
• 314ceeb072 rework structure Eyck Jentzsch 2023-08-20 15:00:51 +0200
• 4c2208c1ac fix wrong exit call Eyck Jentzsch 2022-11-06 17:33:39 +0100
• 36a6de6dc0 remove raven dirs Stanislaw Kaushanski 2022-05-02 13:21:12 +0200
• d2cb78724a move RAVEN FW into Validation-VP repo Stanislaw Kaushanski 2022-05-02 13:19:36 +0200
• 0de438dc52 avoid interrupts while printing Stanislaw Kaushanski 2022-05-02 09:51:05 +0200
• 5f44f8df98 Improve wait for interrupt routines Stanislaw Kaushanski 2022-04-28 19:20:32 +0200
• 02ce96eed8 improve interrupt handling Stanislaw Kaushanski 2022-04-26 15:29:49 +0200
• 46f197c287 Add additional registers for input to FW (number of XSPNs, batch size, iterations) feature/rework_xspn Johannes Wirth 2022-03-11 14:21:25 +0100
• 43e2a299db fpga_spn: add check if input-/ref-data fits into memory Johannes Wirth 2022-03-10 14:17:52 +0100
• 8450f85c93 raven_spn: add check if input-/ref-data fits into memory Johannes Wirth 2022-03-10 13:11:10 +0100
• a14ff554b0 Move XSPN input and ref data to Validation-VP Johannes Wirth 2022-03-10 13:09:11 +0100
• 588ca3c7ba Merge pull request 'Add allocate+free functionality for fpga' (#1) from feature/fpga-alloc-free into master Stanislaw Kaushanski 2022-02-11 16:12:21 +0100
• 91f28e9f2b Add allocate+free functionality for fpga feature/fpga-alloc-free Johannes Wirth 2022-01-20 18:22:21 +0100
• 446af340c8 fpga_spn: use separate reset for DMA Johannes Wirth 2021-11-10 09:51:19 +0100
• 89ea594399 Update FPGA Firmware for bigger batch sizes Johannes Wirth 2021-07-13 10:51:28 +0200
• a70f5bb09c add wait for both spn interrupts Stanislaw Kaushanski 2021-05-17 11:54:37 +0200
• 1b09899d2a XSPN hybrid simulation passed in MINRES environment Stanislaw Kaushanski 2021-04-22 14:50:21 +0200
• 5ba7d5dd24 extend spn_checker to comapre the results from 2nd XSPN accelerator Stanislaw Kaushanski 2021-04-20 20:36:00 +0200
• 26d7560891 add second XSPN partition Stanislaw Kaushanski 2021-04-20 08:30:39 +0200
• 96de37dbc2 increase XSPN load Stanislaw Kaushanski 2021-04-14 08:45:21 +0200
• d0eff8c08d longer simulation Stanislaw Kaushanski 2021-04-12 13:12:04 +0200
• 2a9ce332c7 fix hello-world init Stanislaw Kaushanski 2021-04-09 11:19:05 +0200
• 9578bcfa45 Use spn_checker in fpga_spn firmware Johannes Wirth 2021-03-31 16:22:08 +0200
• f5e0d13891 move data handling into snp_checker vp Stanislaw Kaushanski 2021-03-26 10:36:15 +0100
• b03f1bff4f create snp result checker to enable parallel spn calculation and result comparison Stanislaw Kaushanski 2021-03-25 09:36:16 +0100
• 8c0211f945 Cleanup SPN firmwares Johannes Wirth 2021-03-19 11:56:13 +0100
• 3743cbfecd enable result check in raven_spn fw Stanislaw Kaushanski 2021-03-10 12:05:23 +0100
• 6bfe684e73 Create separate xspn-fpga FW Add xspn data for different accelerators Johannes Wirth 2021-03-04 11:19:35 +0100
• 7f8ddf3201 re-implement wait_for_interrupt and get rid of multiplication in check_results for better performance Stanislaw Kaushanski 2021-01-08 09:30:47 +0100
• 685f25e2ce Passed multi-thread-xspn-vp simulation Stanislaw Kaushanski 2021-01-06 17:27:58 +0100
• 3d93e4b9a5 Give XSPN the address of the input_data array Stanislaw Kaushanski 2021-01-05 12:56:31 +0100
• 62cdc0c7b9 error exit Stanislaw Kaushanski 2020-12-30 11:37:06 +0100
• 4dbbb73f01 restructure for parallel execution Stanislaw Kaushanski 2020-12-14 12:52:05 +0100
• 0d0d12edff wait for interrupt instead of time delay Stanislaw Kaushanski 2020-12-14 08:43:11 +0100