Merge remote-tracking branch 'origin/main' into develop

This commit is contained in:
Eyck Jentzsch 2024-06-30 07:54:36 +02:00
commit 3114cb265a
15 changed files with 75 additions and 365 deletions

3
.gitignore vendored
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@ -151,3 +151,6 @@ compile_commands.json
CTestTestfile.cmake
*.dump
.vscode/c_cpp_properties.json
semihosting_test/build/semihosting_test
semihosting_test/build/Makefile

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@ -4,16 +4,8 @@ endif()
if (NOT DEFINED ISA)
set(ISA imc)
endif()
message(STATUS "Building firmware using ${BOARD} board configuration")
add_custom_target(fw-hello-world ALL
COMMAND make -C ${riscvfw_SOURCE_DIR}/hello-world BOARD=${BOARD} ISA=${ISA}
USES_TERMINAL
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
add_custom_target(fw-dhrystone ALL
COMMAND make -C ${riscvfw_SOURCE_DIR}/benchmarks/dhrystone BOARD=${BOARD} ISA=${ISA}
USES_TERMINAL
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
add_custom_target(fw-coremark ALL
COMMAND make -C ${riscvfw_SOURCE_DIR}/benchmarks/coremark/cm PORT_DIR=../tgc BOARD=${BOARD} ISA=${ISA}
message(STATUS "Building firmware using ${BOARD} board configuration and isa ${ISA}")
add_custom_target(fw-common ALL
COMMAND make -C hello-world BOARD=${BOARD} ISA=${ISA} && make -C benchmarks/dhrystone BOARD=${BOARD} ISA=${ISA} && make -C benchmarks/coremark BOARD=${BOARD} ISA=${ISA}
USES_TERMINAL
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})

4
Jenkinsfile vendored
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@ -47,13 +47,13 @@ pipeline {
stage('make TGC5L') {steps { make_hello("TGC5L")}}
stage('make rtl') {steps { make_hello("rtl")}}
stage('make ehrenberg') {steps { make_hello("ehrenberg")}}
stage('make tgc-vp') {steps { make_hello("tgc-vp")}}*/
stage('make tgc_vp') {steps { make_hello("tgc_vp")}}*/
stage('make hello-world') {
matrix {
axes {
axis{
name 'BOARD'
values 'iss', 'hifive1', 'TGCP', 'ehrenberg', 'rtl', 'tgc-vp'
values 'iss', 'hifive1', 'TGCP', 'ehrenberg', 'rtl', 'tgc_vp'
}
}
stages {

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@ -1,2 +1,25 @@
# Firmware
# MINRES Firmware Repository
## Structure
This repository comes with several executables ready to be built, such as `hello-world` or `coremark` and `dhrystone` in the `benchmark` directory.
Creating the executables in the easiest way possible is done by calling `make`in the corresponding directory.
## Prerequisite
This repository requires `riscv64-unknown-elf-gcc` to be located in `$PATH`.
## How to Use
When compiling executables, the target platform needs to be specified using the 'BOARD' variable. When compiling for the TGC5C for example, use `make BOARD=tgc_vp`, when compiling for RTL `make BOARD=rtl`. The default value for the Board variable is 'iss'.
The arch can be set with the 'ISA' variable, the default value is 'imc'.
When compiling for the TGC5A VP for example, the call to create the correct binary is the following:
```
make BOARD=tgc_vp ISA=e
```
## Useful information
Using `bear -- <build-command>` will cause a compile_commands.json to be emitted. This allows using completion tools like clangd.
## Current Limitations
Currently, this repository only supports creation of 32-bit executables (Even when setting the `RISCV_ARCH` and `RISCV_ABI` manually).
Compiling for the 'e' extension / ISA together with any other extension (`ISA=emc` for example), requires setting the `RISCV_ABI=ilp32e` explicitly.
When switching ABI or ARCH ensure that object files in the corresponding 'env' dir in the 'bare-metal-bsp' submodule are removed, so they get created with the appropriate flags (namely the 'init.o' file).

@ -1 +1 @@
Subproject commit d5304739fa8db6a3c16e417c9bc15b6fad749136
Subproject commit 87dc0ec2304adcb94a25b397a357aadae1304867

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@ -1,3 +1,4 @@
*.o
*.elf
*.log
*.log
/coremark.*

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@ -0,0 +1,33 @@
TARGET := coremark
ISA?=imc
ITERATIONS?=600 # 300 for TGC
ASM_SRCS :=
C_SRCS := core_list_join.c core_main.c core_matrix.c core_state.c core_util.c core_portme.c ee_printf.c
HEADERS := cm/coremark.h
vpath %.c cm
BOARD?=iss
LINK_TARGET=link
RISCV_ARCH:=rv32$(ISA)
ifeq ($(ISA),e)
RISCV_ABI:=ilp32e
else
RISCV_ABI:=ilp32
endif
PORT_CFLAGS = -DPERFORMANCE_RUN=1 -DCLOCKS_PER_SEC=10000000 -Wno-pointer-to-int-cast -Wno-int-to-pointer-cast
PORT_CFLAGS+= -g -O3 -fno-common -funroll-loops -finline-functions -falign-functions=16 -falign-jumps=4 -falign-loops=4 -finline-limit=1000 -fno-if-conversion2 -fselective-scheduling -fno-crossjumping -freorder-blocks-and-partition
FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
CFLAGS = $(PORT_CFLAGS) -I. -Icm -DFLAGS_STR=\"$(FLAGS_STR)\"
CFLAGS += -DITERATIONS=$(ITERATIONS)
LDFLAGS := -g -Wl,--wrap=scanf -Wl,--wrap=printf -Wl,--wrap=exit -lgcc -lm
TOOL_DIR=$(dir $(compiler))
BSP_BASE = ../../bare-metal-bsp
include $(BSP_BASE)/env/common-gcc.mk

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@ -673,8 +673,6 @@ uart_send_char(char c)
}
#elif defined(BOARD_iss)
*((uint32_t*) 0xFFFF0000) = c;
#elif defined(BOARD_TGCP)
//TODO: implement
#else
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
UART0_REG(UART_REG_TXFIFO) = c;

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@ -1,102 +0,0 @@
# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# Original Author: Shay Gal-on
#File : core_portme.mak
ISA?=imc
BOARD?=iss
RISCV_ARCH:=rv32$(ISA)_zicsr_zifencei
ifeq ($(ISA),e)
RISCV_ABI:=ilp32e
else
RISCV_ABI:=ilp32
endif
BSP_BASE = ../../../bare-metal-bsp
TRIPLET?=riscv64-unknown-elf
# Flag : OUTFLAG
# Use this flag to define how to to get an executable (e.g -o)
OUTFLAG= -o
# Flag : CC
# Use this flag to define compiler to use
CC = $(TRIPLET)-gcc
# Flag : LD
# Use this flag to define compiler to use
LD = $(TRIPLET)-gcc
# Flag : AS
# Use this flag to define compiler to use
AS = $(TRIPLET)-as
# Flag : CFLAGS
# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
PORT_CFLAGS = -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -O3 -DCLOCKS_PER_SEC=10000000 -nostdlib -nostartfiles -nodefaultlibs \
-funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto -g
FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\" -I$(BSP_BASE)/env/$(BOARD)
#Flag : LFLAGS_END
# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts).
# Note : On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.
SEPARATE_COMPILE=1
# Flag : SEPARATE_COMPILE
# You must also define below how to create an object file, and how to link.
OBJOUT = -o
LFLAGS = -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -g
#--specs=nano.specs -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
ASFLAGS =
OFLAG = -o
COUT = -c
LFLAGS_END =
# Flag : PORT_SRCS
# Port specific source files can be added here
# You may also need cvt.c if the fcvt functions are not provided as intrinsics by your compiler!
PORT_SRCS = $(PORT_DIR)/core_portme.c $(PORT_DIR)/ee_printf.c
vpath %.c $(PORT_DIR)
vpath %.s $(PORT_DIR)
PORT_OBJS = core_portme.o ee_printf.o
# Flag : LOAD
# For a simple port, we assume self hosted compile and run, no load needed.
# Flag : RUN
# For a simple port, we assume self hosted compile and run, simple invocation of the executable
LOAD = echo ""
RUN = echo ""
OEXT = .o
EXE = .elf
$(OPATH)$(PORT_DIR)/%$(OEXT) : %.c
$(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@
$(OPATH)%$(OEXT) : %.c
$(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@
$(OPATH)$(PORT_DIR)/%$(OEXT) : %.s
$(AS) $(ASFLAGS) $< $(OBJOUT) $@
# Target : port_pre% and port_post%
# For the purpose of this simple port, no pre or post steps needed.
.PHONY : port_prebuild port_postbuild port_prerun port_postrun port_preload port_postload
port_pre% port_post% :
# FLAG : OPATH
# Path to the output folder. Default - current folder.
OPATH = ./
MKDIR = mkdir -p
dist-clean: clean
rm -f *.o

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@ -1,241 +0,0 @@
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
OUTPUT_ARCH(riscv)
MEMORY
{
RAM (rwx) : ORIGIN = 0x0, LENGTH = 128M
}
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@ -1,11 +1,12 @@
TARGET := dhrystone
ISA?=imc
ITERATIONS?=50000 # 20000 for TGC
ASM_SRCS :=
C_SRCS := dhry_stubs.c dhry_1.c dhry_2.c
HEADERS := dhry.h
BOARD=iss
BOARD?=iss
LINK_TARGET=link
RISCV_ARCH:=rv32$(ISA)
ifneq (,$(findstring e,$(ISA)))
@ -14,9 +15,8 @@ else
RISCV_ABI:=ilp32
endif
# '-lgcc -lm' are needed to add softfloat routines
CFLAGS := -g -march=$(RISCV_ARCH)_zicsr_zifencei -mabi=$(RISCV_ABI) -mcmodel=medlow -O3 -DHZ=32768 -DTIME -DNO_INIT -fno-inline -fno-builtin-printf -fno-common -Wno-implicit \
CFLAGS := -g -O3 -DITERATIONS=$(ITERATIONS) -DHZ=32768 -DTIME -DNO_INIT -fno-inline -fno-builtin-printf -fno-common -Wno-implicit \
-funroll-loops -fpeel-loops -fgcse-sm -fgcse-las
LDFLAGS := -g -march=$(RISCV_ARCH)_zicsr_zifencei -mabi=$(RISCV_ABI) -mcmodel=medlow -Wl,--wrap=scanf -Wl,--wrap=printf -Wl,--wrap=exit -lgcc -lm
TOOL_DIR=$(dir $(compiler))

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@ -1,4 +1,7 @@
#include "platform.h"
#ifndef ITERATIONS
#define ITERATIONS 20000
#endif
/* The functions in this file are only meant to support Dhrystone on an
* embedded RV32 system and are obviously incorrect in general. */
@ -11,7 +14,7 @@ long time(void)
// set the number of dhrystone iterations
void __wrap_scanf(const char* fmt, int* n)
{
*n = 20000;
*n = ITERATIONS;
}
extern volatile uint32_t tohost;