move data handling into snp_checker vp
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@ -6,10 +6,6 @@
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using spn = spn_regs<0x90000000>;
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using spn_checker = spn_checker_regs<0x10040000>;
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// huge arrays of XSPN input and referance data
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extern std::array<uint8_t, 50000> input_data;
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extern std::array<double, 10000> ref_data;
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void run_xspn(int in_addr, int out_addr, int num_samples, int in_beats, int out_beats) {
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spn::mode_reg() = 0;
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spn::input_length_reg() = num_samples; // each sample consists of 5 uint8 values
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@ -53,7 +49,7 @@ int main() {
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printf("Result Bytes: %d\n", result_bytes);
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uint32_t step = 2000;
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uint32_t step = 10000;
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uint32_t iterations = 5;
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uint32_t in_beats = (step * sample_bytes) / axi_bytes;
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@ -61,19 +57,24 @@ int main() {
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uint32_t out_beats = (step * result_bytes) / axi_bytes;
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if (out_beats * axi_bytes < step * result_bytes) out_beats++;
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int in_addr = (int)input_data.data();
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int out_addr = 0x800B0000;
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int in_addr = 0x20010000; // place input samples in the SPI memory
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int out_addr = 0x20210000;
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spn_checker::ref_addr_reg() = (int)ref_data.data();
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spn_checker::addr_reg() = out_addr;
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// inject SPN input data
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spn_checker::input_addr_reg() = in_addr;
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spn_checker::num_input_samples_reg() = sample_bytes * step * iterations;
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spn_checker::start_data_trans_reg() = 1;
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spn_checker::output_addr_reg() = out_addr;
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for (int k = 0; k < iterations*step; k+=step) {
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run_xspn(in_addr, out_addr, step, in_beats, out_beats);
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wait_for_interrupt();
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printf("XSPN finished\n");
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spn_checker::offset_reg() = k;
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spn_checker::length_reg() = step;
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spn_checker::start_reg() = 1;
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spn_checker::start_result_check_reg() = 1;
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spn::interrupt_reg() = 1;
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in_addr += step * sample_bytes; // 5 bytes in each sample
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@ -32,18 +32,18 @@
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// * spn_regs.h Author: <RDL Generator>
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef _SPN_CNTL_REGS_H_
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#define _SPN_CNTL_REGS_H_
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#pragma once
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#include <util/bit_field.h>
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#include <cstdint>
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#define SPN_CNTL_REG_START 0x00
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#define SPN_CNTL_REG_OFFSET 0x10
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#define SPN_CNTL_REG_LENGTH 0x20
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#define SPN_CNTL_REG_ADDR 0x30
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#define SPN_CNTL_REG_REF_ADDR 0x40
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#define SPN_CNTL_REG_START_RESULT_CHECK 0x00
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#define SPN_CNTL_REG_OFFSET 0x10
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#define SPN_CNTL_REG_LENGTH 0x20
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#define SPN_CNTL_REG_OUTPUT_ADDR 0x30
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#define SPN_CNTL_REG_INPUT_ADDR 0x40
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#define SPN_CNTL_REG_NUM_INPUT_SAMPLES 0x50
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#define SPN_CNTL_REG_START_DATA_TRANS 0x60
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template<uint32_t BASE_ADDR>
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class spn_checker_regs {
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@ -52,19 +52,22 @@ public:
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// BEGIN_BF_DECL(start_t, uint32_t);
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// BF_FIELD(start, 0, 1);
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// END_BF_DECL() r_start;
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uint32_t r_start;
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uint32_t r_start_result_check;
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uint32_t r_offset;
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uint32_t r_length;
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uint32_t r_addr;
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uint32_t r_output_addr;
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uint32_t r_ref_addr;
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uint32_t r_input_addr;
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uint32_t r_num_input_samples;
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static inline uint32_t& start_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_START);
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uint32_t r_start_data_trans;
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static inline uint32_t& start_result_check_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_START_RESULT_CHECK);
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}
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static inline uint32_t & offset_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_LENGTH);
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}
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static inline uint32_t & addr_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_ADDR);
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static inline uint32_t & output_addr_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_OUTPUT_ADDR);
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}
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static inline uint32_t & ref_addr_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_REF_ADDR);
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static inline uint32_t & input_addr_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_INPUT_ADDR);
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}
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static inline uint32_t & num_input_samples_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_NUM_INPUT_SAMPLES);
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}
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static inline uint32_t& start_data_trans_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_START_DATA_TRANS);
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}
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};
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#endif // _SPN_CNTL_REGS_H_
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