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6e52af168b
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adds faster decoding to tcc and cleans up others
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2023-07-29 11:42:46 +02:00 |
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bd0d15f3a2
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updates template for faster instruction decoding
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2023-07-23 08:10:57 +02:00 |
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21d3250e1a
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changes templates
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2023-07-09 16:53:59 +02:00 |
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a123beb301
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fixes duplicate variable declaration and templates
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2023-05-27 10:20:49 +02:00 |
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00b0f101ac
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adapts to changes of instrumentation interface in dbt-rise-core
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2023-04-28 20:38:07 +02:00 |
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d881cb6e63
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fix data width of generated code
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2023-03-26 12:12:34 +02:00 |
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207dbf1071
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fixes out of range access for register alias names
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2023-02-17 06:28:30 +01:00 |
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65dca13b42
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fixes WFI miss of interrupt
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2023-01-14 17:40:21 +01:00 |
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7113683ee0
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moves pending interrupt check before handling trap thus saving 1 cycle
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2022-10-15 10:47:35 +02:00 |
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00e02bf565
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adds support for different branch types in tracing
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2022-08-08 06:30:37 +02:00 |
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0833198d34
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aads missing windows compat firx to template
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2022-07-23 14:36:23 +02:00 |
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feaa49d367
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removes decoder again as there is some issue
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2022-06-20 00:39:11 +02:00 |
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f096b15dbd
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factors decoder into separate component
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2022-06-19 13:17:31 +02:00 |
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5d481eb79d
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fix generation of non-exception code
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2022-05-30 22:04:16 +02:00 |
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52ed8b81a6
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fixed template to work with previous code generator
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2022-05-30 14:08:02 +02:00 |
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0c542d42aa
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separate generated sources
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2022-05-21 12:48:28 +02:00 |
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df16378605
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update template for changed code generator
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2022-05-18 19:10:34 +02:00 |
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9d9008a3a2
|
fix pointer mess
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2022-04-26 15:35:17 +02:00 |
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a92b84bef4
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add code word access for ISS plugins
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2022-04-25 14:18:19 +02:00 |
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2e670c4d03
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change interpreter structure
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2022-03-06 15:11:38 +01:00 |
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521f40a3d6
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refactored interpreter backend structure
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2022-03-05 20:59:17 +01:00 |
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ef2a4df925
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simplify spawn block handling
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2022-01-31 23:40:31 +01:00 |
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3563ba80d0
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add spawn blocks
|
2022-01-12 07:21:16 +01:00 |
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c42e336509
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fix proper debug mode handling (#267 & #268)
|
2021-11-07 17:48:44 +01:00 |
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334d3fb296
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adapt to SCC changes
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2021-10-21 22:53:16 +02:00 |
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1d13c8196e
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fix wrong PGMASK usage
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2021-10-11 10:40:01 +02:00 |
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2f15d9676e
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fix unaligned instr fetch behavior
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2021-09-30 19:27:46 +02:00 |
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174259155d
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add support for non-compressed ISA
|
2021-09-23 21:09:52 +02:00 |
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d95846a849
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fix trap handling if illegal fetch (PMP) and U-mode CSRs
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2021-08-01 17:23:22 +02:00 |
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e68918c2e8
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fix instruction decode
|
2021-07-09 07:37:12 +02:00 |
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23b9741adf
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refine and fix TGC_C iss to becoem compliant
|
2021-06-29 11:51:30 +02:00 |
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e432dd8208
|
fix handling of exceptions while accessing address spaces
|
2021-06-07 22:22:36 +02:00 |
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aaceecd5dc
|
fix mu_p platform features and CSRs
|
2021-05-17 09:20:09 +02:00 |
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32e4aa83b8
|
use extracted variables
|
2021-03-27 09:36:52 +00:00 |
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78c7064295
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update groovy template to extract used registers
|
2021-03-26 08:24:45 +00:00 |
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b0bcb7febb
|
small fixes for robustness and readability
|
2021-03-22 22:47:30 +00:00 |
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4e0f20eba0
|
rework abort conditions
|
2021-03-17 19:32:57 +00:00 |
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80057eef32
|
fix RVC description bugs, remove paged fetch
|
2021-03-13 10:46:41 +00:00 |
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a6691bcd3c
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update generated code with correct sign extension
|
2021-03-09 10:21:36 +00:00 |
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c251fe15d5
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fix desscriptions to conform to ISA spec version 20191213 and TGF-C
|
2021-03-07 10:51:00 +00:00 |
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9534d58d01
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regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
|
2021-03-01 06:26:33 +00:00 |
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34bb8e62ae
|
generate working ISS from CoreDSL 2.0
|
2021-02-06 14:47:06 +00:00 |
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c4da47cedd
|
integrate code generation into build process (first attempt)
|
2020-12-30 07:29:52 +00:00 |
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