gabriel
|
6a6c2007d9
|
add Jenkinsfile
|
2024-01-30 10:08:15 +01:00 |
 Eyck Jentzsch
|
3381b01ec1
|
replaces bare-metal-bsp with submodule
|
2024-01-13 15:37:10 +01:00 |
|
Eyck Jentzsch
|
51c8a93336
|
fixes march definitions for dhrystone and coremark
|
2023-12-09 16:38:45 +01:00 |
|
Eyck Jentzsch
|
6ff0161882
|
adds some consistency fixes for variable ISA settings
|
2023-12-02 17:41:14 +01:00 |
|
Eyck Jentzsch
|
8c1c2766e8
|
Merge branch 'develop' into main
|
2023-12-02 16:27:30 +01:00 |
|
Eyck Jentzsch
|
1b8f78fe78
|
makes build more configurable by CLI
|
2023-11-27 10:13:22 +01:00 |
 Stanislaw Kaushanski
|
d20582d7aa
|
fix prci build
|
2023-11-24 13:06:31 +01:00 |
|
Eyck Jentzsch
|
0188d404de
|
fixes hifive1 build
|
2023-11-24 11:39:23 +01:00 |
|
Stanislaw Kaushanski
|
77ca8a01b4
|
add hifive1
|
2023-11-24 09:36:53 +01:00 |
|
Eyck Jentzsch
|
db53376533
|
Merge branch 'develop' into main
|
2023-11-23 18:30:43 +01:00 |
|
Eyck Jentzsch
|
41f204e304
|
adds wrapping to all clib symbols
|
2023-11-23 18:29:26 +01:00 |
|
Eyck Jentzsch
|
acf20a4818
|
adds missing files
|
2023-11-23 18:14:41 +01:00 |
|
Eyck Jentzsch
|
aab4d1f2a0
|
adds missing symbols and sources for libwrap
|
2023-11-23 18:14:41 +01:00 |
|
Eyck Jentzsch
|
e91ce0148b
|
adds build targets
|
2023-10-30 07:51:59 +01:00 |
|
Eyck Jentzsch
|
7093e47c08
|
adds a CMakeLists.txt message to indicate board selection
|
2023-10-27 22:16:21 +02:00 |
|
Eyck Jentzsch
|
63f57b9ba1
|
extends eclipse build configs
|
2023-10-26 06:11:12 +02:00 |
|
Eyck Jentzsch
|
af3a154882
|
adds tgc-vp environment
|
2023-10-25 20:35:44 +02:00 |
|
Eyck Jentzsch
|
b082091db2
|
adds missing files
|
2023-09-30 20:31:58 +02:00 |
|
Eyck Jentzsch
|
eeb17437ee
|
adds missing symbols and sources for libwrap
|
2023-09-28 11:51:20 +02:00 |
|
Eyck Jentzsch
|
9c0047b3ea
|
updates linker script for rtl env
|
2023-08-30 15:07:56 +02:00 |
|
Eyck Jentzsch
|
ca1adccb2b
|
fixes TGC5L settings
|
2023-08-28 10:01:06 +02:00 |
|
Eyck Jentzsch
|
3217871752
|
extends build system to propagate more settings
|
2023-08-20 16:45:54 +02:00 |
|
Eyck Jentzsch
|
9dd7dcb4ce
|
adds TGC5L environment
|
2023-08-20 16:39:20 +02:00 |
|
Eyck Jentzsch
|
3403edcde9
|
adds CMakeLists.txt
|
2023-08-20 15:50:00 +02:00 |
|
Eyck Jentzsch
|
3a3cbf38c3
|
re-adds coremark as submodule
|
2023-08-20 15:23:05 +02:00 |
|
Eyck Jentzsch
|
822696ae0d
|
cleanup
|
2023-08-20 15:20:39 +02:00 |
|
Eyck Jentzsch
|
314ceeb072
|
rework structure
|
2023-08-20 15:00:51 +02:00 |
|
Eyck Jentzsch
|
4c2208c1ac
|
fix wrong exit call
|
2022-11-06 17:33:39 +01:00 |
|
Stanislaw Kaushanski
|
36a6de6dc0
|
remove raven dirs
|
2022-05-02 13:21:12 +02:00 |
|
Stanislaw Kaushanski
|
d2cb78724a
|
move RAVEN FW into Validation-VP repo
|
2022-05-02 13:19:36 +02:00 |
|
Stanislaw Kaushanski
|
0de438dc52
|
avoid interrupts while printing
|
2022-05-02 09:51:05 +02:00 |
|
Stanislaw Kaushanski
|
5f44f8df98
|
Improve wait for interrupt routines
|
2022-04-28 19:20:32 +02:00 |
|
Stanislaw Kaushanski
|
02ce96eed8
|
improve interrupt handling
|
2022-04-26 15:29:49 +02:00 |
 Johannes Wirth
|
46f197c287
|
Add additional registers for input to FW
(number of XSPNs, batch size, iterations)
|
2022-03-11 14:21:25 +01:00 |
|
Johannes Wirth
|
43e2a299db
|
fpga_spn: add check if input-/ref-data fits into memory
|
2022-03-10 14:17:52 +01:00 |
|
Johannes Wirth
|
8450f85c93
|
raven_spn: add check if input-/ref-data fits into memory
|
2022-03-10 13:11:10 +01:00 |
|
Johannes Wirth
|
a14ff554b0
|
Move XSPN input and ref data to Validation-VP
|
2022-03-10 13:09:11 +01:00 |
|
Stanislaw Kaushanski
|
588ca3c7ba
|
Merge pull request 'Add allocate+free functionality for fpga' (#1) from feature/fpga-alloc-free into master
Reviewed-on: VP/Firmwares#1
|
2022-02-11 16:12:21 +01:00 |
|
Johannes Wirth
|
91f28e9f2b
|
Add allocate+free functionality for fpga
|
2022-01-20 18:22:21 +01:00 |
|
Johannes Wirth
|
446af340c8
|
fpga_spn: use separate reset for DMA
|
2021-11-10 09:51:19 +01:00 |
|
Johannes Wirth
|
89ea594399
|
Update FPGA Firmware for bigger batch sizes
|
2021-07-13 10:51:28 +02:00 |
|
Stanislaw Kaushanski
|
a70f5bb09c
|
add wait for both spn interrupts
|
2021-05-17 11:54:37 +02:00 |
|
Stanislaw Kaushanski
|
1b09899d2a
|
XSPN hybrid simulation passed in MINRES environment
|
2021-04-22 14:50:21 +02:00 |
|
Stanislaw Kaushanski
|
5ba7d5dd24
|
extend spn_checker to comapre the results from 2nd XSPN accelerator
|
2021-04-20 20:36:00 +02:00 |
|
Stanislaw Kaushanski
|
26d7560891
|
add second XSPN partition
|
2021-04-20 08:30:39 +02:00 |
|
Stanislaw Kaushanski
|
96de37dbc2
|
increase XSPN load
|
2021-04-14 08:45:21 +02:00 |
|
Stanislaw Kaushanski
|
d0eff8c08d
|
longer simulation
|
2021-04-12 13:12:04 +02:00 |
|
Stanislaw Kaushanski
|
2a9ce332c7
|
fix hello-world init
|
2021-04-09 11:19:05 +02:00 |
|
Johannes Wirth
|
9578bcfa45
|
Use spn_checker in fpga_spn firmware
|
2021-03-31 16:22:08 +02:00 |
|
Stanislaw Kaushanski
|
f5e0d13891
|
move data handling into snp_checker vp
|
2021-03-26 10:36:15 +01:00 |