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8db0cc5d05
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removes clutter
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2023-09-23 10:34:58 +02:00 |
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212fb1c8ff
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adds tracing functionality
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2023-09-22 12:40:35 +02:00 |
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633c0d21a0
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Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop
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2023-09-20 15:17:43 +02:00 |
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51f6fbe0dd
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applies newest CoreDSL changes
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2023-09-20 15:12:03 +02:00 |
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de45d06878
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adds initial working version of llvm backend
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2023-09-19 16:26:07 +02:00 |
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b5d915f389
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fixes compile issues from merge
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2023-08-30 15:49:28 +02:00 |
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813b40409d
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Merge branch 'develop' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop
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2023-08-30 10:05:42 +02:00 |
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c8a4a4c736
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renames core(s)
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2023-08-28 07:09:55 +02:00 |
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20e920338c
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removes v2p function
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2023-08-04 13:08:10 +02:00 |
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24de2bbdf5
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purge build system
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2023-07-30 13:55:57 +02:00 |
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957145ca84
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add SystemC ISS factory
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2023-07-14 11:11:03 +02:00 |
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0b719a4b57
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fixes literal type
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2023-07-10 20:39:02 +02:00 |
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250ea3c980
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extends factory to support SystemC core wrapper
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2023-07-09 18:19:59 +02:00 |
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7b31b8ca8e
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adds updated generated files
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2023-07-09 16:58:47 +02:00 |
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87b4082633
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Merge branch 'tmp' into develop
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2023-07-03 14:22:50 +02:00 |
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4dbc7433a5
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fixes cause CSR handling
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2023-06-12 17:38:56 +02:00 |
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99a9970ddd
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fixes sysc compile issues
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2023-06-12 09:58:24 +02:00 |
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0b5de90fb1
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changes [m|u]cause rd/wr handling
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2023-06-11 18:29:58 +02:00 |
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2281ec4144
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corrects errors and adds new backend and
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2023-06-05 15:18:27 +02:00 |
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11c481cec2
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adds verbosity to error
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2023-06-05 15:17:16 +02:00 |
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a123beb301
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fixes duplicate variable declaration and templates
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2023-05-27 10:20:49 +02:00 |
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ee6218279e
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adapts to latest code gen changes
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2023-05-25 12:52:30 +02:00 |
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6ed7eafc5d
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adds inital version of tcc backend
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2023-05-16 21:51:35 +02:00 |
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32848ec396
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fixes build system and typo in wt_cache
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2023-05-13 16:57:01 +02:00 |
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aa70d8a54a
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fixes CLIC to match clicinfo description in CLIC spec 11.04.2023
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2023-05-02 17:22:13 +02:00 |
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d990f1cf5d
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fixes reading of 64bit CSR register
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2023-05-01 22:23:35 +02:00 |
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1672b01e62
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adds WT cache functionality as mixin
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2023-04-28 20:38:07 +02:00 |
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00b0f101ac
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adapts to changes of instrumentation interface in dbt-rise-core
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2023-04-28 20:38:07 +02:00 |
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f626ee2684
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fixes privilege wrapper for M/U to cope with 64bit
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2023-04-05 15:38:25 +02:00 |
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98dd329833
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fixes CSR access rights
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2023-04-04 09:23:08 +02:00 |
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6213445bc4
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fixes 64bit behavior of CSR regs
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2023-03-27 12:04:43 +02:00 |
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2e4faa4d50
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fixes mstatus mask
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2023-03-25 09:14:56 +01:00 |
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8e1951f298
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adds 64bit mstatus
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2023-03-23 07:47:21 +01:00 |
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7efa924510
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fixes m/uintstatus read
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2023-03-17 10:51:39 +01:00 |
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febbc4fff0
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fixes m/uintstatus read
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2023-03-17 10:23:05 +01:00 |
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39b2788b7e
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implements and fixes CLIC CSR behavior
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2023-03-17 09:09:09 +01:00 |
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a943dd3bdf
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fixes wrong array size which led to unintended CSR definitions
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2023-03-15 14:16:08 +01:00 |
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fedbff5971
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fixes xcause and u-mode clic CSRs
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2023-03-15 12:27:39 +01:00 |
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c2758e8321
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removes mscratchcsw from CLIC feature
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2023-03-15 09:07:00 +01:00 |
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8be5fe71df
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fixes template name typo
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2023-03-12 07:42:09 +01:00 |
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3f7ce41b9d
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fixes CLIC mtvt register behavior
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2023-03-11 14:03:03 +01:00 |
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ad1cbedf00
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adds back missing max irq functions
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2023-03-11 12:47:10 +01:00 |
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83f54b5074
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fixes CLICCFG settings
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2023-03-11 08:48:03 +01:00 |
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a83928fd8c
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fixes CSR/CLIC implementation
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2023-03-10 20:40:21 +01:00 |
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62c118e501
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fixes CSR to match latest fast interrupts spec
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2023-01-20 16:21:04 +01:00 |
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1a0fc4bd5d
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fixes wrong mcounteren in M-mode only priv wrapper
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2022-10-10 08:59:27 +02:00 |
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40d1966e9a
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fixes pending irq within irq hander behavior
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2022-10-08 11:20:52 +02:00 |
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a977200284
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cleans up priv wrappers
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2022-10-05 08:58:57 +02:00 |
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6ba7c82f80
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fixes wrapper definitions for hwl cores
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2022-09-26 13:31:46 +02:00 |
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ad7bb28b4c
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fixes write mask of clic memory mapped registers
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2022-09-17 12:15:19 +02:00 |
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