Commit Graph

133 Commits

Author SHA1 Message Date
0698b604fd add TCC backend 2020-05-29 08:52:55 +02:00
264053a8d6 [WIP] add next increment for TCC 2020-04-17 19:23:43 +02:00
ae1c0b99fe [WIP] basic infrastructure working 2020-04-13 17:03:50 +02:00
8cdf50d69e [WIP] implement basic infrastructure 2020-04-12 12:44:30 +02:00
50663a2fbc [WIP] integrate tcc conan package 2020-04-10 17:14:04 +02:00
15f4c059e6 [WIP] first working version 2020-01-12 18:19:48 +01:00
e483887c43 [WIP] Cleanup of namespaces etc to get compile clean 2020-01-10 11:12:20 +01:00
fd2e40bfd2 Initial setup 2020-01-10 07:24:00 +01:00
f357e563f2 Merge branch 'tmp' into develop 2020-01-09 19:44:52 +01:00
116ed9bb5c [WIP] started to add TinyCC backend 2020-01-09 19:43:17 +01:00
c39460ee34 [WIP] started to add TinyCC backend 2020-01-09 19:37:17 +01:00
8b9775e06b Changed namespaces for LLVM related stuff 2020-01-07 16:38:31 +01:00
3c30c47c90 Updated description and added reference to VP 2019-12-10 04:45:04 +00:00
d037141d98 Fixed C++11 compatibility 2019-07-16 15:52:34 +02:00
1947a2114f Fixed FMT header define 2019-07-14 16:51:14 +02:00
4ea6d73d86 Updated README to reflect latest cahnges 2019-06-29 13:00:58 +00:00
e999d95623 Merge branch 'develop'
Conflicts:
	dbt-core
	platform/src/sysc/plic.cpp
	sc-components
2019-06-28 21:29:35 +02:00
cc21afaaff Fixed CMakeLists.txt dependencies 2019-06-28 21:25:23 +02:00
7f06bba239 Fixed time csr handling 2019-06-28 20:58:02 +02:00
d93c2feec4 Cleanup dependencies 2019-06-18 19:20:43 +00:00
2758933c16 Modernized CMake 2019-06-11 19:22:07 +00:00
67d9beb7bd reorganized layout to only contain risc-v stuff 2019-06-11 16:49:37 +00:00
eb8365f4c3 Updated SC-Components 2019-04-11 05:40:02 +00:00
cb3a0d8411 Merge branch 'develop' 2019-01-10 11:15:02 +00:00
eyck
3e8583977a Refactored core descriptions 2019-01-10 10:58:13 +00:00
eyck
f69b529cab Fixed implementation of RV64 so that remaining riscv-test pass 2019-01-10 10:35:20 +00:00
d5d236bf10 Adapted changes in SCC 2018-11-24 21:38:02 +01:00
769610d6fc Improved disassembly of running ISS 2018-11-24 20:29:24 +01:00
df03e90181 Adapted to vm_base refactoring (move into llvm package) 2018-11-22 20:28:36 +01:00
58a446e6bc Refoctored to to move SystemC wrapper into riscv library 2018-11-19 20:39:11 +01:00
a576fdf8e5 Cleanup of templates 2018-11-19 10:45:50 +01:00
976777a039 Updated submodules 2018-11-12 19:41:23 +01:00
dd7b0f380a Cleanup 2018-11-12 19:38:16 +01:00
d160a34c5d Refactored arch_if to save unneeded constructor calls 2018-11-12 19:36:45 +01:00
8092326437 Changed name to get consistent 2018-11-12 19:36:44 +01:00
20b3665003 Back-ported DVCon turorial changes 2018-11-12 19:36:44 +01:00
124a308ffa Fixed a type which rendered a link useless 2018-07-28 08:10:26 +00:00
62c4311c31 Updated repository references 2018-07-28 10:07:00 +02:00
0bf4933372 Added link to original repo 2018-07-28 10:02:28 +02:00
38099e3fc6 Added ADC, H-Bridge and motor models, refactored project structure 2018-07-28 09:45:49 +02:00
100822810f Added entire system incl. terminal and MCP3008 ADC connected via SPI 2018-07-23 22:46:30 +02:00
a899d30556 Implemented basic HiFive1-like platform with PLL,tracing etc. 2018-07-13 20:04:07 +02:00
b28595445c Extended README and clenaed up lauch configurations 2018-07-12 17:44:06 +02:00
fede5b2af1 Changed SystemC model to model a platform in a system. Added dedicated
UART Terminal connected via tlm_signals
2018-07-12 15:27:36 +02:00
a3baa45b00 Updated SystemC CCI to 1.0 2018-07-11 19:19:41 +02:00
22426ad2ff Removed poco package as it is not used 2018-07-11 19:12:24 +02:00
e2cb2aff20 Updated DBT-RISE library 2018-07-11 17:44:42 +02:00
51bfb02c33 Changed Seasocks lib setting 2018-07-10 19:01:31 +02:00
bd60e4dbe1 Fixed missing check for unset CMAKE_BUILD_TYPE 2018-07-10 18:25:14 +02:00
282ff6964b Fixed typo in CMakeList.txt 2018-05-15 20:10:13 +02:00