„src/main.cpp“ ändern

debugger memory accesses should never lead to traps
streamlines backends and reporting
2023-10-15 09:03:31 +02:00 · 2023-10-06 21:39:48 +02:00 · 2023-10-01 18:33:14 +02:00 · 2023-09-30 22:17:18 +02:00 · 2023-09-30 22:10:24 +02:00 · 2023-09-27 07:51:49 +02:00
34 changed files with 8801 additions and 8574 deletions
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@ -15,19 +15,19 @@ find_package(Boost COMPONENTS coroutine REQUIRED)
 add_subdirectory(softfloat)

 set(LIB_SOURCES 
-	src/iss/arch/tgc_c.cpp
-	src/vm/tcc/vm_tgc_c.cpp
-	src/vm/interp/vm_tgc_c.cpp
+    src/iss/plugin/instruction_count.cpp
+	src/iss/arch/tgc5c.cpp
+	src/vm/interp/vm_tgc5c.cpp
 	src/vm/fp_functions.cpp
 )
 if(WITH_TCC)
 	list(APPEND LIB_SOURCES
-		src/vm/tcc/vm_tgc_c.cpp
+	   src/vm/tcc/vm_tgc5c.cpp
    )
 endif()
 if(WITH_LLVM)
 	list(APPEND LIB_SOURCES
-		src/vm/llvm/vm_tgc_c.cpp
+		src/vm/llvm/vm_tgc5c.cpp
 		src/vm/llvm/fp_impl.cpp
 	)
 endif()
@ -53,14 +53,9 @@ if(WITH_TCC)
 	list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
 endif()

-if(TARGET RapidJSON)
+if(TARGET yaml-cpp::yaml-cpp)
    list(APPEND LIB_SOURCES 
    	src/iss/plugin/cycle_estimate.cpp
-    	src/iss/plugin/pctrace.cpp
-    )
-endif()
-if(TARGET jsoncpp::jsoncpp)
-    list(APPEND LIB_SOURCES 
 	    src/iss/plugin/instruction_count.cpp
    )
 endif()
@ -80,18 +75,23 @@ target_force_link_libraries(${PROJECT_NAME} PRIVATE dbt-rise-core)
 get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES)
 target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL})
 get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS)
-target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
+if(NOT (DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND))
+	target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
+endif()

 target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine)
-if(TARGET jsoncpp::jsoncpp)
-	target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp::jsoncpp)
+if(TARGET yaml-cpp::yaml-cpp)
+	target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS)
+	target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp)
 endif()
-if(TARGET lz4::lz4)
-    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_LZ4)
-    target_link_libraries(${PROJECT_NAME} PUBLIC lz4::lz4)
-endif()
-if(TARGET RapidJSON)
-    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON)
+
+if(WITH_LLVM)
+    find_package(LLVM)
+	target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
+	target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
+	if(BUILD_SHARED_LIBS)
+		target_link_libraries( ${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
+	endif()
 endif()

 set_target_properties(${PROJECT_NAME} PROPERTIES
--- a/TGC5C_instr.yaml
+++ b/TGC5C_instr.yaml
@ -1,307 +1,297 @@

 RV32I: 
-  - LUI:
+  LUI:
    encoding: 0b00000000000000000000000000110111
    mask: 0b00000000000000000000000001111111
    size:   32
    branch:   false
    delay:   1
-  - AUIPC:
+  AUIPC:
    encoding: 0b00000000000000000000000000010111
    mask: 0b00000000000000000000000001111111
    size:   32
    branch:   false
    delay:   1
-  - JAL:
+  JAL:
    encoding: 0b00000000000000000000000001101111
    mask: 0b00000000000000000000000001111111
-    attributes: [[name:no_cont]]
    size:   32
    branch:   true
    delay:   1
-  - JALR:
+  JALR:
    encoding: 0b00000000000000000000000001100111
    mask: 0b00000000000000000111000001111111
-    attributes: [[name:no_cont]]
    size:   32
    branch:   true
-    delay:   1
-  - BEQ:
+    delay:   [1,1]
+  BEQ:
    encoding: 0b00000000000000000000000001100011
    mask: 0b00000000000000000111000001111111
-    attributes: [[name:no_cont], [name:cond]]
    size:   32
    branch:   true
    delay:   [1,1]
-  - BNE:
+  BNE:
    encoding: 0b00000000000000000001000001100011
    mask: 0b00000000000000000111000001111111
-    attributes: [[name:no_cont], [name:cond]]
    size:   32
    branch:   true
    delay:   [1,1]
-  - BLT:
+  BLT:
    encoding: 0b00000000000000000100000001100011
    mask: 0b00000000000000000111000001111111
-    attributes: [[name:no_cont], [name:cond]]
    size:   32
    branch:   true
    delay:   [1,1]
-  - BGE:
+  BGE:
    encoding: 0b00000000000000000101000001100011
    mask: 0b00000000000000000111000001111111
-    attributes: [[name:no_cont], [name:cond]]
    size:   32
    branch:   true
    delay:   [1,1]
-  - BLTU:
+  BLTU:
    encoding: 0b00000000000000000110000001100011
    mask: 0b00000000000000000111000001111111
-    attributes: [[name:no_cont], [name:cond]]
    size:   32
    branch:   true
    delay:   [1,1]
-  - BGEU:
+  BGEU:
    encoding: 0b00000000000000000111000001100011
    mask: 0b00000000000000000111000001111111
-    attributes: [[name:no_cont], [name:cond]]
    size:   32
    branch:   true
    delay:   [1,1]
-  - LB:
+  LB:
    encoding: 0b00000000000000000000000000000011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - LH:
+  LH:
    encoding: 0b00000000000000000001000000000011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - LW:
+  LW:
    encoding: 0b00000000000000000010000000000011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - LBU:
+  LBU:
    encoding: 0b00000000000000000100000000000011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - LHU:
+  LHU:
    encoding: 0b00000000000000000101000000000011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SB:
+  SB:
    encoding: 0b00000000000000000000000000100011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SH:
+  SH:
    encoding: 0b00000000000000000001000000100011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SW:
+  SW:
    encoding: 0b00000000000000000010000000100011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - ADDI:
+  ADDI:
    encoding: 0b00000000000000000000000000010011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SLTI:
+  SLTI:
    encoding: 0b00000000000000000010000000010011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SLTIU:
+  SLTIU:
    encoding: 0b00000000000000000011000000010011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - XORI:
+  XORI:
    encoding: 0b00000000000000000100000000010011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - ORI:
+  ORI:
    encoding: 0b00000000000000000110000000010011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - ANDI:
+  ANDI:
    encoding: 0b00000000000000000111000000010011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SLLI:
+  SLLI:
    encoding: 0b00000000000000000001000000010011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SRLI:
+  SRLI:
    encoding: 0b00000000000000000101000000010011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SRAI:
+  SRAI:
    encoding: 0b01000000000000000101000000010011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - ADD:
+  ADD:
    encoding: 0b00000000000000000000000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SUB:
+  SUB:
    encoding: 0b01000000000000000000000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SLL:
+  SLL:
    encoding: 0b00000000000000000001000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SLT:
+  SLT:
    encoding: 0b00000000000000000010000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SLTU:
+  SLTU:
    encoding: 0b00000000000000000011000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - XOR:
+  XOR:
    encoding: 0b00000000000000000100000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SRL:
+  SRL:
    encoding: 0b00000000000000000101000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - SRA:
+  SRA:
    encoding: 0b01000000000000000101000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - OR:
+  OR:
    encoding: 0b00000000000000000110000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - AND:
+  AND:
    encoding: 0b00000000000000000111000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - FENCE:
+  FENCE:
    encoding: 0b00000000000000000000000000001111
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - ECALL:
+  ECALL:
    encoding: 0b00000000000000000000000001110011
    mask: 0b11111111111111111111111111111111
-    attributes: [[name:no_cont]]
    size:   32
    branch:   false
    delay:   1
-  - EBREAK:
+  EBREAK:
    encoding: 0b00000000000100000000000001110011
    mask: 0b11111111111111111111111111111111
-    attributes: [[name:no_cont]]
    size:   32
    branch:   false
    delay:   1
-  - MRET:
+  MRET:
    encoding: 0b00110000001000000000000001110011
    mask: 0b11111111111111111111111111111111
    attributes: [[name:no_cont]]
    size:   32
    branch:   false
    delay:   1
-  - WFI:
+  WFI:
    encoding: 0b00010000010100000000000001110011
    mask: 0b11111111111111111111111111111111
    size:   32
    branch:   false
    delay:   1
 Zicsr: 
-  - CSRRW:
+  CSRRW:
    encoding: 0b00000000000000000001000001110011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - CSRRS:
+  CSRRS:
    encoding: 0b00000000000000000010000001110011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - CSRRC:
+  CSRRC:
    encoding: 0b00000000000000000011000001110011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - CSRRWI:
+  CSRRWI:
    encoding: 0b00000000000000000101000001110011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - CSRRSI:
+  CSRRSI:
    encoding: 0b00000000000000000110000001110011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - CSRRCI:
+  CSRRCI:
    encoding: 0b00000000000000000111000001110011
    mask: 0b00000000000000000111000001111111
    size:   32
    branch:   false
    delay:   1
 Zifencei: 
-  - FENCE_I:
+  FENCE_I:
    encoding: 0b00000000000000000001000000001111
    mask: 0b00000000000000000111000001111111
    attributes: [[name:flush]]
@ -309,228 +299,233 @@ Zifencei:
    branch:   false
    delay:   1
 RV32M: 
-  - MUL:
+  MUL:
    encoding: 0b00000010000000000000000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - MULH:
+  MULH:
    encoding: 0b00000010000000000001000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - MULHSU:
+  MULHSU:
    encoding: 0b00000010000000000010000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - MULHU:
+  MULHU:
    encoding: 0b00000010000000000011000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - DIV:
+  DIV:
    encoding: 0b00000010000000000100000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - DIVU:
+  DIVU:
    encoding: 0b00000010000000000101000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - REM:
+  REM:
    encoding: 0b00000010000000000110000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
-  - REMU:
+  REMU:
    encoding: 0b00000010000000000111000000110011
    mask: 0b11111110000000000111000001111111
    size:   32
    branch:   false
    delay:   1
 RV32IC: 
-  - CADDI4SPN:
+  C__ADDI4SPN:
    encoding: 0b0000000000000000
    mask: 0b1110000000000011
    size:   16
    branch:   false
    delay:   1
-  - CLW:
+  C__LW:
    encoding: 0b0100000000000000
    mask: 0b1110000000000011
    size:   16
    branch:   false
    delay:   1
-  - CSW:
+  C__SW:
    encoding: 0b1100000000000000
    mask: 0b1110000000000011
    size:   16
    branch:   false
    delay:   1
-  - CADDI:
+  C__ADDI:
    encoding: 0b0000000000000001
    mask: 0b1110000000000011
    size:   16
    branch:   false
    delay:   1
-  - CNOP:
+  C__NOP:
    encoding: 0b0000000000000001
    mask: 0b1110111110000011
    size:   16
    branch:   false
    delay:   1
-  - CJAL:
+  C__JAL:
    encoding: 0b0010000000000001
    mask: 0b1110000000000011
-    attributes: [[name:no_cont]]
    size:   16
    branch:   true
    delay:   1
-  - CLI:
+  C__LI:
    encoding: 0b0100000000000001
    mask: 0b1110000000000011
    size:   16
    branch:   false
    delay:   1
-  - CLUI:
+  C__LUI:
    encoding: 0b0110000000000001
    mask: 0b1110000000000011
    size:   16
    branch:   false
    delay:   1
-  - CADDI16SP:
+  C__ADDI16SP:
    encoding: 0b0110000100000001
    mask: 0b1110111110000011
    size:   16
    branch:   false
    delay:   1
-  - CSRLI:
+  __reserved_clui:
+    encoding: 0b0110000000000001
+    mask: 0b1111000001111111
+    size:   16
+    branch:   false
+    delay:   1
+  C__SRLI:
    encoding: 0b1000000000000001
    mask: 0b1111110000000011
    size:   16
    branch:   false
    delay:   1
-  - CSRAI:
+  C__SRAI:
    encoding: 0b1000010000000001
    mask: 0b1111110000000011
    size:   16
    branch:   false
    delay:   1
-  - CANDI:
+  C__ANDI:
    encoding: 0b1000100000000001
    mask: 0b1110110000000011
    size:   16
    branch:   false
    delay:   1
-  - CSUB:
+  C__SUB:
    encoding: 0b1000110000000001
    mask: 0b1111110001100011
    size:   16
    branch:   false
    delay:   1
-  - CXOR:
+  C__XOR:
    encoding: 0b1000110000100001
    mask: 0b1111110001100011
    size:   16
    branch:   false
    delay:   1
-  - COR:
+  C__OR:
    encoding: 0b1000110001000001
    mask: 0b1111110001100011
    size:   16
    branch:   false
    delay:   1
-  - CAND:
+  C__AND:
    encoding: 0b1000110001100001
    mask: 0b1111110001100011
    size:   16
    branch:   false
    delay:   1
-  - CJ:
+  C__J:
    encoding: 0b1010000000000001
    mask: 0b1110000000000011
-    attributes: [[name:no_cont]]
    size:   16
    branch:   true
    delay:   1
-  - CBEQZ:
+  C__BEQZ:
    encoding: 0b1100000000000001
    mask: 0b1110000000000011
-    attributes: [[name:no_cont], [name:cond]]
    size:   16
    branch:   true
    delay:   [1,1]
-  - CBNEZ:
+  C__BNEZ:
    encoding: 0b1110000000000001
    mask: 0b1110000000000011
-    attributes: [[name:no_cont], [name:cond]]
    size:   16
    branch:   true
    delay:   [1,1]
-  - CSLLI:
+  C__SLLI:
    encoding: 0b0000000000000010
    mask: 0b1111000000000011
+    attributes: [[name:enable, value:1]]
    size:   16
    branch:   false
    delay:   1
-  - CLWSP:
+  C__LWSP:
    encoding: 0b0100000000000010
    mask: 0b1110000000000011
    size:   16
    branch:   false
    delay:   1
-  - CMV:
+  C__MV:
    encoding: 0b1000000000000010
    mask: 0b1111000000000011
    size:   16
    branch:   false
    delay:   1
-  - CJR:
+  C__JR:
    encoding: 0b1000000000000010
    mask: 0b1111000001111111
-    attributes: [[name:no_cont]]
    size:   16
    branch:   true
    delay:   1
-  - CADD:
+  __reserved_cmv:
+    encoding: 0b1000000000000010
+    mask: 0b1111111111111111
+    size:   16
+    branch:   false
+    delay:   1
+  C__ADD:
    encoding: 0b1001000000000010
    mask: 0b1111000000000011
    size:   16
    branch:   false
    delay:   1
-  - CJALR:
+  C__JALR:
    encoding: 0b1001000000000010
    mask: 0b1111000001111111
-    attributes: [[name:no_cont]]
    size:   16
    branch:   true
    delay:   1
-  - CEBREAK:
+  C__EBREAK:
    encoding: 0b1001000000000010
    mask: 0b1111111111111111
-    attributes: [[name:no_cont]]
    size:   16
    branch:   false
    delay:   1
-  - CSWSP:
+  C__SWSP:
    encoding: 0b1100000000000010
    mask: 0b1110000000000011
    size:   16
    branch:   false
    delay:   1
-  - DII:
+  DII:
    encoding: 0b0000000000000000
    mask: 0b1111111111111111
-    attributes: [[name:no_cont]]
    size:   16
    branch:   false
    delay:   1
--- a/gen_input/TGC5C.core_desc
+++ b/gen_input/TGC5C.core_desc
@ -1,8 +1,8 @@
-import "ISA/RV32I.core_desc"
+import "ISA/RVI.core_desc"
 import "ISA/RVM.core_desc"
 import "ISA/RVC.core_desc"

-Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
+Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
    architectural_state {
        XLEN=32;
        // definitions for the architecture wrapper
--- a/gen_input/templates/CORENAME.h.gtl
+++ b/gen_input/templates/CORENAME.h.gtl
@ -76,10 +76,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
    constexpr static char const* const core_type = "${coreDef.name}";
    
    static constexpr std::array<const char*, ${registers.size}> reg_names{
-        {"${registers.collect{it.name}.join('", "')}"}};
+        {"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
 
    static constexpr std::array<const char*, ${registers.size}> reg_aliases{
-        {"${registers.collect{it.alias}.join('", "')}"}};
+        {"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};

    enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};

--- a/gen_input/templates/CORENAME_decoder.cpp.gtl
+++ b/gen_input/templates/CORENAME_decoder.cpp.gtl
@ -1,86 +0,0 @@
-#include "${coreDef.name.toLowerCase()}.h"
-#include <vector>
-#include <array>
-#include <cstdlib>
-#include <algorithm>
-
-namespace iss {
-namespace arch {
-namespace {
-// according to
-// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
-#ifdef __GCC__
-constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
-#elif __cplusplus < 201402L
-constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
-constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
-#else
-constexpr size_t bit_count(uint32_t u) {
-    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
-    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
-}
-#endif
-
-using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
-
-/****************************************************************************
- * start opcode definitions
- ****************************************************************************/
-struct instruction_desriptor {
-    size_t length;
-    uint32_t value;
-    uint32_t mask;
-    opcode_e op;
-};
-
-const std::array<instruction_desriptor, ${instructions.size}> instr_descr = {{
-     /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-    {${instr.length}, ${instr.encoding}, ${instr.mask}, opcode_e::${instr.instruction.name}},<%}%>
-}};
-
-}
-
-template<>
-struct instruction_decoder<${coreDef.name.toLowerCase()}> {
-    using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
-    using code_word_t=traits<${coreDef.name.toLowerCase()}>::code_word_t;
-
-    struct instruction_pattern {
-        uint32_t value;
-        uint32_t mask;
-        opcode_e id;
-    };
-
-    std::array<std::vector<instruction_pattern>, 4> qlut;
-
-    template<typename T>
-    unsigned decode_instruction(T);
-
-    instruction_decoder() {
-        for (auto instr : instr_descr) {
-            auto quadrant = instr.value & 0x3;
-            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
-        }
-        for(auto& lut: qlut){
-            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
-                return bit_count(a.mask) < bit_count(b.mask);
-            });
-        }
-    }
-};
-
-template<>
-unsigned instruction_decoder<${coreDef.name.toLowerCase()}>::decode_instruction<traits<${coreDef.name.toLowerCase()}>::code_word_t>(traits<${coreDef.name.toLowerCase()}>::code_word_t instr){
-    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
-        return !((instr&e.mask) ^ e.value );
-    });
-    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
-}
-
-
-std::unique_ptr<instruction_decoder<${coreDef.name.toLowerCase()}>> traits<${coreDef.name.toLowerCase()}>::get_decoder(){
-    return std::make_unique<instruction_decoder<${coreDef.name.toLowerCase()}>>();
-}
-
-}
-}
--- a/gen_input/templates/CORENAME_instr.yaml.gtl
+++ b/gen_input/templates/CORENAME_instr.yaml.gtl
@ -9,8 +9,8 @@
    }
    instrGroups
 }%><%getInstructionGroups().each{name, instrList -> %>
-${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %>
-  - ${it.instruction.name}:
+${name}: <% instrList.each { %>
+  ${it.instruction.name}:
    encoding: ${it.encoding}
    mask: ${it.mask}<%if(it.attributes.size) {%>
    attributes: ${it.attributes}<%}%>
--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@ -40,9 +40,11 @@ def nativeTypeSize(int size){
 #include <iss/iss.h>
 #include <iss/interp/vm_base.h>
 #include <util/logging.h>
-#include <sstream>
 #include <boost/coroutine2/all.hpp>
 #include <functional>
+#include <exception>
+#include <vector>
+#include <sstream>

 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@ -59,6 +61,10 @@ using namespace iss::arch;
 using namespace iss::debugger;
 using namespace std::placeholders;

+struct memory_access_exception : public std::exception{
+    memory_access_exception(){}
+};
+
 template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
 public:
    using traits = arch::traits<ARCH>;
@ -91,30 +97,9 @@ protected:

    inline const char *name(size_t index){return index<traits::reg_aliases.size()?traits::reg_aliases[index]:"illegal";}

-    typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
    virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;

    // some compile time constants
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum {
-        LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)),
-        LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16))
-    };
-
-    std::array<compile_func, LUT_SIZE> lut;
-
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
-    std::array<compile_func, LUT_SIZE> lut_11;
-
-    struct instruction_pattern {
-        uint32_t value;
-        uint32_t mask;
-        typename arch::traits<ARCH>::opcode_e id;
-    };
-
-    std::array<std::vector<instruction_pattern>, 4> qlut;

    inline void raise(uint16_t trap_id, uint16_t cause){
        auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
@ -314,6 +299,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
            // pre execution stuff
             this->core.reg.last_branch = 0;
            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
+            try{
                switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
                case arch::traits<ARCH>::opcode_e::${instr.name}: {
                    <%instr.fields.eachLine{%>${it}
@ -329,13 +315,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                    *NEXT_PC = *PC + ${instr.length/8};
                    // execute instruction<%instr.behavior.eachLine{%>
                    ${it}<%}%>
-                TRAP_${instr.name}:break;
+                    break;
                }// @suppress("No break at end of case")<%}%>
                default: {
                    *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
                    raise(0,  2);
                }
                }
+            }catch(memory_access_exception& e){}
            // post execution stuff
            process_spawn_blocks();
            if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
--- a/gen_input/templates/llvm/CORENAME.cpp.gtl
+++ b/gen_input/templates/llvm/CORENAME.cpp.gtl
@ -58,6 +58,7 @@ using namespace iss::debugger;

 template <typename ARCH> class vm_impl : public iss::llvm::vm_base<ARCH> {
 public:
+    using traits = arch::traits<ARCH>;
    using super = typename iss::llvm::vm_base<ARCH>;
    using virt_addr_t = typename super::virt_addr_t;
    using phys_addr_t = typename super::phys_addr_t;
@ -80,7 +81,7 @@ public:
 protected:
    using vm_base<ARCH>::get_reg_ptr;

-    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}

    template <typename T> inline ConstantInt *size(T type) {
        return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
@ -88,7 +89,7 @@ protected:

    void setup_module(Module* m) override {
        super::setup_module(m);
-        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
+        iss::llvm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE, traits::XLEN);
    }

    inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
@ -114,112 +115,146 @@ protected:
    }

    inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
-        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
-                                                           this->get_type(traits<ARCH>::XLEN));
+        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val),
+                                                           this->get_type(traits::XLEN));
        this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
    }

    // some compile time constants
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(static_cast<uint64_t>(EXTR_MASK32)), LUT_SIZE_C = 1 << util::bit_count(static_cast<uint64_t>(EXTR_MASK16)) };

    using this_class = vm_impl<ARCH>;
    using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
                                                                                  code_word_t instr,
                                                                                  BasicBlock *bb);
-    std::array<compile_func, LUT_SIZE> lut;
-
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
-    std::array<compile_func, LUT_SIZE> lut_11;
-
-	std::array<compile_func *, 4> qlut;
-
-	std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
-
-    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
-                         compile_func f) {
-        if (pos < 0) {
-            lut[idx] = f;
-        } else {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
-            } else {
-                if ((valid & bitmask) == 0) {
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
-                } else {
-                    auto new_val = idx << 1;
-                    if ((value & bitmask) != 0) new_val++;
-                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
-                }
-            }
-        }
-    }
-
-    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
-
-    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
-        if (pos >= 0) {
-            auto bitmask = 1UL << pos;
-            if ((mask & bitmask) == 0) {
-                lut_val = extract_fields(pos - 1, val, mask, lut_val);
-            } else {
-                auto new_val = lut_val << 1;
-                if ((val & bitmask) != 0) new_val++;
-                lut_val = extract_fields(pos - 1, val, mask, new_val);
-            }
-        }
-        return lut_val;
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
+        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
    }   

 private:
    /****************************************************************************
     * start opcode definitions
     ****************************************************************************/
-    struct InstructionDesriptor {
+    struct instruction_descriptor {
        size_t length;
        uint32_t value;
        uint32_t mask;
        compile_func op;
    };
+    struct decoding_tree_node{
+        std::vector<instruction_descriptor> instrs;
+        std::vector<decoding_tree_node*> children;
+        uint32_t submask = std::numeric_limits<uint32_t>::max();
+        uint32_t value;
+        decoding_tree_node(uint32_t value) : value(value){}
+    };

-    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
+    decoding_tree_node* root {nullptr};
+
+    const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name} */
-        {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
    }};
 
    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
    /* instruction ${idx}: ${instr.name} */
-    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){<%instr.code.eachLine{%>
+    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        bb->setName(fmt::format("${instr.name}_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,${idx});
+        uint64_t PC = pc.val;
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate console output when executing the command */<%instr.disass.eachLine{%>
            ${it}<%}%>
        }
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ ${instr.length/8};
+        this->gen_set_pc(pc, traits::NEXT_PC);
+        <%instr.behavior.eachLine{%>${it}
+        <%}%>
+        this->gen_trap_check(bb);
+    	this->gen_sync(POST_SYNC, ${idx});
+        this->builder.CreateBr(bb);
+    	return returnValue;        
+    }
    <%}%>
    /****************************************************************************
     * end opcode definitions
     ****************************************************************************/
    std::tuple<continuation_e, BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
 		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
-        this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits<ARCH>::NEXT_PC), get_reg_ptr(traits<ARCH>::NEXT_PC), true),
-                                   get_reg_ptr(traits<ARCH>::PC), true);
+        this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
+                                   get_reg_ptr(traits::PC), true);
        this->builder.CreateStore(
-            this->builder.CreateAdd(this->builder.CreateLoad(this->get_typeptr(traits<ARCH>::ICOUNT), get_reg_ptr(traits<ARCH>::ICOUNT), true),
+            this->builder.CreateAdd(this->builder.CreateLoad(this->get_typeptr(traits::ICOUNT), get_reg_ptr(traits::ICOUNT), true),
                                     this->gen_const(64U, 1)),
-            get_reg_ptr(traits<ARCH>::ICOUNT), true);
+            get_reg_ptr(traits::ICOUNT), true);
        pc = pc + ((instr & 3) == 3 ? 4 : 2);
        this->gen_raise_trap(0, 2);     // illegal instruction trap
 		this->gen_sync(iss::POST_SYNC, instr_descr.size());
        this->gen_trap_check(this->leave_blk);
        return std::make_tuple(BRANCH, nullptr);
    }    
+    //decoding functionality
+
+    void populate_decoding_tree(decoding_tree_node* root){
+        //create submask
+        for(auto instr: root->instrs){
+            root->submask &= instr.mask;
+        }
+        //put each instr according to submask&encoding into children
+        for(auto instr: root->instrs){
+            bool foundMatch = false;
+            for(auto child: root->children){
+                //use value as identifying trait
+                if(child->value == (instr.value&root->submask)){
+                    child->instrs.push_back(instr);
+                    foundMatch = true;
+                }
+            }
+            if(!foundMatch){
+                decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask);
+                child->instrs.push_back(instr);
+                root->children.push_back(child);
+            }
+        }
+        root->instrs.clear();
+        //call populate_decoding_tree for all children
+        if(root->children.size() >1)
+            for(auto child: root->children){
+                populate_decoding_tree(child);      
+            }
+        else{
+            //sort instrs by value of the mask, this works bc we want to have the least restrictive one last
+            std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) {
+            return instr1.mask > instr2.mask;
+            }); 
+        }
+    }
+    compile_func decode_instr(decoding_tree_node* node, code_word_t word){
+        if(!node->children.size()){
+            if(node->instrs.size() == 1) return node->instrs[0].op;
+            for(auto instr : node->instrs){
+                if((instr.mask&word) == instr.value) return instr.op;
+            }
+        }
+        else{
+            for(auto child : node->children){
+                if (child->value == (node->submask&word)){
+                    return decode_instr(child, word);
+                }  
+            }  
+        }
+        return nullptr;
+    }
 };

-template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
-    volatile CODE_WORD x = insn;
-    insn = 2 * x;
+template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
+    volatile CODE_WORD x = instr;
+    instr = 2 * x;
 }

 template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
@ -227,14 +262,11 @@ template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
-    qlut[0] = lut_00.data();
-    qlut[1] = lut_01.data();
-    qlut[2] = lut_10.data();
-    qlut[3] = lut_11.data();
-    for (auto instr : instr_descr) {
-        auto quantrant = instr.value & 0x3;
-        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
+    root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
+    for(auto instr:instr_descr){
+        root->instrs.push_back(instr);
    }
+    populate_decoding_tree(root);
 }

 template <typename ARCH>
@ -242,50 +274,50 @@ std::tuple<continuation_e, BasicBlock *>
 vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
    // we fetch at max 4 byte, alignment is 2
    enum {TRAP_ID=1<<16};
-    code_word_t insn = 0;
-    // const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    code_word_t instr = 0;
+    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
    phys_addr_t paddr(pc);
-    auto *const data = (uint8_t *)&insn;
-    paddr = this->core.v2p(pc);
+    auto *const data = (uint8_t *)&instr;
+    if(this->core.has_mmu())
+        paddr = this->core.virt2phys(pc);
    //TODO: re-add page handling
 //    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
 //        auto res = this->core.read(paddr, 2, data);
 //        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-//        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
+//        if ((instr & 0x3) == 0x3) { // this is a 32bit instruction
 //            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
 //        }
 //    } else {
        auto res = this->core.read(paddr, 4, data);
        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
 //    }
-    if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
    // curr pc on stack
    ++inst_cnt;
-    auto lut_val = extract_fields(insn);
-    auto f = qlut[insn & 0x3][lut_val];
+    auto f = decode_instr(root, instr);
    if (f == nullptr) {
        f = &this_class::illegal_intruction;
    }
-    return (this->*f)(pc, insn, this_block);
+    return (this->*f)(pc, instr, this_block);
 }

 template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
    this->builder.SetInsertPoint(leave_blk);
-    this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::NEXT_PC), get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
+    this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false));
 }

 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
    auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
-    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
+    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits::LAST_BRANCH), false);
 }

 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
    this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
-    auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
-    this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
+    auto *PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8);
+    this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false);
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits::LAST_BRANCH), false);
 }

 template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
@ -295,22 +327,25 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {

 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
    this->builder.SetInsertPoint(trap_blk);
-    auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::TRAP_STATE), get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
+    this->gen_sync(POST_SYNC, -1); //TODO get right InstrId
+    auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
-                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
+                              get_reg_ptr(traits::LAST_BRANCH), false);
    std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
-                              this->adj_to64(this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::PC), get_reg_ptr(traits<ARCH>::PC), false))};
+                              this->adj_to64(this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), false))};
    this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
-    auto *trap_addr_val = this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::NEXT_PC), get_reg_ptr(traits<ARCH>::NEXT_PC), false);
+    auto *trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false);
    this->builder.CreateRet(trap_addr_val);
 }

 template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
-    auto *v = this->builder.CreateLoad(this->get_typeptr(arch::traits<ARCH>::TRAP_STATE), get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
+    auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb);
+    auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
    this->gen_cond_branch(this->builder.CreateICmp(
                              ICmpInst::ICMP_EQ, v,
                              ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
-                          bb, this->trap_blk, 1);
+                          target_bb, this->trap_blk, 1);
+    this->builder.SetInsertPoint(target_bb);
 }

 } // namespace ${coreDef.name.toLowerCase()}
--- a/gen_input/templates/tcc/CORENAME.cpp.gtl
+++ b/gen_input/templates/tcc/CORENAME.cpp.gtl
@ -159,6 +159,7 @@ private:
    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
        tu("${instr.name}_{:#010x}:", pc.val);
        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
+        uint64_t PC = pc.val;
        <%instr.fields.eachLine{%>${it}
        <%}%>if(this->disass_enabled){
            /* generate console output when executing the command */<%instr.disass.eachLine{%>
@ -167,11 +168,12 @@ private:
        auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
        pc=pc+ ${instr.length/8};
        gen_set_pc(tu, pc, traits::NEXT_PC);
-        tu.open_scope();<%instr.behavior.eachLine{%>
-        ${it}<%}%>
+        tu.open_scope();
+        <%instr.behavior.eachLine{%>${it}
+        <%}%>
        tu.close_scope();
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
        return returnValue;
    }
    <%}%>
@ -304,6 +306,7 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t

 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
    tu("trap_entry:");
+    this->gen_sync(tu, POST_SYNC, -1);    
    tu("enter_trap(core_ptr, *trap_state, *pc, 0);");
    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(),32));
    tu("return *next_pc;");
--- a/src/iss/arch/hwl.h
+++ b/src/iss/arch/hwl.h
@ -46,7 +46,7 @@ public:
    using this_class = hwl<BASE>;
    using reg_t = typename BASE::reg_t;

-    hwl();
+    hwl(feature_config cfg = feature_config{});
    virtual ~hwl() = default;

 protected:
@ -56,7 +56,7 @@ protected:


 template<typename BASE>
-inline hwl<BASE>::hwl() {
+inline hwl<BASE>::hwl(feature_config cfg): BASE(cfg) {
    for (unsigned addr = 0x800; addr < 0x803; ++addr){
        this->register_custom_csr_rd(addr);
        this->register_custom_csr_wr(addr);
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@ -226,6 +226,8 @@ struct feature_config {
    unsigned clic_num_trigger{0};
    uint64_t tcm_base{0x10000000};
    uint64_t tcm_size{0x8000};
+    uint64_t io_address{0xf0000000};
+    uint64_t io_addr_mask{0xf0000000};
 };

 class trap_load_access_fault : public trap_access {
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@ -304,9 +304,9 @@ protected:
         */
        const std::string core_type_name() const override { return traits<BASE>::core_type; }

-        uint64_t get_pc() override { return arch.reg.PC; };
+        uint64_t get_pc() override { return arch.reg.PC; }

-        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }

        uint64_t get_instr_word() override { return arch.reg.instruction; }

@ -316,9 +316,11 @@ protected:

        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }

-        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }

-        bool is_branch_taken() override { return arch.reg.last_branch; };
+        bool is_branch_taken() override { return arch.reg.last_branch; }
+
+        unsigned get_reg_num() override {return traits<BASE>::NUM_REGS;}

        riscv_hart_m_p<BASE, FEAT> &arch;
    };
@ -680,7 +682,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
                } else {
                    res = hart_mem_rd_delegate( phys_addr, length, data);
                }
-                if (unlikely(res != iss::Ok)){
+                if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)){
                    this->reg.trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                    fault_data=addr;
                }
@ -773,7 +775,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                } else {
                    res = write_mem( phys_addr, length, data);
                }
-                if (unlikely(res != iss::Ok)) {
+                if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                    this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
                    fault_data=addr;
                }
@ -1113,8 +1115,10 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
                        }
                        this->reg.trap_state=std::numeric_limits<uint32_t>::max();
                        this->interrupt_sim=hostvar;
+#ifndef WITH_TCC
+                        throw(iss::simulation_stopped(hostvar));
+#endif
                        break;
-                        //throw(iss::simulation_stopped(hostvar));
                    case 0x0101: {
                        char c = static_cast<char>(hostvar & 0xff);
                        if (c == '\n' || c == 0) {
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@ -286,7 +286,7 @@ public:
        return m[mode];
    }

-    riscv_hart_msu_vp();
+    riscv_hart_msu_vp(feature_config cfg = feature_config{});
    virtual ~riscv_hart_msu_vp() = default;

    void reset(uint64_t address) override;
@ -331,9 +331,9 @@ protected:
         */
        const std::string core_type_name() const override { return traits<BASE>::core_type; }

-        uint64_t get_pc() override { return arch.reg.PC; };
+        uint64_t get_pc() override { return arch.reg.PC; }

-        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }

        uint64_t get_instr_word() override { return arch.reg.instruction; }

@ -343,9 +343,11 @@ protected:

        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }

-        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }

-        bool is_branch_taken() override { return arch.reg.last_branch; };
+        bool is_branch_taken() override { return arch.reg.last_branch; }
+
+        unsigned get_reg_num() override {return traits<BASE>::NUM_REGS; }

        riscv_hart_msu_vp<BASE> &arch;
    };
@ -634,7 +636,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
                    }
                }
                auto res = read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                if (unlikely(res != iss::Ok)){
+                if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)){
                	this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
                    fault_data=addr;
                }
@ -732,7 +734,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                    }
                }
                auto res = write_mem(paddr, length, data);
-                if (unlikely(res != iss::Ok)) {
+                if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                    this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
                    fault_data=addr;
                }
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@ -329,9 +329,9 @@ protected:
         */
        const std::string core_type_name() const override { return traits<BASE>::core_type; }

-        uint64_t get_pc() override { return arch.reg.PC; };
+        uint64_t get_pc() override { return arch.reg.PC; }

-        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }

        uint64_t get_instr_word() override { return arch.reg.instruction; }

@ -341,9 +341,11 @@ protected:

        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }

-        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
+        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }

-        bool is_branch_taken() override { return arch.reg.last_branch; };
+        bool is_branch_taken() override { return arch.reg.last_branch; }
+
+        unsigned get_reg_num() override {return traits<BASE>::NUM_REGS; }

        riscv_hart_mu_p<BASE, FEAT> &arch;
    };
@ -848,7 +850,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                } else {
                    res = hart_mem_rd_delegate( phys_addr, length, data);
                }
-                if (unlikely(res != iss::Ok)){
+                if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)){
                    this->reg.trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                    fault_data=addr;
                }
@ -949,7 +951,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                } else {
                    res = hart_mem_wr_delegate( phys_addr, length, data);
                }
-                if (unlikely(res != iss::Ok)) {
+                if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                    this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
                    fault_data=addr;
                }
--- a/src/iss/arch/tgc5c.cpp
+++ b/src/iss/arch/tgc5c.cpp
@ -30,7 +30,7 @@
 *
 *******************************************************************************/

-#include "tgc_c.h"
+#include "tgc5c.h"
 #include "util/ities.h"
 #include <util/logging.h>
 #include <cstdio>
@ -39,18 +39,18 @@

 using namespace iss::arch;

-constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
-constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
-constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_names;
+constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc5c>::reg_aliases;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_byte_offsets;

-tgc_c::tgc_c()  = default;
+tgc5c::tgc5c()  = default;

-tgc_c::~tgc_c() = default;
+tgc5c::~tgc5c() = default;

-void tgc_c::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<tgc_c>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
+void tgc5c::reset(uint64_t address) {
+    auto base_ptr = reinterpret_cast<traits<tgc5c>::reg_t*>(get_regs_base_ptr());
+    for(size_t i=0; i<traits<tgc5c>::NUM_REGS; ++i)
        *(base_ptr+i)=0;
    reg.PC=address;
    reg.NEXT_PC=reg.PC;
@ -59,11 +59,11 @@ void tgc_c::reset(uint64_t address) {
    reg.icount=0;
 }

-uint8_t *tgc_c::get_regs_base_ptr() {
+uint8_t *tgc5c::get_regs_base_ptr() {
 	return reinterpret_cast<uint8_t*>(&reg);
 }

-tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &addr) {
-    return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
+tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t &addr) {
+    return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5c>::addr_mask);
 }

--- a/src/iss/arch/tgc5c.h
+++ b/src/iss/arch/tgc5c.h
@ -30,8 +30,8 @@
 *
 *******************************************************************************/

-#ifndef _TGC_C_H_
-#define _TGC_C_H_
+#ifndef _TGC5C_H_
+#define _TGC5C_H_

 #include <array>
 #include <iss/arch/traits.h>
@ -41,17 +41,17 @@
 namespace iss {
 namespace arch {

-struct tgc_c;
+struct tgc5c;

-template <> struct traits<tgc_c> {
+template <> struct traits<tgc5c> {

-    constexpr static char const* const core_type = "TGC_C";
+    constexpr static char const* const core_type = "TGC5C";
    
    static constexpr std::array<const char*, 36> reg_names{
-        {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
+        {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}};
 
    static constexpr std::array<const char*, 36> reg_aliases{
-        {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
+        {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};

    enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL};

@ -141,49 +141,49 @@ template <> struct traits<tgc_c> {
        DIVU = 54,
        REM = 55,
        REMU = 56,
-        CADDI4SPN = 57,
-        CLW = 58,
-        CSW = 59,
-        CADDI = 60,
-        CNOP = 61,
-        CJAL = 62,
-        CLI = 63,
-        CLUI = 64,
-        CADDI16SP = 65,
+        C__ADDI4SPN = 57,
+        C__LW = 58,
+        C__SW = 59,
+        C__ADDI = 60,
+        C__NOP = 61,
+        C__JAL = 62,
+        C__LI = 63,
+        C__LUI = 64,
+        C__ADDI16SP = 65,
        __reserved_clui = 66,
-        CSRLI = 67,
-        CSRAI = 68,
-        CANDI = 69,
-        CSUB = 70,
-        CXOR = 71,
-        COR = 72,
-        CAND = 73,
-        CJ = 74,
-        CBEQZ = 75,
-        CBNEZ = 76,
-        CSLLI = 77,
-        CLWSP = 78,
-        CMV = 79,
-        CJR = 80,
+        C__SRLI = 67,
+        C__SRAI = 68,
+        C__ANDI = 69,
+        C__SUB = 70,
+        C__XOR = 71,
+        C__OR = 72,
+        C__AND = 73,
+        C__J = 74,
+        C__BEQZ = 75,
+        C__BNEZ = 76,
+        C__SLLI = 77,
+        C__LWSP = 78,
+        C__MV = 79,
+        C__JR = 80,
        __reserved_cmv = 81,
-        CADD = 82,
-        CJALR = 83,
-        CEBREAK = 84,
-        CSWSP = 85,
+        C__ADD = 82,
+        C__JALR = 83,
+        C__EBREAK = 84,
+        C__SWSP = 85,
        DII = 86,
        MAX_OPCODE
    };
 };

-struct tgc_c: public arch_if {
+struct tgc5c: public arch_if {

-    using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
-    using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
-    using reg_t =  typename traits<tgc_c>::reg_t;
-    using addr_t = typename traits<tgc_c>::addr_t;
+    using virt_addr_t = typename traits<tgc5c>::virt_addr_t;
+    using phys_addr_t = typename traits<tgc5c>::phys_addr_t;
+    using reg_t =  typename traits<tgc5c>::reg_t;
+    using addr_t = typename traits<tgc5c>::addr_t;

-    tgc_c();
-    ~tgc_c();
+    tgc5c();
+    ~tgc5c();

    void reset(uint64_t address=0) override;

@ -203,7 +203,7 @@ struct tgc_c: public arch_if {


 #pragma pack(push, 1)
-    struct TGC_C_regs { 
+    struct TGC5C_regs { 
        uint32_t X0 = 0; 
        uint32_t X1 = 0; 
        uint32_t X2 = 0; 
@ -254,8 +254,9 @@ struct tgc_c: public arch_if {

    uint32_t get_fcsr(){return 0;}
    void set_fcsr(uint32_t val){}
+
 };

 }
 }            
-#endif /* _TGC_C_H_ */
+#endif /* _TGC5C_H_ */
--- a/src/iss/arch/tgc_c_decoder.cpp
+++ b/src/iss/arch/tgc_c_decoder.cpp
@ -1,175 +0,0 @@
-#include "tgc_c.h"
-#include <vector>
-#include <array>
-#include <cstdlib>
-#include <algorithm>
-
-namespace iss {
-namespace arch {
-namespace {
-// according to
-// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
-#ifdef __GCC__
-constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
-#elif __cplusplus < 201402L
-constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
-constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
-#else
-constexpr size_t bit_count(uint32_t u) {
-    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
-    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
-}
-#endif
-
-using opcode_e = traits<tgc_c>::opcode_e;
-
-/****************************************************************************
- * start opcode definitions
- ****************************************************************************/
-struct instruction_desriptor {
-    size_t length;
-    uint32_t value;
-    uint32_t mask;
-    opcode_e op;
-};
-
-const std::array<instruction_desriptor, 90> instr_descr = {{
-     /* entries are: size, valid value, valid mask, function ptr */
-    {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, opcode_e::LUI},
-    {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, opcode_e::AUIPC},
-    {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, opcode_e::JAL},
-    {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, opcode_e::JALR},
-    {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, opcode_e::BEQ},
-    {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, opcode_e::BNE},
-    {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, opcode_e::BLT},
-    {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, opcode_e::BGE},
-    {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, opcode_e::BLTU},
-    {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, opcode_e::BGEU},
-    {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, opcode_e::LB},
-    {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, opcode_e::LH},
-    {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, opcode_e::LW},
-    {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, opcode_e::LBU},
-    {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, opcode_e::LHU},
-    {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, opcode_e::SB},
-    {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, opcode_e::SH},
-    {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, opcode_e::SW},
-    {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, opcode_e::ADDI},
-    {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, opcode_e::SLTI},
-    {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, opcode_e::SLTIU},
-    {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, opcode_e::XORI},
-    {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, opcode_e::ORI},
-    {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, opcode_e::ANDI},
-    {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, opcode_e::SLLI},
-    {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRLI},
-    {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRAI},
-    {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::ADD},
-    {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::SUB},
-    {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::SLL},
-    {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::SLT},
-    {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::SLTU},
-    {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::XOR},
-    {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRL},
-    {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRA},
-    {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::OR},
-    {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::AND},
-    {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE},
-    {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, opcode_e::ECALL},
-    {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, opcode_e::EBREAK},
-    {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::URET},
-    {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::SRET},
-    {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::MRET},
-    {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, opcode_e::WFI},
-    {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::DRET},
-    {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRW},
-    {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRS},
-    {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRC},
-    {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRWI},
-    {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRSI},
-    {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRCI},
-    {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE_I},
-    {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::MUL},
-    {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::MULH},
-    {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::MULHSU},
-    {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::MULHU},
-    {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::DIV},
-    {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::DIVU},
-    {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::REM},
-    {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::REMU},
-    {16, 0b0000000000000000, 0b1110000000000011, opcode_e::CADDI4SPN},
-    {16, 0b0100000000000000, 0b1110000000000011, opcode_e::CLW},
-    {16, 0b1100000000000000, 0b1110000000000011, opcode_e::CSW},
-    {16, 0b0000000000000001, 0b1110000000000011, opcode_e::CADDI},
-    {16, 0b0000000000000001, 0b1110111110000011, opcode_e::CNOP},
-    {16, 0b0010000000000001, 0b1110000000000011, opcode_e::CJAL},
-    {16, 0b0100000000000001, 0b1110000000000011, opcode_e::CLI},
-    {16, 0b0110000000000001, 0b1110000000000011, opcode_e::CLUI},
-    {16, 0b0110000100000001, 0b1110111110000011, opcode_e::CADDI16SP},
-    {16, 0b0110000000000001, 0b1111000001111111, opcode_e::__reserved_clui},
-    {16, 0b1000000000000001, 0b1111110000000011, opcode_e::CSRLI},
-    {16, 0b1000010000000001, 0b1111110000000011, opcode_e::CSRAI},
-    {16, 0b1000100000000001, 0b1110110000000011, opcode_e::CANDI},
-    {16, 0b1000110000000001, 0b1111110001100011, opcode_e::CSUB},
-    {16, 0b1000110000100001, 0b1111110001100011, opcode_e::CXOR},
-    {16, 0b1000110001000001, 0b1111110001100011, opcode_e::COR},
-    {16, 0b1000110001100001, 0b1111110001100011, opcode_e::CAND},
-    {16, 0b1010000000000001, 0b1110000000000011, opcode_e::CJ},
-    {16, 0b1100000000000001, 0b1110000000000011, opcode_e::CBEQZ},
-    {16, 0b1110000000000001, 0b1110000000000011, opcode_e::CBNEZ},
-    {16, 0b0000000000000010, 0b1111000000000011, opcode_e::CSLLI},
-    {16, 0b0100000000000010, 0b1110000000000011, opcode_e::CLWSP},
-    {16, 0b1000000000000010, 0b1111000000000011, opcode_e::CMV},
-    {16, 0b1000000000000010, 0b1111000001111111, opcode_e::CJR},
-    {16, 0b1000000000000010, 0b1111111111111111, opcode_e::__reserved_cmv},
-    {16, 0b1001000000000010, 0b1111000000000011, opcode_e::CADD},
-    {16, 0b1001000000000010, 0b1111000001111111, opcode_e::CJALR},
-    {16, 0b1001000000000010, 0b1111111111111111, opcode_e::CEBREAK},
-    {16, 0b1100000000000010, 0b1110000000000011, opcode_e::CSWSP},
-    {16, 0b0000000000000000, 0b1111111111111111, opcode_e::DII},
-}};
-
-}
-
-template<>
-struct instruction_decoder<tgc_c> {
-    using opcode_e = traits<tgc_c>::opcode_e;
-    using code_word_t=traits<tgc_c>::code_word_t;
-
-    struct instruction_pattern {
-        uint32_t value;
-        uint32_t mask;
-        opcode_e id;
-    };
-
-    std::array<std::vector<instruction_pattern>, 4> qlut;
-
-    template<typename T>
-    unsigned decode_instruction(T);
-
-    instruction_decoder() {
-        for (auto instr : instr_descr) {
-            auto quadrant = instr.value & 0x3;
-            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
-        }
-        for(auto& lut: qlut){
-            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
-                return bit_count(a.mask) > bit_count(b.mask);
-            });
-        }
-    }
-};
-
-template<>
-unsigned instruction_decoder<tgc_c>::decode_instruction<traits<tgc_c>::code_word_t>(traits<tgc_c>::code_word_t instr){
-    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
-        return !((instr&e.mask) ^ e.value );
-    });
-    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
-}
-
-
-std::unique_ptr<instruction_decoder<tgc_c>> traits<tgc_c>::get_decoder(){
-    return std::make_unique<instruction_decoder<tgc_c>>();
-}
-
-}
-}
--- a/src/iss/arch/tgc_mapper.h
+++ b/src/iss/arch/tgc_mapper.h
@ -2,49 +2,49 @@
 #define _ISS_ARCH_TGC_MAPPER_H

 #include "riscv_hart_m_p.h"
-#include "tgc_c.h"
-using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
-#ifdef CORE_TGC_A
+#include "tgc5c.h"
+using tgc5c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5c>;
+#ifdef CORE_TGC5A
 #include "riscv_hart_m_p.h"
-#include <iss/arch/tgc_a.h>
-using tgc_a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_a>;
+#include <iss/arch/tgc5a.h>
+using tgc5a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5a>;
 #endif
-#ifdef CORE_TGC_B
+#ifdef CORE_TGC5B
 #include "riscv_hart_m_p.h"
-#include <iss/arch/tgc_b.h>
-using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
+#include <iss/arch/tgc5b.h>
+using tgc5b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5b>;
 #endif
-#ifdef CORE_TGC_C_XRB_NN
+#ifdef CORE_TGC5C_XRB_NN
 #include "riscv_hart_m_p.h"
 #include "hwl.h"
-#include <iss/arch/tgc_c_xrb_nn.h>
-using tgc_c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>>;
+#include <iss/arch/tgc5c_xrb_nn.h>
+using tgc5c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc5c_xrb_nn>>;
 #endif
-#ifdef CORE_TGC_D
+#ifdef CORE_TGC5D
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc_d.h>
-using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#include <iss/arch/tgc5d.h>
+using tgc5d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
-#ifdef CORE_TGC_D_XRB_MAC
+#ifdef CORE_TGC5D_XRB_MAC
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc_d_xrb_mac.h>
-using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#include <iss/arch/tgc5d_xrb_mac.h>
+using tgc5d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
-#ifdef CORE_TGC_D_XRB_NN
+#ifdef CORE_TGC5D_XRB_NN
 #include "riscv_hart_mu_p.h"
 #include "hwl.h"
-#include <iss/arch/tgc_d_xrb_nn.h>
-using tgc_d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
+#include <iss/arch/tgc5d_xrb_nn.h>
+using tgc5d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
 #endif
-#ifdef CORE_TGC_E
+#ifdef CORE_TGC5E
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc_e.h>
-using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#include <iss/arch/tgc5e.h>
+using tgc5e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
-#ifdef CORE_TGC_X
+#ifdef CORE_TGC5X
 #include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc_x.h>
-using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
+#include <iss/arch/tgc5x.h>
+using tgc5x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
 #endif

 #endif
--- a/src/iss/arch/wt_cache.h
+++ b/src/iss/arch/wt_cache.h
@ -81,7 +81,7 @@ public:
    using mem_write_f = typename BASE::mem_write_f;
    using phys_addr_t = typename BASE::phys_addr_t;

-    wt_cache();
+    wt_cache(feature_config cfg = feature_config{});
    virtual ~wt_cache() = default;

    unsigned size{4096};
@ -103,7 +103,11 @@ protected:


 template<typename BASE>
-inline wt_cache<BASE>::wt_cache() {
+inline wt_cache<BASE>::wt_cache(feature_config cfg)
+:BASE(cfg)
+, io_address{cfg.io_address}
+, io_addr_mask{cfg.io_addr_mask}
+{
    auto cb = base_class::replace_mem_access(
            [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l,d);},
            [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l,d);});
--- a/src/iss/plugin/README.md
+++ b/src/iss/plugin/README.md
@ -0,0 +1,8 @@
+# pctrace
+
+Trace functionality to allow visualizing coverage in lcov and cachegrind tools. Use environment variables NOCOMPRES and REGDUMP to toggle functionality.
+- NOCOMPRES: any value turns off the LZ4 compression
+- REGDUMP: any value switches to tracing the registers instead. Also turns off compression.
+
+Known Bugs: 
+- currently does not work correctly with jit backends, the plugin cant tell if instructions are compressed. Additionaly the cost of instrs that raise a trap is not known. It takes the cost of the instrid -1 (0 at the moment).
--- a/src/iss/plugin/cycle_estimate.cpp
+++ b/src/iss/plugin/cycle_estimate.cpp
@ -33,18 +33,12 @@
 ******************************************************************************/

 #include "cycle_estimate.h"
+#include <yaml-cpp/yaml.h>

 #include <iss/arch_if.h>
 #include <util/logging.h>
-#include <rapidjson/document.h>
-#include <rapidjson/istreamwrapper.h>
-#include <rapidjson/writer.h>
-#include <rapidjson/stringbuffer.h>
-#include <rapidjson/ostreamwrapper.h>
-#include <rapidjson/error/en.h>
 #include <fstream>

-using namespace rapidjson;
 using namespace std;

 iss::plugin::cycle_estimate::cycle_estimate(string const& config_file_name)
@ -61,40 +55,31 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
    if(!instr_if) return false;
    const string  core_name = instr_if->core_type_name();
    if (config_file_name.length() > 0) {
-        ifstream is(config_file_name);
+        std::ifstream is(config_file_name);
        if (is.is_open()) {
            try {
-                IStreamWrapper isw(is);
-                Document d;
-                ParseResult ok = d.ParseStream(isw);
-                if(ok) {
-                    Value& val = d[core_name.c_str()];
-                    if(val.IsArray()){
-                        delays.reserve(val.Size());
-                        for (auto it = val.Begin(); it != val.End(); ++it) {
-                            auto& name = (*it)["name"];
-                            auto& size = (*it)["size"];
-                            auto& delay = (*it)["delay"];
-                            auto& branch = (*it)["branch"];
-                            if(delay.IsArray()) {
-                                auto dt = delay[0].Get<unsigned>();
-                                auto dnt = delay[1].Get<unsigned>();
-                                delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
-                            } else if(delay.Is<unsigned>()) {
-                                auto d = delay.Get<unsigned>();
-                                delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
-                            } else
-                                throw runtime_error("JSON parse error");
+                auto root = YAML::LoadAll(is);
+                if(root.size()!=1) {
+                    LOG(ERR) << "Too many rro nodes in YAML file " << config_file_name;
                }
+                for (auto p : root[0]) {
+                    auto isa_subset = p.first;
+                    auto instructions = p.second;
+                    for (auto const& instr : instructions) {
+                        instr_desc res;
+                        res.is_branch = instr.second["branch"].as<bool>();
+                        auto delay = instr.second["delay"];
+                        if(delay.IsSequence()) {
+                            res.not_taken = delay[0].as<uint64_t>();
+                            res.taken = delay[1].as<uint64_t>();
                        } else {
-                        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
-                        return false;
+                            res.not_taken = delay.as<uint64_t>();
+                            res.taken = res.not_taken;
                        }
-                } else {
-                    LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
-                    return false;
+                        delays.push_back(std::move(res));
                    }
-            } catch (runtime_error &e) {
+                }
+            } catch (YAML::ParserException &e) {
                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
                return false;
            }
--- a/src/iss/plugin/instruction_count.cpp
+++ b/src/iss/plugin/instruction_count.cpp
@ -34,6 +34,7 @@

 #include "instruction_count.h"
 #include <iss/instrumentation_if.h>
+#include <yaml-cpp/yaml.h>

 #include <iss/arch_if.h>
 #include <util/logging.h>
@ -44,8 +45,30 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
        std::ifstream is(config_file_name);
        if (is.is_open()) {
            try {
-                is >> root;
-            } catch (Json::RuntimeError &e) {
+                auto root = YAML::LoadAll(is);
+                if(root.size()!=1) {
+                    LOG(ERR) << "Too many rro nodes in YAML file " << config_file_name;
+                }
+                for (auto p : root[0]) {
+                    auto isa_subset = p.first;
+                    auto instructions = p.second;
+                    for (auto const& instr : instructions) {
+                        instr_delay res;
+                        res.instr_name = instr.first.as<std::string>();
+                        res.size = instr.second["encoding"].as<std::string>().size()-2; // not counting 0b
+                        auto delay = instr.second["delay"];
+                        if(delay.IsSequence()) {
+                            res.not_taken_delay = delay[0].as<uint64_t>();
+                            res.taken_delay = delay[1].as<uint64_t>();
+                        } else {
+                            res.not_taken_delay = delay.as<uint64_t>();
+                            res.taken_delay = res.not_taken_delay;
+                        }
+                        delays.push_back(std::move(res));
+                    }
+                }
+                rep_counts.resize(delays.size());
+            } catch (YAML::ParserException &e) {
                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
            }
        } else {
@ -57,7 +80,7 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
 iss::plugin::instruction_count::~instruction_count() {
 	size_t idx=0;
 	for(auto it:delays){
-		if(rep_counts[idx]>0)
+		if(rep_counts[idx]>0 && it.instr_name.find("__"!=0))
 			LOG(INFO)<<it.instr_name<<";"<<rep_counts[idx];
 		idx++;
 	}
@ -66,27 +89,6 @@ iss::plugin::instruction_count::~instruction_count() {
 bool iss::plugin::instruction_count::registration(const char* const version, vm_if& vm) {
    auto instr_if = vm.get_arch()->get_instrumentation_if();
    if(!instr_if) return false;
-	const std::string  core_name = instr_if->core_type_name();
-    Json::Value &val = root[core_name];
-    if(!val.isNull() && val.isArray()){
-    	delays.reserve(val.size());
-    	for(auto it:val){
-    		auto name = it["name"];
-    		auto size = it["size"];
-    		auto delay = it["delay"];
-    		if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error");
-    		if(delay.isUInt()){
-				const instr_delay entry{name.asCString(), size.asUInt(), delay.asUInt(), 0};
-				delays.push_back(entry);
-    		} else {
-				const instr_delay entry{name.asCString(), size.asUInt(), delay[0].asUInt(), delay[1].asUInt()};
-				delays.push_back(entry);
-    		}
-    	}
-    	rep_counts.resize(delays.size());
-    } else {
-        LOG(ERR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
-    }
 	return true;
 }

--- a/src/iss/plugin/instruction_count.h
+++ b/src/iss/plugin/instruction_count.h
@ -36,8 +36,8 @@
 #define _ISS_PLUGIN_INSTRUCTION_COUNTER_H_

 #include <iss/vm_plugin.h>
-#include <json/json.h>
 #include <string>
+#include <vector>

 namespace iss {
 namespace plugin {
@ -72,7 +72,6 @@ public:
    void callback(instr_info_t) override;

 private:
-    Json::Value root;
    std::vector<instr_delay> delays;
    std::vector<uint64_t> rep_counts;
 };
--- a/src/iss/plugin/pctrace.cpp
+++ b/src/iss/plugin/pctrace.cpp
@ -1,214 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Contributors:
- *       alex.com - initial implementation
- ******************************************************************************/
-
-#include <iss/arch_if.h>
-#include <iss/plugin/pctrace.h>
-#include <util/logging.h>
-#include <util/ities.h>
-#include <rapidjson/document.h>
-#include <rapidjson/istreamwrapper.h>
-#include <rapidjson/writer.h>
-#include <rapidjson/stringbuffer.h>
-#include <rapidjson/ostreamwrapper.h>
-#include <rapidjson/error/en.h>
-#include <fstream>
-#include <iostream>
-#ifdef WITH_LZ4
-#include <lz4frame.h>
-#endif
-
-namespace iss {
-namespace plugin {
-
-using namespace rapidjson;
-using namespace std;
-
-#ifdef WITH_LZ4
-class lz4compress_steambuf: public std::streambuf {
-public:
-    lz4compress_steambuf(const lz4compress_steambuf&) = delete;
-    lz4compress_steambuf& operator=(const lz4compress_steambuf&) = delete;
-    lz4compress_steambuf(std::ostream &sink, size_t buf_size)
-    : sink(sink)
-    , src_buf(buf_size)
-    , dest_buf(LZ4F_compressBound(buf_size, nullptr))
-    {
-        auto errCode = LZ4F_createCompressionContext(&ctx, LZ4F_VERSION);
-        if (LZ4F_isError(errCode) != 0)
-            throw std::runtime_error(std::string("Failed to create LZ4 context: ") + LZ4F_getErrorName(errCode));
-        size_t ret = LZ4F_compressBegin(ctx, &dest_buf.front(), dest_buf.capacity(), nullptr);
-        if (LZ4F_isError(ret) != 0)
-            throw std::runtime_error(std::string("Failed to start LZ4 compression: ") + LZ4F_getErrorName(ret));
-        setp(src_buf.data(), src_buf.data() + src_buf.size() - 1);
-        sink.write(dest_buf.data(), ret);
-    }
-
-    ~lz4compress_steambuf() {
-        close();
-    }
-
-    void close() {
-        if (closed)
-            return;
-        sync();
-        auto ret = LZ4F_compressEnd(ctx, dest_buf.data(), dest_buf.capacity(), nullptr);
-        if (LZ4F_isError(ret) != 0)
-            throw std::runtime_error(std::string("Failed to finish LZ4 compression: ") + LZ4F_getErrorName(ret));
-        sink.write(dest_buf.data(), ret);
-        LZ4F_freeCompressionContext(ctx);
-        closed = true;
-    }
-
-private:
-    int_type overflow(int_type ch) override {
-        compress_and_write();
-        *pptr() = static_cast<char_type>(ch);
-        pbump(1);
-        return ch;
-    }
-
-    int_type sync() override {
-        compress_and_write();
-        return 0;
-    }
-
-    void compress_and_write() {
-        if (closed)
-            throw std::runtime_error("Cannot write to closed stream");
-        if(auto orig_size = pptr() - pbase()){
-            auto ret = LZ4F_compressUpdate(ctx, dest_buf.data(), dest_buf.capacity(), pbase(), orig_size, nullptr);
-            if (LZ4F_isError(ret) != 0)
-                throw std::runtime_error(std::string("LZ4 compression failed: ") + LZ4F_getErrorName(ret));
-            if(ret) sink.write(dest_buf.data(), ret);
-            pbump(-orig_size);
-        }
-    }
-
-    std::ostream &sink;
-    std::vector<char> src_buf;
-    std::vector<char> dest_buf;
-    LZ4F_compressionContext_t ctx{ nullptr };
-    bool closed{ false };
-};
-#endif
-
-pctrace::pctrace(std::string const &filename)
-: instr_if(nullptr)
-, filename(filename)
-, output("output.trc")
-#ifdef WITH_LZ4
-, strbuf(new lz4compress_steambuf(output, 4096))
-, ostr(strbuf.get())
-#endif
-{ }
-
-pctrace::~pctrace() { }
-
-bool pctrace::registration(const char *const version, vm_if& vm) {
-    instr_if = vm.get_arch()->get_instrumentation_if();
-    if(!instr_if) return false;
-    const string  core_name = instr_if->core_type_name();
-    if (filename.length() > 0) {
-        ifstream is(filename);
-        if (is.is_open()) {
-            try {
-                IStreamWrapper isw(is);
-                Document d;
-                ParseResult ok = d.ParseStream(isw);
-                if(ok) {
-                    Value& val = d[core_name.c_str()];
-                    if(val.IsArray()){
-                        delays.reserve(val.Size());
-                        for (auto it = val.Begin(); it != val.End(); ++it) {
-                            auto& name = (*it)["name"];
-                            auto& size = (*it)["size"];
-                            auto& delay = (*it)["delay"];
-                            auto& branch = (*it)["branch"];
-                            if(delay.IsArray()) {
-                                auto dt = delay[0].Get<unsigned>();
-                                auto dnt = delay[1].Get<unsigned>();
-                                delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
-                            } else if(delay.Is<unsigned>()) {
-                                auto d = delay.Get<unsigned>();
-                                delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
-                            } else
-                                throw runtime_error("JSON parse error");
-
-                        }
-                    } else {
-                        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
-                        return false;
-                    }
-                } else {
-                    LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
-                    return false;
-                }
-            } catch (runtime_error &e) {
-                LOG(ERR) << "Could not parse input file " << filename << ", reason: " << e.what();
-                return false;
-            }
-        } else {
-            LOG(ERR) << "Could not open input file " << filename;
-            return false;
-        }
-    }
-    return true;
-}
-
-void pctrace::callback(instr_info_t iinfo) {
-    auto delay = 0;
-    size_t id = iinfo.instr_id;
-    auto entry = delays[id];
-    auto instr = instr_if->get_instr_word();
-    auto call = id==65 || id ==86 || ((id==2 || id==3) && bit_sub<7,5>(instr)!=0) ;//not taking care of tail calls (jalr with loading x6)
-    bool taken = instr_if->is_branch_taken();
-    bool compressed = (instr&0x3)!=0x3;
-    if (taken) {
-        delay = entry.taken;
-        if(entry.taken > 1)
-            instr_if->update_last_instr_cycles(entry.taken);
-    } else {
-        delay = entry.not_taken;
-        if (entry.not_taken > 1)
-            instr_if->update_last_instr_cycles(entry.not_taken);
-    }
-#ifndef WITH_LZ4
-    output<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
-#else
-    auto rdbuf=ostr.rdbuf();
-    ostr<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
-#endif
-}
-}
-}
--- a/src/iss/plugin/pctrace.h
+++ b/src/iss/plugin/pctrace.h
@ -1,101 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Contributors:
- *       eyck@minres.com - initial API and implementation
- ******************************************************************************/
-
-#ifndef _ISS_PLUGIN_COV_H_
-#define _ISS_PLUGIN_COV_H_
-
-#include <iss/vm_plugin.h>
-#include "iss/instrumentation_if.h"
-#include <string>
-#include <fstream>
-
-
-namespace iss {
-namespace plugin {
-class lz4compress_steambuf;
-class pctrace : public iss::vm_plugin {
-    struct instr_delay {
-        std::string instr_name;
-        size_t size;
-        size_t not_taken_delay;
-        size_t taken_delay;
-    };
-    BEGIN_BF_DECL(instr_desc, uint32_t)
-        BF_FIELD(taken, 24, 8)
-        BF_FIELD(not_taken, 16, 8)
-        BF_FIELD(is_branch, 8, 8)
-        BF_FIELD(size, 0, 8)
-        instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
-            this->size=size;
-            this->taken=taken;
-            this->not_taken=not_taken;
-            this->is_branch=branch;
-        }
-    END_BF_DECL();
-
-public:
-
-    pctrace(const pctrace &) = delete;
-
-    pctrace(const pctrace &&) = delete;
-
-    pctrace(std::string const &);
-
-    virtual ~pctrace();
-
-    pctrace &operator=(const pctrace &) = delete;
-
-    pctrace &operator=(const pctrace &&) = delete;
-
-    bool registration(const char *const version, vm_if &arch) override;
-
-    sync_type get_sync() override { return POST_SYNC; };
-
-    void callback(instr_info_t) override;
-
-private:
-    iss::instrumentation_if *instr_if  {nullptr};
-    std::ofstream output;
-#ifdef WITH_LZ4
-    std::unique_ptr<lz4compress_steambuf> strbuf;
-    std::ostream ostr;
-#endif
-    std::string filename;
-    std::vector<instr_desc> delays;
-    bool jumped{false}, first{true};
-};
-}
-}
-
-#endif /* _ISS_PLUGIN_COV_H_ */
--- a/src/main.cpp
+++ b/src/main.cpp
@ -44,7 +44,6 @@
 #include <iss/log_categories.h>
 #include "iss/plugin/cycle_estimate.h"
 #include "iss/plugin/instruction_count.h"
-#include "iss/plugin/pctrace.h"
 #ifndef WIN32
 #include <iss/plugin/loader.h>
 #endif
@ -74,14 +73,14 @@ int main(int argc, char *argv[]) {
        ("mem,m", po::value<std::string>(), "the memory input file")
        ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
        ("backend", po::value<std::string>()->default_value("interp"), "the ISS backend to use, options are: interp, tcc")
-        ("isa", po::value<std::string>()->default_value("tgc_c"), "isa to use for simulation");
+        ("isa", po::value<std::string>()->default_value("tgc5c"), "core or isa name to use for simulation, use '?' to get list");
    // clang-format on
    auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
    try {
        po::store(parsed, clim); // can throw
        // --help option
        if (clim.count("help")) {
-            std::cout << "DBT-RISE-RiscV simulator for RISC-V" << std::endl << desc << std::endl;
+            std::cout << "DBT-RISE-TGC simulator for TGC RISC-V cores" << std::endl << desc << std::endl;
            return 0;
        }
        po::notify(clim); // throws on error, so do after help in case
@ -119,13 +118,15 @@ int main(int argc, char *argv[]) {
        iss::cpu_ptr cpu{nullptr};
        std::string isa_opt(clim["isa"].as<std::string>());
        if(isa_opt.size()==0 || isa_opt == "?") {
-            std::cout<<"Available cores: "<<util::join(f.get_names(), ", ")<<std::endl;
+            auto list = f.get_names();
+            std::sort(std::begin(list), std::end(list));
+            std::cout<<"Available implementations (core|platform|backend):\n  - "<<util::join(list, "\n  - ")<<std::endl;
            return 0;
        } else if (isa_opt.find('|') != std::string::npos) {
            std::tie(cpu, vm) = f.create(isa_opt+"|"+clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
        } else {
            auto base_isa = isa_opt.substr(0, 5);
-            if(base_isa=="tgc_d" || base_isa=="tgc_e") {
+            if(base_isa=="tgc5d" || base_isa=="tgc5e") {
                isa_opt += "|mu_p_clic_pmp|"+clim["backend"].as<std::string>();
            } else {
                isa_opt += "|m_p|"+clim["backend"].as<std::string>();
@ -149,6 +150,7 @@ int main(int argc, char *argv[]) {
                    plugin_name = opt_val.substr(0, found);
                    arg = opt_val.substr(found + 1, opt_val.size());
                }
+#if defined(WITH_PLUGINS)
                if (plugin_name == "ic") {
                    auto *ic_plugin = new iss::plugin::instruction_count(arg);
                    vm->register_plugin(*ic_plugin);
@ -157,12 +159,10 @@ int main(int argc, char *argv[]) {
                    auto *ce_plugin = new iss::plugin::cycle_estimate(arg);
                    vm->register_plugin(*ce_plugin);
                    plugin_list.push_back(ce_plugin);
-                } else if (plugin_name == "pctrace") {
-                    auto *plugin = new iss::plugin::pctrace(arg);
-                    vm->register_plugin(*plugin);
-                    plugin_list.push_back(plugin);
-               } else {
-#ifndef WIN32
+                } else
+#endif
+                {
+#if !defined(WIN32)
                    std::vector<char const*> a{};
                    if(arg.length())
                        a.push_back({arg.c_str()});
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@ -50,7 +50,6 @@
 #include <array>
 #include <iss/plugin/cycle_estimate.h>
 #include <iss/plugin/instruction_count.h>
-#include <iss/plugin/pctrace.h>

 // clang-format on

@ -147,8 +146,8 @@ public:
            std::tie(cpu, vm) = f.create(type+"|"+backend);
        } else {
            auto base_isa = type.substr(0, 5);
-            if(base_isa=="tgc_d" || base_isa=="tgc_e") {
-                std::tie(cpu, vm) = f.create(type + "|mu_p_clic_pmp|" + backend, gdb_port, owner);
+            if(base_isa=="tgc5d" || base_isa=="tgc5e") {
+                std::tie(cpu, vm) = f.create(type + "|mu_p_clic_pmp|" + backend, gdb_port);
            } else {
                std::tie(cpu, vm) = f.create(type + "|m_p|" + backend, gdb_port, owner);
           }
@ -283,10 +282,6 @@ void core_complex::before_end_of_elaboration() {
                auto *plugin = new iss::plugin::cycle_estimate(filename);
                cpu->vm->register_plugin(*plugin);
                plugin_list.push_back(plugin);
-            } else if (plugin_name == "pctrace") {
-                auto *plugin = new iss::plugin::pctrace(filename);
-                cpu->vm->register_plugin(*plugin);
-                plugin_list.push_back(plugin);
            } else {
 #ifndef WIN32
                std::array<char const*, 1> a{{filename.c_str()}};
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@ -96,7 +96,7 @@ public:

    cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};

-    cci::cci_param<std::string> core_type{"core_type", "tgc_c"};
+    cci::cci_param<std::string> core_type{"core_type", "tgc5c"};

    cci::cci_param<std::string> backend{"backend", "interp"};

@ -121,7 +121,7 @@ public:

    scml_property<unsigned long long> reset_address{"reset_address", 0ULL};

-    scml_property<std::string> core_type{"core_type", "tgc_c"};
+    scml_property<std::string> core_type{"core_type", "tgc5c"};

    scml_property<std::string> backend{"backend", "interp"};

@ -139,7 +139,7 @@ public:
    , elf_file{"elf_file", ""}
    , enable_disass{"enable_disass", false}
    , reset_address{"reset_address", 0ULL}
-    , core_type{"core_type", "tgc_c"}
+    , core_type{"core_type", "tgc5c"}
    , backend{"backend", "interp"}
    , gdb_server_port{"gdb_server_port", 0}
    , dump_ir{"dump_ir", false}
--- a/src/sysc/register_tgc_c.cpp
+++ b/src/sysc/register_tgc_c.cpp
@ -31,7 +31,7 @@
 *******************************************************************************/

 #include "iss_factory.h"
-#include <iss/arch/tgc_c.h>
+#include <iss/arch/tgc5c.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
 #include "sc_core_adapter.h"
@ -42,15 +42,15 @@ namespace iss {
 namespace interp {
 using namespace sysc;
 volatile std::array<bool, 2> tgc_init = {
-        iss_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc_c*>(cpu), gdb_port)}};
+        iss_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
        }),
-        iss_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc_c*>(cpu), gdb_port)}};
+        iss_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
        })
 };
 }
@ -58,15 +58,15 @@ volatile std::array<bool, 2> tgc_init = {
 namespace tcc {
 using namespace sysc;
 volatile std::array<bool, 2> tgc_init = {
-        iss_factory::instance().register_creator("tgc_c|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc_c*>(cpu), gdb_port)}};
+        iss_factory::instance().register_creator("tgc5c|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
        }),
-        iss_factory::instance().register_creator("tgc_c|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
-            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc_c*>(cpu), gdb_port)}};
+        iss_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
+            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
+            return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
        })
 };
 }
--- a/src/vm/interp/vm_tgc5c.cpp
+++ b/src/vm/interp/vm_tgc5c.cpp
--- a/src/vm/interp/vm_tgc_c.cpp
+++ b/src/vm/interp/vm_tgc_c.cpp
--- a/src/vm/llvm/vm_tgc5c.cpp
+++ b/src/vm/llvm/vm_tgc5c.cpp
--- a/src/vm/llvm/vm_tgc_c.cpp
+++ b/src/vm/llvm/vm_tgc_c.cpp
--- a/src/vm/tcc/vm_tgc5c.cpp
+++ b/src/vm/tcc/vm_tgc5c.cpp
Author	SHA1	Message	Date
Eyck Jentzsch	ae4322c1b9	„src/main.cpp“ ändern	2023-10-15 09:03:31 +02:00
Stanislaw Kaushanski	9180ad1f9c	debugger memory accesses should never lead to traps	2023-10-06 21:39:48 +02:00
Eyck Jentzsch	ee6a068b06	streamlines backends and reporting	2023-10-01 18:33:14 +02:00
Eyck Jentzsch	b9b165465d	adds some template updates	2023-09-30 22:17:18 +02:00
Eyck Jentzsch	b97853ff5a	update plugins to read YAML file	2023-09-30 22:10:24 +02:00
Eyck Jentzsch	b7f023756e	fixes constructor calls of derived riscv_hart classes	2023-09-27 07:51:49 +02:00
Eyck Jentzsch	2095ac985b	fixes forgotten removal of pctrace in core_complex	2023-09-27 06:19:59 +02:00
Eyck Jentzsch	3fb8fe765a	aligns riscv_hart_msu_vp with riscv_hart_m_p	2023-09-26 20:17:26 +02:00
Eyck-Alexander Jentzsch	5fd226b670	moves pctrace	2023-09-25 09:44:51 +02:00
Eyck-Alexander Jentzsch	417076f8e6	stops jit block creation in case of ECALL and EBREAK	2023-09-23 11:30:58 +02:00
Eyck-Alexander Jentzsch	70839bbbf2	changes templates for correct plugin callback in case of trap	2023-09-23 10:35:21 +02:00
Eyck-Alexander Jentzsch	8db0cc5d05	removes clutter	2023-09-23 10:34:58 +02:00
Eyck-Alexander Jentzsch	212fb1c8ff	adds tracing functionality	2023-09-22 12:40:35 +02:00
Eyck-Alexander Jentzsch	f74f98f361	improves readability	2023-09-22 12:40:12 +02:00
Eyck-Alexander Jentzsch	f074092a78	Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop	2023-09-20 15:18:05 +02:00
Eyck-Alexander Jentzsch	633c0d21a0	Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop	2023-09-20 15:17:43 +02:00
Eyck-Alexander Jentzsch	51f6fbe0dd	applies newest CoreDSL changes	2023-09-20 15:12:03 +02:00
Eyck-Alexander Jentzsch	de45d06878	adds initial working version of llvm backend	2023-09-19 16:26:07 +02:00
Eyck Jentzsch	c7038cafa5	updates naming in checked-in sources	2023-09-19 12:11:49 +02:00
Eyck Jentzsch	40f50b0ec0	changes register names to lower case in printing	2023-09-09 18:54:18 +02:00
Eyck-Alexander Jentzsch	b360fc2c75	Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop	2023-09-05 10:08:49 +02:00
Eyck-Alexander Jentzsch	e21f8dc379	allows functions in interp and updates generated	2023-09-05 10:08:00 +02:00
Eyck Jentzsch	8ee3ac90f7	adapts name changes	2023-09-04 12:45:45 +02:00
Eyck Jentzsch	d5763d2f36	fixes option depended compilation	2023-08-30 17:11:50 +02:00
Eyck Jentzsch	b5d915f389	fixes compile issues from merge	2023-08-30 15:49:28 +02:00
Eyck Jentzsch	813b40409d	Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop	2023-08-30 10:05:42 +02:00
Eyck Jentzsch	c8a4a4c736	renames core(s)	2023-08-28 07:09:55 +02:00