 Eyck Jentzsch
|
b5d915f389
|
fixes compile issues from merge
|
2023-08-30 15:49:28 +02:00 |
|
Eyck Jentzsch
|
813b40409d
|
Merge branch 'develop' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop
|
2023-08-30 10:05:42 +02:00 |
|
Eyck Jentzsch
|
c8a4a4c736
|
renames core(s)
|
2023-08-28 07:09:55 +02:00 |
|
Eyck Jentzsch
|
20e920338c
|
removes v2p function
|
2023-08-04 13:08:10 +02:00 |
|
Eyck Jentzsch
|
24de2bbdf5
|
purge build system
|
2023-07-30 13:55:57 +02:00 |
|
Eyck Jentzsch
|
957145ca84
|
add SystemC ISS factory
|
2023-07-14 11:11:03 +02:00 |
|
Eyck Jentzsch
|
0b719a4b57
|
fixes literal type
|
2023-07-10 20:39:02 +02:00 |
|
Eyck Jentzsch
|
250ea3c980
|
extends factory to support SystemC core wrapper
|
2023-07-09 18:19:59 +02:00 |
 Eyck-Alexander Jentzsch
|
7b31b8ca8e
|
adds updated generated files
|
2023-07-09 16:58:47 +02:00 |
|
Eyck-Alexander Jentzsch
|
87b4082633
|
Merge branch 'tmp' into develop
|
2023-07-03 14:22:50 +02:00 |
|
Eyck Jentzsch
|
4dbc7433a5
|
fixes cause CSR handling
|
2023-06-12 17:38:56 +02:00 |
|
Eyck Jentzsch
|
99a9970ddd
|
fixes sysc compile issues
|
2023-06-12 09:58:24 +02:00 |
|
Eyck Jentzsch
|
0b5de90fb1
|
changes [m|u]cause rd/wr handling
|
2023-06-11 18:29:58 +02:00 |
|
Eyck-Alexander Jentzsch
|
2281ec4144
|
corrects errors and adds new backend and
|
2023-06-05 15:18:27 +02:00 |
|
Eyck-Alexander Jentzsch
|
11c481cec2
|
adds verbosity to error
|
2023-06-05 15:17:16 +02:00 |
|
Eyck Jentzsch
|
a123beb301
|
fixes duplicate variable declaration and templates
|
2023-05-27 10:20:49 +02:00 |
|
Eyck Jentzsch
|
ee6218279e
|
adapts to latest code gen changes
|
2023-05-25 12:52:30 +02:00 |
|
Eyck-Alexander Jentzsch
|
6ed7eafc5d
|
adds inital version of tcc backend
|
2023-05-16 21:51:35 +02:00 |
|
Eyck Jentzsch
|
32848ec396
|
fixes build system and typo in wt_cache
|
2023-05-13 16:57:01 +02:00 |
|
Eyck Jentzsch
|
aa70d8a54a
|
fixes CLIC to match clicinfo description in CLIC spec 11.04.2023
|
2023-05-02 17:22:13 +02:00 |
|
Eyck Jentzsch
|
d990f1cf5d
|
fixes reading of 64bit CSR register
|
2023-05-01 22:23:35 +02:00 |
|
Eyck Jentzsch
|
1672b01e62
|
adds WT cache functionality as mixin
|
2023-04-28 20:38:07 +02:00 |
|
Eyck Jentzsch
|
00b0f101ac
|
adapts to changes of instrumentation interface in dbt-rise-core
|
2023-04-28 20:38:07 +02:00 |
|
Eyck Jentzsch
|
f626ee2684
|
fixes privilege wrapper for M/U to cope with 64bit
|
2023-04-05 15:38:25 +02:00 |
|
Eyck Jentzsch
|
98dd329833
|
fixes CSR access rights
|
2023-04-04 09:23:08 +02:00 |
|
Eyck Jentzsch
|
6213445bc4
|
fixes 64bit behavior of CSR regs
|
2023-03-27 12:04:43 +02:00 |
|
Eyck Jentzsch
|
2e4faa4d50
|
fixes mstatus mask
|
2023-03-25 09:14:56 +01:00 |
|
Eyck Jentzsch
|
8e1951f298
|
adds 64bit mstatus
|
2023-03-23 07:47:21 +01:00 |
|
Eyck Jentzsch
|
7efa924510
|
fixes m/uintstatus read
|
2023-03-17 10:51:39 +01:00 |
|
Eyck Jentzsch
|
febbc4fff0
|
fixes m/uintstatus read
|
2023-03-17 10:23:05 +01:00 |
|
Eyck Jentzsch
|
39b2788b7e
|
implements and fixes CLIC CSR behavior
|
2023-03-17 09:09:09 +01:00 |
|
Eyck Jentzsch
|
a943dd3bdf
|
fixes wrong array size which led to unintended CSR definitions
|
2023-03-15 14:16:08 +01:00 |
|
Eyck Jentzsch
|
fedbff5971
|
fixes xcause and u-mode clic CSRs
|
2023-03-15 12:27:39 +01:00 |
|
Eyck Jentzsch
|
c2758e8321
|
removes mscratchcsw from CLIC feature
|
2023-03-15 09:07:00 +01:00 |
|
Eyck Jentzsch
|
8be5fe71df
|
fixes template name typo
|
2023-03-12 07:42:09 +01:00 |
|
Eyck Jentzsch
|
3f7ce41b9d
|
fixes CLIC mtvt register behavior
|
2023-03-11 14:03:03 +01:00 |
|
Eyck Jentzsch
|
ad1cbedf00
|
adds back missing max irq functions
|
2023-03-11 12:47:10 +01:00 |
|
Eyck Jentzsch
|
83f54b5074
|
fixes CLICCFG settings
|
2023-03-11 08:48:03 +01:00 |
|
Eyck Jentzsch
|
a83928fd8c
|
fixes CSR/CLIC implementation
|
2023-03-10 20:40:21 +01:00 |
|
Eyck Jentzsch
|
62c118e501
|
fixes CSR to match latest fast interrupts spec
|
2023-01-20 16:21:04 +01:00 |
|
Eyck Jentzsch
|
1a0fc4bd5d
|
fixes wrong mcounteren in M-mode only priv wrapper
|
2022-10-10 08:59:27 +02:00 |
|
Eyck Jentzsch
|
40d1966e9a
|
fixes pending irq within irq hander behavior
|
2022-10-08 11:20:52 +02:00 |
|
Eyck Jentzsch
|
a977200284
|
cleans up priv wrappers
|
2022-10-05 08:58:57 +02:00 |
|
Eyck Jentzsch
|
6ba7c82f80
|
fixes wrapper definitions for hwl cores
|
2022-09-26 13:31:46 +02:00 |
|
Eyck Jentzsch
|
ad7bb28b4c
|
fixes write mask of clic memory mapped registers
|
2022-09-17 12:15:19 +02:00 |
|
Eyck Jentzsch
|
1ad66a71d8
|
extends supported break point types
|
2022-08-06 09:53:24 +02:00 |
|
Eyck Jentzsch
|
e60fa3d5e6
|
adaptes to changes in dbt-rise-core
|
2022-08-06 09:49:32 +02:00 |
|
Eyck Jentzsch
|
57347ae4d9
|
fixes cppcheck flagged issues
|
2022-07-23 13:49:10 +02:00 |
|
Eyck Jentzsch
|
4876f18ba9
|
adds windows compatibility fixes
|
2022-07-18 11:43:42 +02:00 |
|
Eyck Jentzsch
|
12ccfc055a
|
updates generate tgc_c definition
|
2022-07-11 22:58:10 +02:00 |
|
Eyck Jentzsch
|
feaa49d367
|
removes decoder again as there is some issue
|
2022-06-20 00:39:11 +02:00 |
|
Eyck Jentzsch
|
f096b15dbd
|
factors decoder into separate component
|
2022-06-19 13:17:31 +02:00 |
|
Eyck Jentzsch
|
076b5a39ad
|
fix class naming
|
2022-06-02 08:30:49 +02:00 |
|
Eyck Jentzsch
|
f40ab41899
|
fix left-over from layout refactoring
|
2022-06-02 08:30:02 +02:00 |
|
Eyck Jentzsch
|
0703a0a845
|
update tgc-mapper
|
2022-05-30 07:45:32 +02:00 |
|
Eyck Jentzsch
|
0c542d42aa
|
separate generated sources
|
2022-05-21 12:48:28 +02:00 |
|
Eyck Jentzsch
|
966d1616c5
|
change source code to unified layout
|
2022-05-21 11:55:24 +02:00 |
|
Eyck Jentzsch
|
9d9008a3a2
|
fix pointer mess
|
2022-04-26 15:35:17 +02:00 |
|
Eyck Jentzsch
|
a92b84bef4
|
add code word access for ISS plugins
|
2022-04-25 14:18:19 +02:00 |
|
Eyck Jentzsch
|
c42e336509
|
fix proper debug mode handling (#267 & #268)
|
2021-11-07 17:48:44 +01:00 |
|
Eyck Jentzsch
|
1616f0ac90
|
remove deprecated functions
|
2021-10-30 12:57:08 +02:00 |
|
Eyck Jentzsch
|
23b9741adf
|
refine and fix TGC_C iss to becoem compliant
|
2021-06-29 11:51:30 +02:00 |
|
Eyck Jentzsch
|
cf7b62a3f9
|
update names
|
2021-05-13 15:54:48 +02:00 |
|
Eyck Jentzsch
|
40db74ce02
|
remove tgf_b code generation
|
2021-03-07 16:26:14 +00:00 |
|
Eyck Jentzsch
|
dae8acb8a3
|
checkpoint before refactor
|
2021-03-06 07:17:42 +00:00 |
|
Eyck Jentzsch
|
9534d58d01
|
regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
|
2021-03-01 06:26:33 +00:00 |
|
Eyck Jentzsch
|
1668df0531
|
regenerated sources and and add opcode enum to headers
|
2021-02-23 08:29:31 +00:00 |
|
Eyck Jentzsch
|
337f1634c0
|
add mssing change
|
2021-02-15 18:01:46 +00:00 |
|
Eyck Jentzsch
|
34bb8e62ae
|
generate working ISS from CoreDSL 2.0
|
2021-02-06 14:47:06 +00:00 |
|
Eyck Jentzsch
|
c4da47cedd
|
integrate code generation into build process (first attempt)
|
2020-12-30 07:29:52 +00:00 |
|
Eyck Jentzsch
|
ab554539e3
|
first version of tgf_c based on CoreDSL 2.0
|
2020-12-29 08:48:22 +00:00 |
 Stanislaw Kaushanski
|
43488676dd
|
Update TGF naming convention
|
2020-09-11 10:45:44 +02:00 |
|
Stanislaw Kaushanski
|
9754e3953f
|
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
|
2020-08-24 15:01:54 +02:00 |
|
Stanislaw Kaushanski
|
8fce0c4759
|
Generate TGF01 and TGF02 cores
|
2020-08-20 17:29:36 +02:00 |
|
Eyck Jentzsch
|
10797a473d
|
modernize build system and cleanup dependencies
|
2020-05-30 14:16:10 +02:00 |
|
Eyck Jentzsch
|
116ed9bb5c
|
[WIP] started to add TinyCC backend
|
2020-01-09 19:43:17 +01:00 |
|
Eyck Jentzsch
|
7f06bba239
|
Fixed time csr handling
|
2019-06-28 20:58:02 +02:00 |
|
Eyck Jentzsch
|
67d9beb7bd
|
reorganized layout to only contain risc-v stuff
|
2019-06-11 16:49:37 +00:00 |