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57d5ea92be
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moves common functionality to base class
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2025-03-10 16:00:26 +01:00 |
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383d762abc
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applies clang-format and updates SystemC HTIF implementation
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2025-03-06 12:10:12 +01:00 |
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53de21eef9
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adds generator changed output
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2025-02-12 20:45:04 +01:00 |
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be0f783af8
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adds cycle increment to tcc
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2024-12-28 13:06:46 +01:00 |
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1089800682
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updates vm_impls and core.h to work with new vm_base
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2024-12-28 08:24:09 +01:00 |
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be6f5791fa
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adds update to cyclecount after each instr for asmjit
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2024-11-26 20:26:18 +01:00 |
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ad60449073
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updates generated cores
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2024-09-27 20:04:58 +02:00 |
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5f9d0beafb
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corrects softfloat to comply with RVD ACT
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2024-09-23 22:22:57 +02:00 |
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76ea0db25d
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adds newest generated vm_impl
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2024-08-17 23:19:51 +02:00 |
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de79adc50d
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updates debugger hook to stop before fetching instructions
this relates to https://github.com/Minres/DBT-RISE-RISCV/issues/8 :
Debugger loses control when trap vector fetch fails
and https://github.com/Minres/DBT-RISE-RISCV/issues/7 : Two debugger
single-steps are required at reset vector
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2024-08-17 12:39:54 +02:00 |
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a45fcd28db
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updates fn calling generation
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2024-08-17 08:22:04 +02:00 |
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0f15032210
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removes gen_wait as wait can be called like any other extern function
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2024-08-14 15:25:06 +02:00 |
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efc11d87a5
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updates template with fcsr check, adds extra braces on If Statements
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2024-08-14 14:32:58 +02:00 |
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4a19e27926
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adds changes due to generator being more inline with others
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2024-08-14 13:52:08 +02:00 |
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c15cdb0955
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expands return values of jit creating functions to inhibit endless trapping
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2024-08-14 11:49:59 +02:00 |
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b5341700aa
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updates template and adds braces when using conditions
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2024-08-13 08:55:14 +02:00 |
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fbca690b3b
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replaces gen_wait, updates template to include fp_functions when necessary
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2024-08-08 12:57:08 +02:00 |
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235a7e6e24
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updates template
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2024-08-08 11:08:28 +02:00 |
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62d21e1156
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updates disass
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2024-08-07 09:21:07 +02:00 |
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b3cc9d2346
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makes core_complex a template
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2024-08-04 18:47:32 +02:00 |
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933f08494c
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removes C++17 dependency from asmjit backend
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2024-08-04 17:41:49 +02:00 |
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21f8eab432
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adds regenerated tgc5c
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2024-08-02 19:18:28 +02:00 |
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f579ec6e48
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changes access to rounding mode to fail explicitly instead of unintended behavior
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2024-07-31 12:30:41 +02:00 |
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fd20e66f1f
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changes softfloat API usage, all effected Instrs pass test suite
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2024-07-31 12:30:41 +02:00 |
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7ffa7667b6
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fixes concerning FMADD_S, FMSUB_S, FNMADD_S, and FNSUB_S
mostly about ensuring correct sign
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2024-07-31 12:30:41 +02:00 |
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72b11beac5
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moves decoder to dbt-rise-core
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2024-07-25 10:13:38 +02:00 |
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c6b99cd155
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introduces new decoder to interp backend
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2024-07-24 12:28:35 +02:00 |
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b1306c3a47
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improves instruction decoding by avoiding copying, replaces .size()
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2024-07-24 08:54:37 +02:00 |
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0d6bf924ed
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changes jh.globals from map to vector
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2024-07-23 15:45:51 +02:00 |
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86de536c8f
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changes jh globals to seperate riscv specifics
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2024-07-23 14:35:31 +02:00 |
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051dd5e2d3
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updates templates for decoder in seperate class, adds again generated templates
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2024-07-23 13:46:10 +02:00 |
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e3942be776
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Introduces decoder in a seperate class
|
2024-07-23 13:08:53 +02:00 |
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6ee484a771
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moves instruction decoder into own class
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2024-07-23 11:30:33 +02:00 |
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60808c8649
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corrects template since util fns are no longer vm_base members
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2024-07-23 11:29:56 +02:00 |
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0432803d82
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updates templates and vm impls for better LAST_BRANCH handling
|
2024-07-22 09:04:17 +02:00 |
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d42d2ce533
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corrects illegal instruction for llvm
|
2024-07-18 14:04:23 +02:00 |
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236d12d7f5
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integrates gen_bool for Conditions (was truncation) into llvm
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2024-07-18 13:30:42 +02:00 |
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e1b6cab890
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removes setting of NEXT_PC to max when trapping in llvm and asmjit, adds default disass to llvm
|
2024-07-18 12:02:40 +02:00 |
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8361f88718
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removes setting of NEXT_PC to max if trap
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2024-07-18 11:37:53 +02:00 |
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2ec7ea4b41
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removes leftover gen_sync in asmjit
|
2024-07-17 22:39:12 +02:00 |
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b24965d321
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corrects gen_sync update order, improves illegal instruction
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2024-07-17 20:52:01 +02:00 |
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244bf6d2f2
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corrects gen_sync before trap check, improves illegal_instruction
|
2024-07-17 20:25:49 +02:00 |
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1a4465a371
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changes template: adds correct illegal instruction, reorders gen_sync to allow correct instr id eve when trapping, adds newly generated vm
|
2024-07-17 19:59:01 +02:00 |
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11a30caae8
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integrates generator changes to canPrecompute
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2024-07-17 15:14:13 +02:00 |
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ac1a26a10c
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integrates new tval changes into llvm
|
2024-07-17 14:17:02 +02:00 |
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7a199e122d
|
integrates new tval changes into asmjit
|
2024-07-17 09:42:12 +02:00 |
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d8c3d2e19c
|
integrates new tval changes into tcc
|
2024-07-16 17:35:23 +02:00 |
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375755999a
|
integrates new tval changes
|
2024-07-16 15:32:35 +02:00 |
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149b3136d2
|
updates generated files
|
2024-07-10 12:55:36 +02:00 |
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ac8f8b0539
|
updates vms with fixed Zc in tgc5c.core_desc
|
2024-07-10 12:51:59 +02:00 |
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