fixes linker script

sysctrl.h added
adapts to changed field layout in config registers of the camera module
2025-03-06 11:24:43 +01:00 · 2025-03-05 09:59:33 +01:00 · 2025-03-03 11:05:04 +01:00 · 2025-02-26 17:10:46 +01:00 · 2025-02-24 17:05:51 +01:00 · 2025-02-24 10:14:10 +01:00
55 changed files with 4606 additions and 770 deletions
--- a/.gitignore
+++ b/.gitignore
@@ -151,3 +151,4 @@ compile_commands.json
 CTestTestfile.cmake
 *.dump

+/doc/
--- a/env/common-gcc.mk
+++ b/env/common-gcc.mk
@@ -4,7 +4,7 @@ _MK_COMMON := # defined
 TL_TARGET?=all

 .PHONY: $(TL_TARGET)
-$(TL_TARGET): $(TARGET)
+$(TL_TARGET): $(TARGET).elf

 ENV_DIR:=$(dir $(lastword $(MAKEFILE_LIST)))
 BSP_BASE=$(ENV_DIR)/..
@@ -63,8 +63,7 @@ OBJDUMP := $(TOOL_DIR)$(TRIPLET)-objdump
 OBJCOPY := $(TOOL_DIR)$(TRIPLET)-objcopy

 ifndef NO_DEFAULT_LINK
-$(TARGET): $(LINK_OBJS) $(LINK_DEPS)
-	echo LINK_OBJS: $(LINK_OBJS)
+$(TARGET).elf: $(LINK_OBJS) $(LINK_DEPS)
 	$(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP_LDFLAGS) $(LIBWRAP) $(LD_SCRIPT) -o $@
 	$(OBJDUMP) -d -S $@ > $(TARGET).dis
 endif
@@ -80,6 +79,6 @@ $(CXX_OBJS): %.o: %.cpp $(HEADERS)

 .PHONY: clean
 clean:
-	rm -f $(CLEAN_OBJS) $(LIBWRAP)
+	rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf

 endif
--- a/env/ehrenberg/camera.lds
+++ b/env/ehrenberg/camera.lds
@@ -0,0 +1,167 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  rom (rxai!w) : ORIGIN = 0x80000000, LENGTH = 16k
+  ram (wxa!ri) : ORIGIN = 0x80004000, LENGTH = 112k
+}
+
+PHDRS
+{
+  rom PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+  .init ORIGIN(rom)        :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >rom AT>rom :rom
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >rom AT>rom :rom
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >rom AT>rom :rom
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >rom AT>rom :rom
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >rom AT>rom :rom
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >rom AT>rom :rom
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >rom AT>rom :rom
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >rom AT>rom :rom
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >rom AT>rom :rom
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >rom AT>rom :rom
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>rom :ram_init
+
+  .data          :
+  {
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+  } >ram AT>rom :ram_init
+
+  .srodata        :
+  {
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>rom :ram_init
+
+  .sdata          :
+  {
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>rom :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+}
--- a/env/ehrenberg/init.c
+++ b/env/ehrenberg/init.c
@@ -85,19 +85,26 @@ void __attribute__((weak)) handle_m_ext_interrupt(){
 void __attribute__((weak)) handle_m_time_interrupt(){
  uint64_t time = get_aclint_mtime(aclint);
  time+=MTIMER_NEXT_TICK_INC;
-  set_aclint_mtime(aclint, time);
+  set_aclint_mtimecmp(aclint, time);
 }

 void __attribute__((weak)) default_handler(void) {
  puts("default handler\n");
 }

+void __attribute__((weak)) interrupt_handler(unsigned) {
+  puts("interrupt handler\n");
+}
+
 uint32_t handle_trap(uint32_t mcause, uint32_t mepc, uint32_t sp){
-  if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
-    handle_m_ext_interrupt();
-    // External Machine-Level interrupt from PLIC
-  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
-    handle_m_time_interrupt();
+  if ((mcause & MCAUSE_INT)) {
+    if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
+      handle_m_ext_interrupt();
+    } else if (((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ 
+      handle_m_time_interrupt();
+    } else {
+      interrupt_handler(mcause& ~MCAUSE_INT);
+    }
  } else {
    write(1, "trap\n", 5);
    _exit(1 + mcause);
--- a/env/ehrenberg/link.lds
+++ b/env/ehrenberg/link.lds
@@ -4,10 +4,10 @@ ENTRY( _start )

 MEMORY
 {
-  rom   (rxai!w) : ORIGIN = 0xFFFFE000, LENGTH = 4k
-  flash (rxai!w) : ORIGIN = 0xE0000000, LENGTH = 4M
-  ram (wxa!ri) :   ORIGIN = 0x80000000, LENGTH = 32K
-  dram (wxa!ri) :  ORIGIN = 0x00000000, LENGTH = 256M
+  rom   (rxai!w) : ORIGIN = 0xFFFFE000, LENGTH = 2k
+  flash (rxai!w) : ORIGIN = 0xE0000000, LENGTH = 16M
+  ram   (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 128K
+  dram  (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 2048M
 }

 PHDRS
@@ -107,6 +107,11 @@ SECTIONS
    KEEP (*(.dtors))
  } >flash AT>flash :flash

+  .dummy          :
+  {
+	*(.comment.*)
+
+  }
  .lalign         :
  {
    . = ALIGN(4);
--- a/env/ehrenberg/platform.h
+++ b/env/ehrenberg/platform.h
@@ -4,34 +4,46 @@
 #define _ISS_PLATFORM_H

 #if __riscv_xlen == 32
-#define MCAUSE_INT         0x80000000UL
-#define MCAUSE_CAUSE       0x000003FFUL
+#define MCAUSE_INT 0x80000000UL
+#define MCAUSE_CAUSE 0x000003FFUL
 #else
-#define MCAUSE_INT         0x8000000000000000UL
-#define MCAUSE_CAUSE       0x00000000000003FFUL
+#define MCAUSE_INT 0x8000000000000000UL
+#define MCAUSE_CAUSE 0x00000000000003FFUL
 #endif

 #define APB_BUS

-#include "ehrenberg/devices/gpio.h"
-#include "ehrenberg/devices/uart.h"
-#include "ehrenberg/devices/timer.h"
 #include "ehrenberg/devices/aclint.h"
-#include "ehrenberg/devices/interrupt.h"
+#include "ehrenberg/devices/camera.h"
+#include "ehrenberg/devices/dma.h"
+#include "ehrenberg/devices/gen/sysctrl.h"
+#include "ehrenberg/devices/gpio.h"
+#include "ehrenberg/devices/i2s.h"
+#include "ehrenberg/devices/msg_if.h"
 #include "ehrenberg/devices/qspi.h"
+#include "ehrenberg/devices/timer.h"
+#include "ehrenberg/devices/uart.h"

-#define PERIPH(TYPE, ADDR) ((volatile TYPE*) (ADDR))
+#define PERIPH(TYPE, ADDR) ((volatile TYPE *)(ADDR))

 #define APB_BASE 0xF0000000

-#define gpio        PERIPH(gpio_t,      APB_BASE+0x0000)
-#define uart        PERIPH(uart_t,      APB_BASE+0x1000)
-#define timer       PERIPH(timer_t,     APB_BASE+0x20000)
-#define aclint      PERIPH(aclint_t,    APB_BASE+0x30000)
-#define irq         PERIPH(irq_t,       APB_BASE+0x40000)
-#define qspi        PERIPH(qspi_t,      APB_BASE+0x50000)
+#define gpio PERIPH(gpio_t, APB_BASE + 0x0000)
+#define uart PERIPH(uart_t, APB_BASE + 0x01000)
+#define timer PERIPH(timercounter_t, APB_BASE + 0x20000)
+#define aclint PERIPH(aclint_t, APB_BASE + 0x30000)
+#define sysctrl PERIPH(sysctrl_t, APB_BASE + 0x40000)
+#define qspi PERIPH(qspi_t, APB_BASE + 0x50000)
+#define i2s PERIPH(i2s_t, APB_BASE + 0x90000)
+#define camera PERIPH(camera_t, APB_BASE + 0xA0000)
+#define dma PERIPH(dma_t, APB_BASE + 0xB0000)
+#define msgif PERIPH(mkcontrolclusterstreamcontroller_t, APB_BASE + 0xC0000)
+
+#include "ehrenberg/devices/flexki_messages.h"
+#include "ehrenberg/devices/fki_cluster_info.h"

 #define XIP_START_LOC 0xE0040000
+#define RAM_START_LOC 0x80000000

 // Misc

--- a/env/ehrenberg/ram.lds
+++ b/env/ehrenberg/ram.lds
@@ -0,0 +1,167 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  rom (rxai!w) : ORIGIN = 0xC0000000, LENGTH = 64k
+  ram (wxa!ri) : ORIGIN = 0xC0010000, LENGTH = 64k
+}
+
+PHDRS
+{
+  rom PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+  .init ORIGIN(rom)        :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >rom AT>rom :rom
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >rom AT>rom :rom
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >rom AT>rom :rom
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >rom AT>rom :rom
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >rom AT>rom :rom
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >rom AT>rom :rom
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >rom AT>rom :rom
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >rom AT>rom :rom
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >rom AT>rom :rom
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >rom AT>rom :rom
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>rom :ram_init
+
+  .data          :
+  {
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+  } >ram AT>rom :ram_init
+
+  .srodata        :
+  {
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>rom :ram_init
+
+  .sdata          :
+  {
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>rom :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+}
--- a/env/ehrenberg/rom.lds
+++ b/env/ehrenberg/rom.lds
@@ -0,0 +1,170 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 4k
+  ram (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 32k
+}
+
+PHDRS
+{
+  rom PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+  .init ORIGIN(rom)        :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >rom AT>rom :rom
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >rom AT>rom :rom
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >rom AT>rom :rom
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >rom AT>rom :rom
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >rom AT>rom :rom
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >rom AT>rom :rom
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >rom AT>rom :rom
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >rom AT>rom :rom
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >rom AT>rom :rom
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >rom AT>rom :rom
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>rom :ram_init
+
+  .data          :
+  {
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+  } >ram AT>rom :ram_init
+
+  .srodata        :
+  {
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>rom :ram_init
+
+  .sdata          :
+  {
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>rom :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+
+  PROVIDE( tohost = 0xfffffff0 );
+  PROVIDE( fromhost = 0xfffffff8 );
+}
--- a/env/entry.S
+++ b/env/entry.S
@@ -10,66 +10,80 @@
  .align 2
  .global trap_entry
 trap_entry:
+  addi sp, sp, -32*REGBYTES
+
+  sw  x1,  1*REGBYTES(sp)
+  sw  x2,  2*REGBYTES(sp)
+  sw  x3,  3*REGBYTES(sp)
+  sw  x4,  4*REGBYTES(sp)
+  sw  x5,  5*REGBYTES(sp)
+  sw  x6,  6*REGBYTES(sp)
+  sw  x7,  7*REGBYTES(sp)
+  sw  x8,  8*REGBYTES(sp)
+  sw  x9,  9*REGBYTES(sp)
+  sw x10, 10*REGBYTES(sp)
+  sw x11, 11*REGBYTES(sp)
+  sw x12, 12*REGBYTES(sp)
+  sw x13, 13*REGBYTES(sp)
+  sw x14, 14*REGBYTES(sp)
+  sw x15, 15*REGBYTES(sp)
 #ifndef __riscv_abi_rve
-  addi sp, sp, -8*REGBYTES
-  STORE x1, 1*REGBYTES(sp) // ra
-  STORE x5, 2*REGBYTES(sp) // t0
-  STORE x10, 3*REGBYTES(sp) // a0
-  STORE x11, 4*REGBYTES(sp) // a1
-  STORE x12, 5*REGBYTES(sp) // a2
-  STORE x13, 6*REGBYTES(sp) // a3
-  STORE x15, 7*REGBYTES(sp) // t1
-#else
-  addi sp, sp, -16*REGBYTES
-  STORE x1, 1*REGBYTES(sp) // ra
-  STORE x5, 2*REGBYTES(sp) // t0
-  STORE x6, 3*REGBYTES(sp) // t1
-  STORE x7, 4*REGBYTES(sp) // t2
-  STORE x10, 5*REGBYTES(sp) // a0
-  STORE x11, 6*REGBYTES(sp) // a1
-  STORE x12, 7*REGBYTES(sp) // a2
-  STORE x13, 8*REGBYTES(sp) // a3
-  STORE x14, 9*REGBYTES(sp) // a4
-  STORE x15, 10*REGBYTES(sp) // a5
-  STORE x16, 11*REGBYTES(sp) // a6
-  STORE x17, 12*REGBYTES(sp) // a7
-  STORE x28, 13*REGBYTES(sp) // t3
-  STORE x29, 14*REGBYTES(sp) // t4
-  STORE x30, 15*REGBYTES(sp) // t5
-  STORE x31, 16*REGBYTES(sp) // t6
+  sw x16, 16*REGBYTES(sp)
+  sw x17, 17*REGBYTES(sp)
+  sw x18, 18*REGBYTES(sp)
+  sw x19, 19*REGBYTES(sp)
+  sw x20, 20*REGBYTES(sp)
+  sw x21, 21*REGBYTES(sp)
+  sw x22, 22*REGBYTES(sp)
+  sw x23, 23*REGBYTES(sp)
+  sw x24, 24*REGBYTES(sp)
+  sw x25, 25*REGBYTES(sp)
+  sw x26, 26*REGBYTES(sp)
+  sw x27, 27*REGBYTES(sp)
+  sw x28, 28*REGBYTES(sp)
+  sw x29, 29*REGBYTES(sp)
+  sw x30, 30*REGBYTES(sp)
+  sw x31, 31*REGBYTES(sp)
 #endif
  csrr a0, mcause
  csrr a1, mepc
  mv a2, sp
  call handle_trap
  csrw mepc, a0
+
+
+  lw  x1,  1*REGBYTES(sp)
+  lw  x2,  2*REGBYTES(sp)
+  lw  x3,  3*REGBYTES(sp)
+  lw  x4,  4*REGBYTES(sp)
+  lw  x5,  5*REGBYTES(sp)
+  lw  x6,  6*REGBYTES(sp)
+  lw  x7,  7*REGBYTES(sp)
+  lw  x8,  8*REGBYTES(sp)
+  lw  x9,  9*REGBYTES(sp)
+  lw x10, 10*REGBYTES(sp)
+  lw x11, 11*REGBYTES(sp)
+  lw x12, 12*REGBYTES(sp)
+  lw x13, 13*REGBYTES(sp)
+  lw x14, 14*REGBYTES(sp)
+  lw x15, 15*REGBYTES(sp)
 #ifndef __riscv_abi_rve
-  addi sp, sp, -8*REGBYTES
-  LOAD x1, 1*REGBYTES(sp) // ra
-  LOAD x5, 2*REGBYTES(sp) // t0
-  LOAD x10, 3*REGBYTES(sp) // a0
-  LOAD x11, 4*REGBYTES(sp) // a1
-  LOAD x12, 5*REGBYTES(sp) // a2
-  LOAD x13, 6*REGBYTES(sp) // a3
-  LOAD x15, 7*REGBYTES(sp) // t1
-#else
-  addi sp, sp, -16*REGBYTES
-  LOAD x1, 1*REGBYTES(sp) // ra
-  LOAD x5, 2*REGBYTES(sp) // t0
-  LOAD x6, 3*REGBYTES(sp) // t1
-  LOAD x7, 4*REGBYTES(sp) // t2
-  LOAD x10, 5*REGBYTES(sp) // a0
-  LOAD x11, 6*REGBYTES(sp) // a1
-  LOAD x12, 7*REGBYTES(sp) // a2
-  LOAD x13, 8*REGBYTES(sp) // a3
-  LOAD x14, 9*REGBYTES(sp) // a4
-  LOAD x15, 10*REGBYTES(sp) // a5
-  LOAD x16, 11*REGBYTES(sp) // a6
-  LOAD x17, 12*REGBYTES(sp) // a7
-  LOAD x28, 13*REGBYTES(sp) // t3
-  LOAD x29, 14*REGBYTES(sp) // t4
-  LOAD x30, 15*REGBYTES(sp) // t5
-  LOAD x31, 16*REGBYTES(sp) // t6
+  lw x16, 16*REGBYTES(sp)
+  lw x17, 17*REGBYTES(sp)
+  lw x18, 18*REGBYTES(sp)
+  lw x19, 19*REGBYTES(sp)
+  lw x20, 20*REGBYTES(sp)
+  lw x21, 21*REGBYTES(sp)
+  lw x22, 22*REGBYTES(sp)
+  lw x23, 23*REGBYTES(sp)
+  lw x24, 24*REGBYTES(sp)
+  lw x25, 25*REGBYTES(sp)
+  lw x26, 26*REGBYTES(sp)
+  lw x27, 27*REGBYTES(sp)
+  lw x28, 28*REGBYTES(sp)
+  lw x29, 29*REGBYTES(sp)
+  lw x30, 30*REGBYTES(sp)
+  lw x31, 31*REGBYTES(sp)
 #endif
  mret

--- a/env/start.S
+++ b/env/start.S
@@ -7,12 +7,17 @@
 _start:
 .option push
 .option norelax
-    la gp, trap_entry
-    csrw mtvec, gp
+.option norvc
+	j 1f
+	.2byte	0x4e4d
+	.2byte	0x5352
+	.4byte  0x669
+1:
    la gp, __global_pointer$
 .option pop
 	la sp, _sp
-
+    la t0, trap_entry
+    csrw mtvec, t0
 	/* Load data section */
 	la a0, _data_lma
 	la a1, _data
@@ -37,11 +42,11 @@ _start:
 2:

 	/* Call global constructors */
-//#ifdef HAVE_INIT_FINI
+#ifndef HAVE_NO_INIT_FINI
 	la a0, __libc_fini_array
 	call atexit
 	call __libc_init_array
-//#endif
+#endif
 #ifndef __riscv_float_abi_soft
 	/* Enable FPU */
 	li t0, MSTATUS_FS
--- a/env/tgc_vp
+++ b/env/tgc_vp
@@ -1 +1 @@
-ehrenberg/
+ehrenberg
--- a/include/ehrenberg/devices/aclint.h
+++ b/include/ehrenberg/devices/aclint.h
@@ -1,10 +1,9 @@
-#ifndef _BSP_ACLINT_H
-#define _BSP_ACLINT_H
+#ifndef _DEVICES_ACLINT_H
+#define _DEVICES_ACLINT_H

 #include <stdint.h>
-#include "gen/Apb3AClint.h"
+#include "gen/aclint.h"

-#define aclint_t apb3aclint_t

 static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value){
    set_aclint_mtime_hi(reg, (uint32_t)(value >> 32));
@@ -26,4 +25,4 @@ static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg){
    return value;
 }

-#endif /* _BSP_ACLINT_H */
+#endif /* _DEVICES_ACLINT_H */
--- a/include/ehrenberg/devices/camera.h
+++ b/include/ehrenberg/devices/camera.h
@@ -0,0 +1,6 @@
+#ifndef _DEVICES_CAM_H
+#define _DEVICES_CAM_H
+
+#include "gen/camera.h"
+
+#endif /* _DEVICES_CAM_H */
--- a/include/ehrenberg/devices/dma.h
+++ b/include/ehrenberg/devices/dma.h
@@ -0,0 +1,11 @@
+#ifndef _DEVICES_DMA_H
+#define _DEVICES_DMA_H
+
+#include "gen/dma.h"
+
+#define EVENT_UART 1
+#define I2S_LEFT_SAMPLE_AVAIL 2
+#define I2S_RIGHT_SAMPLE_AVAIL 4
+#define CAMERA_PIXEL_AVAIL 8
+
+#endif /* _BSP_DMA_H */
--- a/include/ehrenberg/devices/fki_cluster_info.h
+++ b/include/ehrenberg/devices/fki_cluster_info.h
@@ -0,0 +1,316 @@
+#pragma once
+#ifndef _FKI_CLUSTER_INFO_H
+#define _FKI_CLUSTER_INFO_H
+
+
+static uint8_t fki_ccc(uint8_t cluster);
+static uint8_t fki_dma(uint8_t cluster);
+static uint8_t fki_axi2stream(uint8_t cluster);
+static uint8_t fki_stream2axi(uint8_t cluster);
+static uint8_t fki_dma_adapter(uint8_t cluster);
+static uint64_t fki_addr_ccc_peMapping(uint8_t cluster);
+static uint64_t fki_addr_sram1(uint8_t cluster);
+static uint64_t fki_addr_ccc_configMem(uint8_t cluster);
+static uint64_t fki_addr_sram2(uint8_t cluster);
+static uint64_t fki_addr_cntrl_cva5(uint8_t cluster);
+static uint64_t fki_addr_cntrl_tgc(uint8_t cluster);
+static uint64_t fki_addr_ccc_idxTasks(uint8_t cluster);
+static uint64_t fki_addr_ccc_idxJobs(uint8_t cluster);
+static uint64_t fki_addr_aes_adapter(uint8_t cluster);
+static uint64_t fki_addr_ut_adapter(uint8_t cluster);
+static uint64_t fki_addr_sram0(uint8_t cluster);
+static uint64_t fki_addr_sram3(uint8_t cluster);
+static uint64_t fki_addr_hide_adapter(uint8_t cluster);
+
+#define Compute0 2
+#define Compute0_ccc 2,0
+#define Compute0_stream2axi 2,1
+#define Compute0_axi2stream 2,2
+#define Compute0_dma 2,4
+#define Compute0_dma_adapter 2,5
+#define ADDR_Compute0_ccc_idxJobs 0x80004000
+#define ADDR_Compute0_ccc_idxTasks 0x80005000
+#define ADDR_Compute0_ccc_configMem 0x80000000
+#define ADDR_Compute0_ccc_peMapping 0x80006000
+#define ADDR_Compute0_aes_adapter 0x80007000
+#define ADDR_Compute0_hide_adapter 0x80008000
+#define ADDR_Compute0_cntrl_cva5 0x80009000
+#define ADDR_Compute0_cntrl_tgc 0x8000a000
+#define ADDR_Compute0_ut_adapter 0x8000b000
+#define ADDR_Compute0_sram0 0x8000c000
+#define ADDR_Compute0_sram1 0x8010c000
+#define ADDR_Compute0_sram2 0x8018c000
+#define ADDR_Compute0_sram3 0x8020c000
+#define Compute1 3
+#define Compute1_ccc 3,0
+#define Compute1_stream2axi 3,1
+#define Compute1_axi2stream 3,2
+#define Compute1_dma 3,4
+#define Compute1_dma_adapter 3,5
+#define ADDR_Compute1_ccc_idxJobs 0x90004000
+#define ADDR_Compute1_ccc_idxTasks 0x90005000
+#define ADDR_Compute1_ccc_configMem 0x90000000
+#define ADDR_Compute1_ccc_peMapping 0x90006000
+#define ADDR_Compute1_aes_adapter 0x90007000
+#define ADDR_Compute1_hide_adapter 0x90008000
+#define ADDR_Compute1_cntrl_cva5 0x90009000
+#define ADDR_Compute1_cntrl_tgc 0x9000a000
+#define ADDR_Compute1_ut_adapter 0x9000b000
+#define ADDR_Compute1_sram0 0x9000c000
+#define ADDR_Compute1_sram1 0x9010c000
+#define ADDR_Compute1_sram2 0x9018c000
+#define ADDR_Compute1_sram3 0x9020c000
+
+static uint8_t fki_ccc(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0;
+		}
+		case 3: {
+			return 0;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_dma(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 4;
+		}
+		case 2: {
+			return 4;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_axi2stream(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 2;
+		}
+		case 2: {
+			return 2;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_stream2axi(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 1;
+		}
+		case 2: {
+			return 1;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_dma_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 5;
+		}
+		case 3: {
+			return 5;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_ccc_peMapping(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80006000;
+		}
+		case 3: {
+			return 0x90006000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_sram1(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x9010c000;
+		}
+		case 2: {
+			return 0x8010c000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_ccc_configMem(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x90000000;
+		}
+		case 2: {
+			return 0x80000000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_sram2(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x8018c000;
+		}
+		case 3: {
+			return 0x9018c000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_cntrl_cva5(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80009000;
+		}
+		case 3: {
+			return 0x90009000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_cntrl_tgc(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x8000a000;
+		}
+		case 3: {
+			return 0x9000a000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_ccc_idxTasks(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80005000;
+		}
+		case 3: {
+			return 0x90005000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_ccc_idxJobs(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80004000;
+		}
+		case 3: {
+			return 0x90004000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_aes_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80007000;
+		}
+		case 3: {
+			return 0x90007000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_ut_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x9000b000;
+		}
+		case 2: {
+			return 0x8000b000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_sram0(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x8000c000;
+		}
+		case 3: {
+			return 0x9000c000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_sram3(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x8020c000;
+		}
+		case 3: {
+			return 0x9020c000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_hide_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80008000;
+		}
+		case 3: {
+			return 0x90008000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+#endif //_FKI_CLUSTER_INFO_H
--- a/include/ehrenberg/devices/flexki_messages.h
+++ b/include/ehrenberg/devices/flexki_messages.h
@@ -0,0 +1,77 @@
+#ifndef _FLEXKI_MESSAGES_H
+#define _FLEXKI_MESSAGES_H
+
+#include "fki_cluster_info.h"
+
+#include <stdbool.h>
+
+static void send_msg(uint32_t cluster, uint32_t component, uint32_t msg_len, uint32_t msg_id, uint32_t* words) {
+    set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(msgif, component);
+	set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(msgif, cluster);
+	set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(msgif, msg_len);
+	set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(msgif, msg_id);
+    for (uint32_t i = 0; i < msg_len; i = i + 1) {
+        switch (i) {
+            case 0:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(msgif, words[i]);
+                break;
+            case 1:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(msgif, words[i]);
+                break;
+            case 2:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(msgif, words[i]);
+                break;
+            case 3:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(msgif, words[i]);
+                break;
+            case 4:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(msgif, words[i]);
+                break;
+            case 5:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(msgif, words[i]);
+                break;
+            case 6:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(msgif, words[i]);
+                break;
+            case 7:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(msgif, words[i]);
+                break;
+            default:
+                break;
+        }
+    }
+    set_mkcontrolclusterstreamcontroller_REG_SEND(msgif, 1);
+}
+
+static uint32_t check_response(void) {
+    while (true) {
+        if (get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(msgif) != 0) {
+            return get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(msgif);
+        }
+    }
+}
+
+static uint32_t wait_response(uint32_t msg_id) {
+    while (true) {
+        if (get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(msgif) != 0) {
+            if (get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(msgif) == msg_id) {
+                break;
+            }
+        }
+    }
+	uint32_t response_payload = get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(msgif);
+	set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(msgif, 1);
+	return response_payload;
+}
+
+static void fki_dma_transfer(uint32_t cluster, uint32_t msg_id, uint32_t srcAddr, uint32_t destAddr, uint32_t bytes) {
+    uint32_t values[] = {
+        0,
+        srcAddr,
+        destAddr,
+        bytes
+    };
+    send_msg(cluster, fki_dma(cluster), 4, msg_id, values);
+}
+
+#endif /* _FLEXKI_MESSAGES_H */
--- a/include/ehrenberg/devices/gen/Apb3AClint.h
+++ b/include/ehrenberg/devices/gen/Apb3AClint.h
@@ -1,53 +0,0 @@
-/*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Generated at 2024-02-19 14:24:37 UTC 
-* by peakrdl_mnrs version 1.2.2
-*/
-
-#ifndef _BSP_APB3ACLINT_H
-#define _BSP_APB3ACLINT_H
-
-#include <stdint.h>
-
-typedef struct __attribute((__packed__)) {
-    volatile uint32_t MSIP0;
-    volatile uint32_t MTIMECMP0LO;
-    volatile uint32_t MTIMECMP0HI;
-    volatile uint32_t MTIME_LO;
-    volatile uint32_t MTIME_HI;
-}apb3aclint_t;
-
-inline uint32_t get_aclint_msip0(volatile apb3aclint_t *reg){
-    return (reg->MSIP0 >> 0) & 0x1;
-}
-inline void set_aclint_msip0(volatile apb3aclint_t *reg, uint8_t value){
-    reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
-}
-inline uint32_t get_aclint_mtimecmp0lo(volatile apb3aclint_t *reg){
-    return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
-}
-inline void set_aclint_mtimecmp0lo(volatile apb3aclint_t *reg, uint32_t value){
-    reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
-}
-inline uint32_t get_aclint_mtimecmp0hi(volatile apb3aclint_t *reg){
-    return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
-}
-inline void set_aclint_mtimecmp0hi(volatile apb3aclint_t *reg, uint32_t value){
-    reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
-}
-inline uint32_t get_aclint_mtime_lo(volatile apb3aclint_t *reg){
-    return (reg->MTIME_LO >> 0) & 0xffffffff;
-}
-inline void set_aclint_mtime_lo(volatile apb3aclint_t *reg, uint32_t value){
-    reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
-}
-inline uint32_t get_aclint_mtime_hi(volatile apb3aclint_t *reg){
-    return (reg->MTIME_HI >> 0) & 0xffffffff;
-}
-inline void set_aclint_mtime_hi(volatile apb3aclint_t *reg, uint32_t value){
-    reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
-}
-#endif /* _BSP_APB3ACLINT_H */
--- a/include/ehrenberg/devices/gen/Apb3Gpio.h
+++ b/include/ehrenberg/devices/gen/Apb3Gpio.h
@@ -1,36 +0,0 @@
-/*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Generated at 2024-02-19 14:24:37 UTC 
-* by peakrdl_mnrs version 1.2.2
-*/
-
-#ifndef _BSP_APB3GPIO_H
-#define _BSP_APB3GPIO_H
-
-#include <stdint.h>
-
-typedef struct __attribute((__packed__)) {
-    volatile uint32_t VALUE;
-    volatile uint32_t WRITE;
-    volatile uint32_t WRITEENABLE;
-}apb3gpio_t;
-
-inline uint32_t get_gpio_value(volatile apb3gpio_t *reg){
-    return (reg->VALUE >> 0) & 0xffffffff;
-}
-inline uint32_t get_gpio_write(volatile apb3gpio_t *reg){
-    return (reg->WRITE >> 0) & 0xffffffff;
-}
-inline void set_gpio_write(volatile apb3gpio_t *reg, uint32_t value){
-    reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
-}
-inline uint32_t get_gpio_writeEnable(volatile apb3gpio_t *reg){
-    return (reg->WRITEENABLE >> 0) & 0xffffffff;
-}
-inline void set_gpio_writeEnable(volatile apb3gpio_t *reg, uint32_t value){
-    reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
-}
-#endif /* _BSP_APB3GPIO_H */
--- a/include/ehrenberg/devices/gen/Apb3IrqCtrl.h
+++ b/include/ehrenberg/devices/gen/Apb3IrqCtrl.h
@@ -1,32 +0,0 @@
-/*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Generated at 2024-02-19 14:24:37 UTC 
-* by peakrdl_mnrs version 1.2.2
-*/
-
-#ifndef _BSP_APB3IRQCTRL_H
-#define _BSP_APB3IRQCTRL_H
-
-#include <stdint.h>
-
-typedef struct __attribute((__packed__)) {
-    volatile uint32_t PENDINGSREG;
-    volatile uint32_t MASKSREG;
-}apb3irqctrl_t;
-
-inline uint32_t get_irq_pendingsReg(volatile apb3irqctrl_t *reg){
-    return (reg->PENDINGSREG >> 0) & 0xf;
-}
-inline void set_irq_pendingsReg(volatile apb3irqctrl_t *reg, uint8_t value){
-    reg->PENDINGSREG = (reg->PENDINGSREG & ~(0xfU << 0)) | (value << 0);
-}
-inline uint32_t get_irq_masksReg(volatile apb3irqctrl_t *reg){
-    return (reg->MASKSREG >> 0) & 0xf;
-}
-inline void set_irq_masksReg(volatile apb3irqctrl_t *reg, uint8_t value){
-    reg->MASKSREG = (reg->MASKSREG & ~(0xfU << 0)) | (value << 0);
-}
-#endif /* _BSP_APB3IRQCTRL_H */
--- a/include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h
+++ b/include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h
@@ -1,214 +0,0 @@
-/*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Generated at 2024-02-19 14:24:37 UTC 
-* by peakrdl_mnrs version 1.2.2
-*/
-
-#ifndef _BSP_APB3SPIXDRMASTERCTRL_H
-#define _BSP_APB3SPIXDRMASTERCTRL_H
-
-#include <stdint.h>
-
-typedef struct __attribute((__packed__)) {
-    volatile uint32_t DATA;
-    volatile uint32_t STATUS;
-    volatile uint32_t CONFIG;
-    volatile uint32_t INTR;
-    uint32_t fill0[4];
-    volatile uint32_t SCLK_CONFIG;
-    volatile uint32_t SSGEN_SETUP;
-    volatile uint32_t SSGEN_HOLD;
-    volatile uint32_t SSGEN_DISABLE;
-    volatile uint32_t SSGEN_ACTIVE_HIGH;
-    uint32_t fill1[3];
-    volatile uint32_t XIP_ENABLE;
-    volatile uint32_t XIP_CONFIG;
-    volatile uint32_t XIP_MODE;
-    uint32_t fill2[1];
-    volatile uint32_t XIP_WRITE;
-    volatile uint32_t XIP_READ_WRITE;
-    volatile uint32_t XIP_READ;
-}apb3spixdrmasterctrl_t;
-
-#define SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
-#define SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
-#define SPI_XIP_CONFIG_INSTRUCTION(V) ((V & SPI_XIP_CONFIG_INSTRUCTION_MASK) << SPI_XIP_CONFIG_INSTRUCTION_OFFS)
-
-#define SPI_XIP_CONFIG_ENABLE_OFFS 8
-#define SPI_XIP_CONFIG_ENABLE_MASK 1
-#define SPI_XIP_CONFIG_ENABLE(V) ((V & SPI_XIP_CONFIG_ENABLE_MASK) << SPI_XIP_CONFIG_ENABLE_OFFS)
-
-#define SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
-#define SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
-#define SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
-
-#define SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
-#define SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
-#define SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
-
-inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_data_write(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->DATA >> 8) & 0x1;
-}
-inline void set_spi_data_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
-}
-inline uint32_t get_spi_data_read(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->DATA >> 9) & 0x1;
-}
-inline void set_spi_data_read(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
-}
-inline uint32_t get_spi_data_kind(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->DATA >> 11) & 0x1;
-}
-inline void set_spi_data_kind(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
-}
-inline uint32_t get_spi_data_rx_data_invalid(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->DATA >> 31) & 0x1;
-}
-inline uint32_t get_spi_status_tx_free(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->STATUS >> 0) & 0x3f;
-}
-inline uint32_t get_spi_status_rx_avail(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->STATUS >> 16) & 0x3f;
-}
-inline uint32_t get_spi_config_kind(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->CONFIG >> 0) & 0x3;
-}
-inline void set_spi_config_kind(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
-}
-inline uint32_t get_spi_config_mode(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->CONFIG >> 4) & 0x7;
-}
-inline void set_spi_config_mode(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x7U << 4)) | (value << 4);
-}
-inline uint32_t get_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->INTR >> 0) & 0x1;
-}
-inline void set_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
-}
-inline uint32_t get_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->INTR >> 1) & 0x1;
-}
-inline void set_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
-}
-inline uint32_t get_spi_intr_tx_ip(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->INTR >> 8) & 0x1;
-}
-inline uint32_t get_spi_intr_rx_ip(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->INTR >> 9) & 0x1;
-}
-inline uint32_t get_spi_intr_tx_active(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->INTR >> 16) & 0x1;
-}
-inline uint32_t get_spi_sclk_config(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->SCLK_CONFIG >> 0) & 0xfff;
-}
-inline void set_spi_sclk_config(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
-    reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->SSGEN_SETUP >> 0) & 0xfff;
-}
-inline void set_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
-    reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->SSGEN_HOLD >> 0) & 0xfff;
-}
-inline void set_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
-    reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->SSGEN_DISABLE >> 0) & 0xfff;
-}
-inline void set_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
-    reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
-}
-inline void set_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
-}
-inline uint32_t get_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_ENABLE >> 0) & 0x1;
-}
-inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
-}
-inline uint32_t get_spi_xip_config(volatile apb3spixdrmasterctrl_t *reg){
-    return reg->XIP_CONFIG;
-}
-inline void set_spi_xip_config(volatile apb3spixdrmasterctrl_t *reg, uint32_t value){
-    reg->XIP_CONFIG = value;
-}
-inline uint32_t get_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_CONFIG >> 0) & 0xff;
-}
-inline void set_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_CONFIG >> 8) & 0x1;
-}
-inline void set_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
-}
-inline uint32_t get_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_CONFIG >> 16) & 0xff;
-}
-inline void set_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
-}
-inline uint32_t get_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_CONFIG >> 24) & 0xf;
-}
-inline void set_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
-}
-inline uint32_t get_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_MODE >> 0) & 0x7;
-}
-inline void set_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 0)) | (value << 0);
-}
-inline uint32_t get_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_MODE >> 8) & 0x7;
-}
-inline void set_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 8)) | (value << 8);
-}
-inline uint32_t get_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_MODE >> 16) & 0x7;
-}
-inline void set_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 16)) | (value << 16);
-}
-inline uint32_t get_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_MODE >> 24) & 0x7;
-}
-inline void set_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 24)) | (value << 24);
-}
-inline void set_spi_xip_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
-}
-inline void set_spi_xip_read_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
-    reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
-}
-inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t *reg){
-    return (reg->XIP_READ >> 0) & 0xff;
-}
-#endif /* _BSP_APB3SPIXDRMASTERCTRL_H */
--- a/include/ehrenberg/devices/gen/Apb3Timer.h
+++ b/include/ehrenberg/devices/gen/Apb3Timer.h
@@ -1,73 +0,0 @@
-/*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Generated at 2024-02-19 14:24:37 UTC 
-* by peakrdl_mnrs version 1.2.2
-*/
-
-#ifndef _BSP_APB3TIMER_H
-#define _BSP_APB3TIMER_H
-
-#include <stdint.h>
-
-typedef struct __attribute((__packed__)) {
-    volatile uint32_t PRESCALER;
-    volatile uint32_t T0_CTRL;
-    volatile uint32_t T0_OVERFLOW;
-    volatile uint32_t T0_VALUE;
-    volatile uint32_t T1_CTRL;
-    volatile uint32_t T1_OVERFLOW;
-    volatile uint32_t T1_VALUE;
-}apb3timer_t;
-
-inline uint32_t get_timer_prescaler(volatile apb3timer_t *reg){
-    return (reg->PRESCALER >> 0) & 0xffff;
-}
-inline void set_timer_prescaler(volatile apb3timer_t *reg, uint16_t value){
-    reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
-}
-inline uint32_t get_timer_t0_ctrl_enable(volatile apb3timer_t *reg){
-    return (reg->T0_CTRL >> 0) & 0x7;
-}
-inline void set_timer_t0_ctrl_enable(volatile apb3timer_t *reg, uint8_t value){
-    reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
-}
-inline uint32_t get_timer_t0_ctrl_clear(volatile apb3timer_t *reg){
-    return (reg->T0_CTRL >> 3) & 0x3;
-}
-inline void set_timer_t0_ctrl_clear(volatile apb3timer_t *reg, uint8_t value){
-    reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
-}
-inline uint32_t get_timer_t0_overflow(volatile apb3timer_t *reg){
-    return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
-}
-inline void set_timer_t0_overflow(volatile apb3timer_t *reg, uint32_t value){
-    reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
-}
-inline uint32_t get_timer_t0_value(volatile apb3timer_t *reg){
-    return (reg->T0_VALUE >> 0) & 0xffffffff;
-}
-inline uint32_t get_timer_t1_ctrl_enable(volatile apb3timer_t *reg){
-    return (reg->T1_CTRL >> 0) & 0x7;
-}
-inline void set_timer_t1_ctrl_enable(volatile apb3timer_t *reg, uint8_t value){
-    reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
-}
-inline uint32_t get_timer_t1_ctrl_clear(volatile apb3timer_t *reg){
-    return (reg->T1_CTRL >> 3) & 0x3;
-}
-inline void set_timer_t1_ctrl_clear(volatile apb3timer_t *reg, uint8_t value){
-    reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
-}
-inline uint32_t get_timer_t1_overflow(volatile apb3timer_t *reg){
-    return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
-}
-inline void set_timer_t1_overflow(volatile apb3timer_t *reg, uint32_t value){
-    reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
-}
-inline uint32_t get_timer_t1_value(volatile apb3timer_t *reg){
-    return (reg->T1_VALUE >> 0) & 0xffffffff;
-}
-#endif /* _BSP_APB3TIMER_H */
--- a/include/ehrenberg/devices/gen/Apb3Uart.h
+++ b/include/ehrenberg/devices/gen/Apb3Uart.h
@@ -1,104 +0,0 @@
-/*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Generated at 2024-02-19 14:24:37 UTC 
-* by peakrdl_mnrs version 1.2.2
-*/
-
-#ifndef _BSP_APB3UART_H
-#define _BSP_APB3UART_H
-
-#include <stdint.h>
-
-typedef struct __attribute((__packed__)) {
-    volatile uint32_t RX_TX_REG;
-    volatile uint32_t INT_CTRL_REG;
-    volatile uint32_t CLK_DIVIDER_REG;
-    volatile uint32_t FRAME_CONFIG_REG;
-    volatile uint32_t STATUS_REG;
-}apb3uart_t;
-
-inline uint32_t get_uart_rx_tx_reg_data(volatile apb3uart_t *reg){
-    return (reg->RX_TX_REG >> 0) & 0xff;
-}
-inline void set_uart_rx_tx_reg_data(volatile apb3uart_t *reg, uint8_t value){
-    reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
-}
-inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile apb3uart_t *reg){
-    return (reg->RX_TX_REG >> 14) & 0x1;
-}
-inline uint32_t get_uart_rx_tx_reg_tx_free(volatile apb3uart_t *reg){
-    return (reg->RX_TX_REG >> 15) & 0x1;
-}
-inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t *reg){
-    return (reg->INT_CTRL_REG >> 0) & 0x1;
-}
-inline void set_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t *reg, uint8_t value){
-    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
-}
-inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t *reg){
-    return (reg->INT_CTRL_REG >> 1) & 0x1;
-}
-inline void set_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t *reg, uint8_t value){
-    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
-}
-inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile apb3uart_t *reg){
-    return (reg->INT_CTRL_REG >> 8) & 0x1;
-}
-inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile apb3uart_t *reg){
-    return (reg->INT_CTRL_REG >> 9) & 0x1;
-}
-inline uint32_t get_uart_clk_divider_reg(volatile apb3uart_t *reg){
-    return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
-}
-inline void set_uart_clk_divider_reg(volatile apb3uart_t *reg, uint32_t value){
-    reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
-}
-inline uint32_t get_uart_frame_config_reg_data_lenght(volatile apb3uart_t *reg){
-    return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
-}
-inline void set_uart_frame_config_reg_data_lenght(volatile apb3uart_t *reg, uint8_t value){
-    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
-}
-inline uint32_t get_uart_frame_config_reg_parity(volatile apb3uart_t *reg){
-    return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
-}
-inline void set_uart_frame_config_reg_parity(volatile apb3uart_t *reg, uint8_t value){
-    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
-}
-inline uint32_t get_uart_frame_config_reg_stop_bit(volatile apb3uart_t *reg){
-    return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
-}
-inline void set_uart_frame_config_reg_stop_bit(volatile apb3uart_t *reg, uint8_t value){
-    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
-}
-inline uint32_t get_uart_status_reg_read_error(volatile apb3uart_t *reg){
-    return (reg->STATUS_REG >> 0) & 0x1;
-}
-inline uint32_t get_uart_status_reg_stall(volatile apb3uart_t *reg){
-    return (reg->STATUS_REG >> 1) & 0x1;
-}
-inline uint32_t get_uart_status_reg_break(volatile apb3uart_t *reg){
-    return (reg->STATUS_REG >> 8) & 0x1;
-}
-inline uint32_t get_uart_status_reg_break_detected(volatile apb3uart_t *reg){
-    return (reg->STATUS_REG >> 9) & 0x1;
-}
-inline void set_uart_status_reg_break_detected(volatile apb3uart_t *reg, uint8_t value){
-    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
-}
-inline uint32_t get_uart_status_reg_set_break(volatile apb3uart_t *reg){
-    return (reg->STATUS_REG >> 10) & 0x1;
-}
-inline void set_uart_status_reg_set_break(volatile apb3uart_t *reg, uint8_t value){
-    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
-}
-inline uint32_t get_uart_status_reg_clear_break(volatile apb3uart_t *reg){
-    return (reg->STATUS_REG >> 11) & 0x1;
-}
-inline void set_uart_status_reg_clear_break(volatile apb3uart_t *reg, uint8_t value){
-    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
-}
-#endif /* _BSP_APB3UART_H */
--- a/include/ehrenberg/devices/gen/aclint.h
+++ b/include/ehrenberg/devices/gen/aclint.h
@@ -0,0 +1,91 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-08-02 08:46:07 UTC 
+* by peakrdl_mnrs version 1.2.7
+*/
+
+#ifndef _BSP_ACLINT_H
+#define _BSP_ACLINT_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t MSIP0;
+    uint8_t fill0[16380];
+    volatile uint32_t MTIMECMP0LO;
+    volatile uint32_t MTIMECMP0HI;
+    uint8_t fill1[32752];
+    volatile uint32_t MTIME_LO;
+    volatile uint32_t MTIME_HI;
+}aclint_t;
+
+#define ACLINT_MSIP0_OFFS 0
+#define ACLINT_MSIP0_MASK 0x1
+#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
+
+#define ACLINT_MTIMECMP0LO_OFFS 0
+#define ACLINT_MTIMECMP0LO_MASK 0xffffffff
+#define ACLINT_MTIMECMP0LO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
+
+#define ACLINT_MTIMECMP0HI_OFFS 0
+#define ACLINT_MTIMECMP0HI_MASK 0xffffffff
+#define ACLINT_MTIMECMP0HI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
+
+#define ACLINT_MTIME_LO_OFFS 0
+#define ACLINT_MTIME_LO_MASK 0xffffffff
+#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
+
+#define ACLINT_MTIME_HI_OFFS 0
+#define ACLINT_MTIME_HI_MASK 0xffffffff
+#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
+
+//ACLINT_MSIP0
+inline uint32_t get_aclint_msip0(volatile aclint_t* reg){
+     return reg->MSIP0;
+}
+inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value){
+     reg->MSIP0 = value;
+}
+inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg){
+    return (reg->MSIP0 >> 0) & 0x1;
+}
+inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value){
+    reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
+}
+
+//ACLINT_MTIMECMP0LO
+inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg){
+    return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value){
+    reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//ACLINT_MTIMECMP0HI
+inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg){
+    return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value){
+    reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//ACLINT_MTIME_LO
+inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg){
+    return (reg->MTIME_LO >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value){
+    reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//ACLINT_MTIME_HI
+inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg){
+    return (reg->MTIME_HI >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value){
+    reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_ACLINT_H */
--- a/include/ehrenberg/devices/gen/apb3spi.h
+++ b/include/ehrenberg/devices/gen/apb3spi.h
@@ -0,0 +1,430 @@
+/*
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2025-02-17 15:56:47 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_APB3SPI_H
+#define _BSP_APB3SPI_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t DATA;
+    volatile uint32_t STATUS;
+    volatile uint32_t CONFIG;
+    volatile uint32_t INTR;
+    uint8_t fill0[16];
+    volatile uint32_t SCLK_CONFIG;
+    volatile uint32_t SSGEN_SETUP;
+    volatile uint32_t SSGEN_HOLD;
+    volatile uint32_t SSGEN_DISABLE;
+    volatile uint32_t SSGEN_ACTIVE_HIGH;
+    uint8_t fill1[12];
+    volatile uint32_t XIP_ENABLE;
+    volatile uint32_t XIP_CONFIG;
+    volatile uint32_t XIP_MODE;
+    uint8_t fill2[4];
+    volatile uint32_t XIP_WRITE;
+    volatile uint32_t XIP_READ_WRITE;
+    volatile uint32_t XIP_READ;
+}apb3spi_t;
+
+#define APB3SPI_DATA_DATA_OFFS 0
+#define APB3SPI_DATA_DATA_MASK 0xff
+#define APB3SPI_DATA_DATA(V) ((V & APB3SPI_DATA_DATA_MASK) << APB3SPI_DATA_DATA_OFFS)
+
+#define APB3SPI_DATA_WRITE_OFFS 8
+#define APB3SPI_DATA_WRITE_MASK 0x1
+#define APB3SPI_DATA_WRITE(V) ((V & APB3SPI_DATA_WRITE_MASK) << APB3SPI_DATA_WRITE_OFFS)
+
+#define APB3SPI_DATA_READ_OFFS 9
+#define APB3SPI_DATA_READ_MASK 0x1
+#define APB3SPI_DATA_READ(V) ((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS)
+
+#define APB3SPI_DATA_SSGEN_OFFS 11
+#define APB3SPI_DATA_SSGEN_MASK 0x1
+#define APB3SPI_DATA_SSGEN(V) ((V & APB3SPI_DATA_SSGEN_MASK) << APB3SPI_DATA_SSGEN_OFFS)
+
+#define APB3SPI_DATA_RX_DATA_INVALID_OFFS 31
+#define APB3SPI_DATA_RX_DATA_INVALID_MASK 0x1
+#define APB3SPI_DATA_RX_DATA_INVALID(V) ((V & APB3SPI_DATA_RX_DATA_INVALID_MASK) << APB3SPI_DATA_RX_DATA_INVALID_OFFS)
+
+#define APB3SPI_STATUS_TX_FREE_OFFS 0
+#define APB3SPI_STATUS_TX_FREE_MASK 0x3f
+#define APB3SPI_STATUS_TX_FREE(V) ((V & APB3SPI_STATUS_TX_FREE_MASK) << APB3SPI_STATUS_TX_FREE_OFFS)
+
+#define APB3SPI_STATUS_RX_AVAIL_OFFS 16
+#define APB3SPI_STATUS_RX_AVAIL_MASK 0x3f
+#define APB3SPI_STATUS_RX_AVAIL(V) ((V & APB3SPI_STATUS_RX_AVAIL_MASK) << APB3SPI_STATUS_RX_AVAIL_OFFS)
+
+#define APB3SPI_CONFIG_KIND_OFFS 0
+#define APB3SPI_CONFIG_KIND_MASK 0x3
+#define APB3SPI_CONFIG_KIND(V) ((V & APB3SPI_CONFIG_KIND_MASK) << APB3SPI_CONFIG_KIND_OFFS)
+
+#define APB3SPI_CONFIG_MODE_OFFS 4
+#define APB3SPI_CONFIG_MODE_MASK 0x3
+#define APB3SPI_CONFIG_MODE(V) ((V & APB3SPI_CONFIG_MODE_MASK) << APB3SPI_CONFIG_MODE_OFFS)
+
+#define APB3SPI_INTR_TX_IE_OFFS 0
+#define APB3SPI_INTR_TX_IE_MASK 0x1
+#define APB3SPI_INTR_TX_IE(V) ((V & APB3SPI_INTR_TX_IE_MASK) << APB3SPI_INTR_TX_IE_OFFS)
+
+#define APB3SPI_INTR_RX_IE_OFFS 1
+#define APB3SPI_INTR_RX_IE_MASK 0x1
+#define APB3SPI_INTR_RX_IE(V) ((V & APB3SPI_INTR_RX_IE_MASK) << APB3SPI_INTR_RX_IE_OFFS)
+
+#define APB3SPI_INTR_TX_IP_OFFS 8
+#define APB3SPI_INTR_TX_IP_MASK 0x1
+#define APB3SPI_INTR_TX_IP(V) ((V & APB3SPI_INTR_TX_IP_MASK) << APB3SPI_INTR_TX_IP_OFFS)
+
+#define APB3SPI_INTR_RX_IP_OFFS 9
+#define APB3SPI_INTR_RX_IP_MASK 0x1
+#define APB3SPI_INTR_RX_IP(V) ((V & APB3SPI_INTR_RX_IP_MASK) << APB3SPI_INTR_RX_IP_OFFS)
+
+#define APB3SPI_INTR_TX_ACTIVE_OFFS 16
+#define APB3SPI_INTR_TX_ACTIVE_MASK 0x1
+#define APB3SPI_INTR_TX_ACTIVE(V) ((V & APB3SPI_INTR_TX_ACTIVE_MASK) << APB3SPI_INTR_TX_ACTIVE_OFFS)
+
+#define APB3SPI_SCLK_CONFIG_OFFS 0
+#define APB3SPI_SCLK_CONFIG_MASK 0xfff
+#define APB3SPI_SCLK_CONFIG(V) ((V & APB3SPI_SCLK_CONFIG_MASK) << APB3SPI_SCLK_CONFIG_OFFS)
+
+#define APB3SPI_SSGEN_SETUP_OFFS 0
+#define APB3SPI_SSGEN_SETUP_MASK 0xfff
+#define APB3SPI_SSGEN_SETUP(V) ((V & APB3SPI_SSGEN_SETUP_MASK) << APB3SPI_SSGEN_SETUP_OFFS)
+
+#define APB3SPI_SSGEN_HOLD_OFFS 0
+#define APB3SPI_SSGEN_HOLD_MASK 0xfff
+#define APB3SPI_SSGEN_HOLD(V) ((V & APB3SPI_SSGEN_HOLD_MASK) << APB3SPI_SSGEN_HOLD_OFFS)
+
+#define APB3SPI_SSGEN_DISABLE_OFFS 0
+#define APB3SPI_SSGEN_DISABLE_MASK 0xfff
+#define APB3SPI_SSGEN_DISABLE(V) ((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS)
+
+#define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0
+#define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
+#define APB3SPI_SSGEN_ACTIVE_HIGH(V) ((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS)
+
+#define APB3SPI_XIP_ENABLE_OFFS 0
+#define APB3SPI_XIP_ENABLE_MASK 0x1
+#define APB3SPI_XIP_ENABLE(V) ((V & APB3SPI_XIP_ENABLE_MASK) << APB3SPI_XIP_ENABLE_OFFS)
+
+#define APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
+#define APB3SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
+#define APB3SPI_XIP_CONFIG_INSTRUCTION(V) ((V & APB3SPI_XIP_CONFIG_INSTRUCTION_MASK) << APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS)
+
+#define APB3SPI_XIP_CONFIG_ENABLE_OFFS 8
+#define APB3SPI_XIP_CONFIG_ENABLE_MASK 0x1
+#define APB3SPI_XIP_CONFIG_ENABLE(V) ((V & APB3SPI_XIP_CONFIG_ENABLE_MASK) << APB3SPI_XIP_CONFIG_ENABLE_OFFS)
+
+#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
+#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
+#define APB3SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
+
+#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
+#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
+#define APB3SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
+
+#define APB3SPI_XIP_MODE_INSTRUCTION_OFFS 0
+#define APB3SPI_XIP_MODE_INSTRUCTION_MASK 0x3
+#define APB3SPI_XIP_MODE_INSTRUCTION(V) ((V & APB3SPI_XIP_MODE_INSTRUCTION_MASK) << APB3SPI_XIP_MODE_INSTRUCTION_OFFS)
+
+#define APB3SPI_XIP_MODE_ADDRESS_OFFS 8
+#define APB3SPI_XIP_MODE_ADDRESS_MASK 0x3
+#define APB3SPI_XIP_MODE_ADDRESS(V) ((V & APB3SPI_XIP_MODE_ADDRESS_MASK) << APB3SPI_XIP_MODE_ADDRESS_OFFS)
+
+#define APB3SPI_XIP_MODE_DUMMY_OFFS 16
+#define APB3SPI_XIP_MODE_DUMMY_MASK 0x3
+#define APB3SPI_XIP_MODE_DUMMY(V) ((V & APB3SPI_XIP_MODE_DUMMY_MASK) << APB3SPI_XIP_MODE_DUMMY_OFFS)
+
+#define APB3SPI_XIP_MODE_PAYLOAD_OFFS 24
+#define APB3SPI_XIP_MODE_PAYLOAD_MASK 0x3
+#define APB3SPI_XIP_MODE_PAYLOAD(V) ((V & APB3SPI_XIP_MODE_PAYLOAD_MASK) << APB3SPI_XIP_MODE_PAYLOAD_OFFS)
+
+#define APB3SPI_XIP_WRITE_OFFS 0
+#define APB3SPI_XIP_WRITE_MASK 0xff
+#define APB3SPI_XIP_WRITE(V) ((V & APB3SPI_XIP_WRITE_MASK) << APB3SPI_XIP_WRITE_OFFS)
+
+#define APB3SPI_XIP_READ_WRITE_OFFS 0
+#define APB3SPI_XIP_READ_WRITE_MASK 0xff
+#define APB3SPI_XIP_READ_WRITE(V) ((V & APB3SPI_XIP_READ_WRITE_MASK) << APB3SPI_XIP_READ_WRITE_OFFS)
+
+#define APB3SPI_XIP_READ_OFFS 0
+#define APB3SPI_XIP_READ_MASK 0xff
+#define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS)
+
+//APB3SPI_DATA
+inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg){
+     return reg->DATA;
+}
+inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value){
+     reg->DATA = value;
+}
+inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg){
+    return (reg->DATA >> 8) & 0x1;
+}
+inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
+}
+inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg){
+    return (reg->DATA >> 9) & 0x1;
+}
+inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
+}
+inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t* reg){
+    return (reg->DATA >> 11) & 0x1;
+}
+inline void set_apb3spi_data_ssgen(volatile apb3spi_t* reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
+}
+inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg){
+    return (reg->DATA >> 31) & 0x1;
+}
+
+//APB3SPI_STATUS
+inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg){
+     return reg->STATUS;
+}
+inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg){
+    return (reg->STATUS >> 0) & 0x3f;
+}
+inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg){
+    return (reg->STATUS >> 16) & 0x3f;
+}
+
+//APB3SPI_CONFIG
+inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg){
+     return reg->CONFIG;
+}
+inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value){
+     reg->CONFIG = value;
+}
+inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg){
+    return (reg->CONFIG >> 0) & 0x3;
+}
+inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg){
+    return (reg->CONFIG >> 4) & 0x3;
+}
+inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
+}
+
+//APB3SPI_INTR
+inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg){
+     return reg->INTR;
+}
+inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value){
+     reg->INTR = value;
+}
+inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg){
+    return (reg->INTR >> 0) & 0x1;
+}
+inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value){
+    reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg){
+    return (reg->INTR >> 1) & 0x1;
+}
+inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value){
+    reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
+}
+inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg){
+    return (reg->INTR >> 8) & 0x1;
+}
+inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t* reg, uint8_t value){
+    reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8);
+}
+inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg){
+    return (reg->INTR >> 9) & 0x1;
+}
+inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t* reg, uint8_t value){
+    reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9);
+}
+inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg){
+    return (reg->INTR >> 16) & 0x1;
+}
+
+//APB3SPI_SCLK_CONFIG
+inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg){
+     return reg->SCLK_CONFIG;
+}
+inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value){
+     reg->SCLK_CONFIG = value;
+}
+inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg){
+    return (reg->SCLK_CONFIG >> 0) & 0xfff;
+}
+inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value){
+    reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
+}
+
+//APB3SPI_SSGEN_SETUP
+inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg){
+     return reg->SSGEN_SETUP;
+}
+inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value){
+     reg->SSGEN_SETUP = value;
+}
+inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg){
+    return (reg->SSGEN_SETUP >> 0) & 0xfff;
+}
+inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value){
+    reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
+}
+
+//APB3SPI_SSGEN_HOLD
+inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg){
+     return reg->SSGEN_HOLD;
+}
+inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value){
+     reg->SSGEN_HOLD = value;
+}
+inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg){
+    return (reg->SSGEN_HOLD >> 0) & 0xfff;
+}
+inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value){
+    reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
+}
+
+//APB3SPI_SSGEN_DISABLE
+inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg){
+     return reg->SSGEN_DISABLE;
+}
+inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value){
+     reg->SSGEN_DISABLE = value;
+}
+inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg){
+    return (reg->SSGEN_DISABLE >> 0) & 0xfff;
+}
+inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value){
+    reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
+}
+
+//APB3SPI_SSGEN_ACTIVE_HIGH
+inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg){
+     return reg->SSGEN_ACTIVE_HIGH;
+}
+inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value){
+     reg->SSGEN_ACTIVE_HIGH = value;
+}
+inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg){
+    return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
+}
+inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value){
+    reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
+}
+
+//APB3SPI_XIP_ENABLE
+inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg){
+     return reg->XIP_ENABLE;
+}
+inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value){
+     reg->XIP_ENABLE = value;
+}
+inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg){
+    return (reg->XIP_ENABLE >> 0) & 0x1;
+}
+inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
+}
+
+//APB3SPI_XIP_CONFIG
+inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg){
+     return reg->XIP_CONFIG;
+}
+inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value){
+     reg->XIP_CONFIG = value;
+}
+inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg){
+    return (reg->XIP_CONFIG >> 0) & 0xff;
+}
+inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg){
+    return (reg->XIP_CONFIG >> 8) & 0x1;
+}
+inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
+}
+inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg){
+    return (reg->XIP_CONFIG >> 16) & 0xff;
+}
+inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
+}
+inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg){
+    return (reg->XIP_CONFIG >> 24) & 0xf;
+}
+inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
+}
+
+//APB3SPI_XIP_MODE
+inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg){
+     return reg->XIP_MODE;
+}
+inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value){
+     reg->XIP_MODE = value;
+}
+inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg){
+    return (reg->XIP_MODE >> 0) & 0x3;
+}
+inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg){
+    return (reg->XIP_MODE >> 8) & 0x3;
+}
+inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
+}
+inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg){
+    return (reg->XIP_MODE >> 16) & 0x3;
+}
+inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
+}
+inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg){
+    return (reg->XIP_MODE >> 24) & 0x3;
+}
+inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
+}
+
+//APB3SPI_XIP_WRITE
+inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value){
+     reg->XIP_WRITE = value;
+}
+inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
+}
+
+//APB3SPI_XIP_READ_WRITE
+inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value){
+     reg->XIP_READ_WRITE = value;
+}
+inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
+}
+
+//APB3SPI_XIP_READ
+inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg){
+     return reg->XIP_READ;
+}
+inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg){
+    return (reg->XIP_READ >> 0) & 0xff;
+}
+
+#endif /* _BSP_APB3SPI_H */
--- a/include/ehrenberg/devices/gen/camera.h
+++ b/include/ehrenberg/devices/gen/camera.h
@@ -0,0 +1,337 @@
+/*
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2025-02-28 17:25:03 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_CAMERA_H
+#define _BSP_CAMERA_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t PIXEL;
+    volatile uint32_t CONFIG;
+    volatile uint32_t CONFIG2;
+    volatile uint32_t DATA_SIZE;
+    volatile uint32_t START;
+    volatile uint32_t STATUS;
+    volatile uint32_t CAMERA_CLOCK_CTRL;
+    volatile uint32_t IE;
+    volatile uint32_t IP;
+}camera_t;
+
+#define CAMERA_PIXEL_OFFS 0
+#define CAMERA_PIXEL_MASK 0xffffffff
+#define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS)
+
+#define CAMERA_CONFIG_OUTPUT_CURR_OFFS 0
+#define CAMERA_CONFIG_OUTPUT_CURR_MASK 0x3
+#define CAMERA_CONFIG_OUTPUT_CURR(V) ((V & CAMERA_CONFIG_OUTPUT_CURR_MASK) << CAMERA_CONFIG_OUTPUT_CURR_OFFS)
+
+#define CAMERA_CONFIG_OFFSET_RAMP_OFFS 2
+#define CAMERA_CONFIG_OFFSET_RAMP_MASK 0x3
+#define CAMERA_CONFIG_OFFSET_RAMP(V) ((V & CAMERA_CONFIG_OFFSET_RAMP_MASK) << CAMERA_CONFIG_OFFSET_RAMP_OFFS)
+
+#define CAMERA_CONFIG_RAMP_GAIN_OFFS 4
+#define CAMERA_CONFIG_RAMP_GAIN_MASK 0x3
+#define CAMERA_CONFIG_RAMP_GAIN(V) ((V & CAMERA_CONFIG_RAMP_GAIN_MASK) << CAMERA_CONFIG_RAMP_GAIN_OFFS)
+
+#define CAMERA_CONFIG_VRST_PIX_OFFS 6
+#define CAMERA_CONFIG_VRST_PIX_MASK 0x3
+#define CAMERA_CONFIG_VRST_PIX(V) ((V & CAMERA_CONFIG_VRST_PIX_MASK) << CAMERA_CONFIG_VRST_PIX_OFFS)
+
+#define CAMERA_CONFIG_ROWS_IN_RESET_OFFS 8
+#define CAMERA_CONFIG_ROWS_IN_RESET_MASK 0xff
+#define CAMERA_CONFIG_ROWS_IN_RESET(V) ((V & CAMERA_CONFIG_ROWS_IN_RESET_MASK) << CAMERA_CONFIG_ROWS_IN_RESET_OFFS)
+
+#define CAMERA_CONFIG_HIGH_SPEED_OFFS 16
+#define CAMERA_CONFIG_HIGH_SPEED_MASK 0x1
+#define CAMERA_CONFIG_HIGH_SPEED(V) ((V & CAMERA_CONFIG_HIGH_SPEED_MASK) << CAMERA_CONFIG_HIGH_SPEED_OFFS)
+
+#define CAMERA_CONFIG_IDLE_MODE_OFFS 17
+#define CAMERA_CONFIG_IDLE_MODE_MASK 0x1
+#define CAMERA_CONFIG_IDLE_MODE(V) ((V & CAMERA_CONFIG_IDLE_MODE_MASK) << CAMERA_CONFIG_IDLE_MODE_OFFS)
+
+#define CAMERA_CONFIG_CVC_CURR_OFFS 18
+#define CAMERA_CONFIG_CVC_CURR_MASK 0x3
+#define CAMERA_CONFIG_CVC_CURR(V) ((V & CAMERA_CONFIG_CVC_CURR_MASK) << CAMERA_CONFIG_CVC_CURR_OFFS)
+
+#define CAMERA_CONFIG_VREF_OFFS 20
+#define CAMERA_CONFIG_VREF_MASK 0x3
+#define CAMERA_CONFIG_VREF(V) ((V & CAMERA_CONFIG_VREF_MASK) << CAMERA_CONFIG_VREF_OFFS)
+
+#define CAMERA_CONFIG_MCLK_MODE_OFFS 22
+#define CAMERA_CONFIG_MCLK_MODE_MASK 0x3
+#define CAMERA_CONFIG_MCLK_MODE(V) ((V & CAMERA_CONFIG_MCLK_MODE_MASK) << CAMERA_CONFIG_MCLK_MODE_OFFS)
+
+#define CAMERA_CONFIG_OUTPUT_MODE_OFFS 24
+#define CAMERA_CONFIG_OUTPUT_MODE_MASK 0x1
+#define CAMERA_CONFIG_OUTPUT_MODE(V) ((V & CAMERA_CONFIG_OUTPUT_MODE_MASK) << CAMERA_CONFIG_OUTPUT_MODE_OFFS)
+
+#define CAMERA_CONFIG_CDS_GAIN_OFFS 25
+#define CAMERA_CONFIG_CDS_GAIN_MASK 0x1
+#define CAMERA_CONFIG_CDS_GAIN(V) ((V & CAMERA_CONFIG_CDS_GAIN_MASK) << CAMERA_CONFIG_CDS_GAIN_OFFS)
+
+#define CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS 26
+#define CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK 0x1
+#define CAMERA_CONFIG_BIAS_CURR_INCREASE(V) ((V & CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK) << CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS)
+
+#define CAMERA_CONFIG_ROWS_DELAY_OFFS 27
+#define CAMERA_CONFIG_ROWS_DELAY_MASK 0x1f
+#define CAMERA_CONFIG_ROWS_DELAY(V) ((V & CAMERA_CONFIG_ROWS_DELAY_MASK) << CAMERA_CONFIG_ROWS_DELAY_OFFS)
+
+#define CAMERA_CONFIG2_AUTO_IDLE_OFFS 0
+#define CAMERA_CONFIG2_AUTO_IDLE_MASK 0x1
+#define CAMERA_CONFIG2_AUTO_IDLE(V) ((V & CAMERA_CONFIG2_AUTO_IDLE_MASK) << CAMERA_CONFIG2_AUTO_IDLE_OFFS)
+
+#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS 1
+#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK 0x1
+#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME(V) ((V & CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK) << CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS)
+
+#define CAMERA_DATA_SIZE_OFFS 0
+#define CAMERA_DATA_SIZE_MASK 0x3
+#define CAMERA_DATA_SIZE(V) ((V & CAMERA_DATA_SIZE_MASK) << CAMERA_DATA_SIZE_OFFS)
+
+#define CAMERA_START_OFFS 0
+#define CAMERA_START_MASK 0x1
+#define CAMERA_START(V) ((V & CAMERA_START_MASK) << CAMERA_START_OFFS)
+
+#define CAMERA_STATUS_OFFS 0
+#define CAMERA_STATUS_MASK 0x1
+#define CAMERA_STATUS(V) ((V & CAMERA_STATUS_MASK) << CAMERA_STATUS_OFFS)
+
+#define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0
+#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfff
+#define CAMERA_CAMERA_CLOCK_CTRL(V) ((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS)
+
+#define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0
+#define CAMERA_IE_EN_PIXEL_AVAIL_MASK 0x1
+#define CAMERA_IE_EN_PIXEL_AVAIL(V) ((V & CAMERA_IE_EN_PIXEL_AVAIL_MASK) << CAMERA_IE_EN_PIXEL_AVAIL_OFFS)
+
+#define CAMERA_IE_EN_FRAME_FINISHED_OFFS 1
+#define CAMERA_IE_EN_FRAME_FINISHED_MASK 0x1
+#define CAMERA_IE_EN_FRAME_FINISHED(V) ((V & CAMERA_IE_EN_FRAME_FINISHED_MASK) << CAMERA_IE_EN_FRAME_FINISHED_OFFS)
+
+#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS 0
+#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK 0x1
+#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND(V) ((V & CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK) << CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS)
+
+#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS 1
+#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1
+#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS)
+
+//CAMERA_PIXEL
+inline uint32_t get_camera_pixel(volatile camera_t* reg){
+    return (reg->PIXEL >> 0) & 0xffffffff;
+}
+inline void set_camera_pixel(volatile camera_t* reg, uint32_t value){
+    reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//CAMERA_CONFIG
+inline uint32_t get_camera_config(volatile camera_t* reg){
+     return reg->CONFIG;
+}
+inline void set_camera_config(volatile camera_t* reg, uint32_t value){
+     reg->CONFIG = value;
+}
+inline uint32_t get_camera_config_output_curr(volatile camera_t* reg){
+    return (reg->CONFIG >> 0) & 0x3;
+}
+inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg){
+    return (reg->CONFIG >> 2) & 0x3;
+}
+inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2);
+}
+inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg){
+    return (reg->CONFIG >> 4) & 0x3;
+}
+inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
+}
+inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg){
+    return (reg->CONFIG >> 6) & 0x3;
+}
+inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6);
+}
+inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg){
+    return (reg->CONFIG >> 8) & 0xff;
+}
+inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8);
+}
+inline uint32_t get_camera_config_high_speed(volatile camera_t* reg){
+    return (reg->CONFIG >> 16) & 0x1;
+}
+inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16);
+}
+inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg){
+    return (reg->CONFIG >> 17) & 0x1;
+}
+inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17);
+}
+inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg){
+    return (reg->CONFIG >> 18) & 0x3;
+}
+inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18);
+}
+inline uint32_t get_camera_config_vref(volatile camera_t* reg){
+    return (reg->CONFIG >> 20) & 0x3;
+}
+inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20);
+}
+inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg){
+    return (reg->CONFIG >> 22) & 0x3;
+}
+inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22);
+}
+inline uint32_t get_camera_config_output_mode(volatile camera_t* reg){
+    return (reg->CONFIG >> 24) & 0x1;
+}
+inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24);
+}
+inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg){
+    return (reg->CONFIG >> 25) & 0x1;
+}
+inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25);
+}
+inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg){
+    return (reg->CONFIG >> 26) & 0x1;
+}
+inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26);
+}
+inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg){
+    return (reg->CONFIG >> 27) & 0x1f;
+}
+inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27);
+}
+
+//CAMERA_CONFIG2
+inline uint32_t get_camera_config2(volatile camera_t* reg){
+     return reg->CONFIG2;
+}
+inline void set_camera_config2(volatile camera_t* reg, uint32_t value){
+     reg->CONFIG2 = value;
+}
+inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg){
+    return (reg->CONFIG2 >> 0) & 0x1;
+}
+inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg){
+    return (reg->CONFIG2 >> 1) & 0x1;
+}
+inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1);
+}
+
+//CAMERA_DATA_SIZE
+inline uint32_t get_camera_data_size(volatile camera_t* reg){
+     return reg->DATA_SIZE;
+}
+inline void set_camera_data_size(volatile camera_t* reg, uint32_t value){
+     reg->DATA_SIZE = value;
+}
+inline uint32_t get_camera_data_size_data_size(volatile camera_t* reg){
+    return (reg->DATA_SIZE >> 0) & 0x3;
+}
+inline void set_camera_data_size_data_size(volatile camera_t* reg, uint8_t value){
+    reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0);
+}
+
+//CAMERA_START
+inline uint32_t get_camera_start(volatile camera_t* reg){
+     return reg->START;
+}
+inline void set_camera_start(volatile camera_t* reg, uint32_t value){
+     reg->START = value;
+}
+inline uint32_t get_camera_start_start(volatile camera_t* reg){
+    return (reg->START >> 0) & 0x1;
+}
+inline void set_camera_start_start(volatile camera_t* reg, uint8_t value){
+    reg->START = (reg->START & ~(0x1U << 0)) | (value << 0);
+}
+
+//CAMERA_STATUS
+inline uint32_t get_camera_status(volatile camera_t* reg){
+     return reg->STATUS;
+}
+inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg){
+    return (reg->STATUS >> 0) & 0x1;
+}
+
+//CAMERA_CAMERA_CLOCK_CTRL
+inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg){
+     return reg->CAMERA_CLOCK_CTRL;
+}
+inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value){
+     reg->CAMERA_CLOCK_CTRL = value;
+}
+inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg){
+    return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff;
+}
+inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value){
+    reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0);
+}
+
+//CAMERA_IE
+inline uint32_t get_camera_ie(volatile camera_t* reg){
+     return reg->IE;
+}
+inline void set_camera_ie(volatile camera_t* reg, uint32_t value){
+     reg->IE = value;
+}
+inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg){
+    return (reg->IE >> 0) & 0x1;
+}
+inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg){
+    return (reg->IE >> 1) & 0x1;
+}
+inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
+}
+
+//CAMERA_IP
+inline uint32_t get_camera_ip(volatile camera_t* reg){
+     return reg->IP;
+}
+inline void set_camera_ip(volatile camera_t* reg, uint32_t value){
+     reg->IP = value;
+}
+inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg){
+    return (reg->IP >> 0) & 0x1;
+}
+inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value){
+    reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg){
+    return (reg->IP >> 1) & 0x1;
+}
+inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value){
+    reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
+}
+
+#endif /* _BSP_CAMERA_H */
--- a/include/ehrenberg/devices/gen/dma.h
+++ b/include/ehrenberg/devices/gen/dma.h
@@ -0,0 +1,454 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-08-02 08:46:07 UTC 
+* by peakrdl_mnrs version 1.2.7
+*/
+
+#ifndef _BSP_DMA_H
+#define _BSP_DMA_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t CONTROL;
+    volatile uint32_t STATUS;
+    volatile uint32_t IE;
+    volatile uint32_t IP;
+    volatile uint32_t CH0_EVENT;
+    volatile uint32_t CH0_TRANSFER;
+    volatile uint32_t CH0_SRC_START_ADDR;
+    volatile uint32_t CH0_SRC_ADDR_INC;
+    volatile uint32_t CH0_DST_START_ADDR;
+    volatile uint32_t CH0_DST_ADDR_INC;
+    volatile uint32_t CH1_EVENT;
+    volatile uint32_t CH1_TRANSFER;
+    volatile uint32_t CH1_SRC_START_ADDR;
+    volatile uint32_t CH1_SRC_ADDR_INC;
+    volatile uint32_t CH1_DST_START_ADDR;
+    volatile uint32_t CH1_DST_ADDR_INC;
+}dma_t;
+
+#define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
+#define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
+#define DMA_CONTROL_CH0_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS)
+
+#define DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS 1
+#define DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK 0x1
+#define DMA_CONTROL_CH1_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS)
+
+#define DMA_STATUS_CH0_BUSY_OFFS 0
+#define DMA_STATUS_CH0_BUSY_MASK 0x1
+#define DMA_STATUS_CH0_BUSY(V) ((V & DMA_STATUS_CH0_BUSY_MASK) << DMA_STATUS_CH0_BUSY_OFFS)
+
+#define DMA_STATUS_CH1_BUSY_OFFS 1
+#define DMA_STATUS_CH1_BUSY_MASK 0x1
+#define DMA_STATUS_CH1_BUSY(V) ((V & DMA_STATUS_CH1_BUSY_MASK) << DMA_STATUS_CH1_BUSY_OFFS)
+
+#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS 0
+#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK 0x1
+#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS)
+
+#define DMA_IE_CH0_IE_TRANSFER_DONE_OFFS 1
+#define DMA_IE_CH0_IE_TRANSFER_DONE_MASK 0x1
+#define DMA_IE_CH0_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_TRANSFER_DONE_OFFS)
+
+#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS 2
+#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK 0x1
+#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS)
+
+#define DMA_IE_CH1_IE_TRANSFER_DONE_OFFS 3
+#define DMA_IE_CH1_IE_TRANSFER_DONE_MASK 0x1
+#define DMA_IE_CH1_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_TRANSFER_DONE_OFFS)
+
+#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS 0
+#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK 0x1
+#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS)
+
+#define DMA_IP_CH0_IP_TRANSFER_DONE_OFFS 1
+#define DMA_IP_CH0_IP_TRANSFER_DONE_MASK 0x1
+#define DMA_IP_CH0_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_TRANSFER_DONE_OFFS)
+
+#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS 2
+#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK 0x1
+#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS)
+
+#define DMA_IP_CH1_IP_TRANSFER_DONE_OFFS 3
+#define DMA_IP_CH1_IP_TRANSFER_DONE_MASK 0x1
+#define DMA_IP_CH1_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_TRANSFER_DONE_OFFS)
+
+#define DMA_CH0_EVENT_SELECT_OFFS 0
+#define DMA_CH0_EVENT_SELECT_MASK 0x1f
+#define DMA_CH0_EVENT_SELECT(V) ((V & DMA_CH0_EVENT_SELECT_MASK) << DMA_CH0_EVENT_SELECT_OFFS)
+
+#define DMA_CH0_EVENT_COMBINE_OFFS 31
+#define DMA_CH0_EVENT_COMBINE_MASK 0x1
+#define DMA_CH0_EVENT_COMBINE(V) ((V & DMA_CH0_EVENT_COMBINE_MASK) << DMA_CH0_EVENT_COMBINE_OFFS)
+
+#define DMA_CH0_TRANSFER_WIDTH_OFFS 0
+#define DMA_CH0_TRANSFER_WIDTH_MASK 0x3
+#define DMA_CH0_TRANSFER_WIDTH(V) ((V & DMA_CH0_TRANSFER_WIDTH_MASK) << DMA_CH0_TRANSFER_WIDTH_OFFS)
+
+#define DMA_CH0_TRANSFER_SEG_LENGTH_OFFS 2
+#define DMA_CH0_TRANSFER_SEG_LENGTH_MASK 0x3ff
+#define DMA_CH0_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH0_TRANSFER_SEG_LENGTH_MASK) << DMA_CH0_TRANSFER_SEG_LENGTH_OFFS)
+
+#define DMA_CH0_TRANSFER_SEG_COUNT_OFFS 12
+#define DMA_CH0_TRANSFER_SEG_COUNT_MASK 0xfffff
+#define DMA_CH0_TRANSFER_SEG_COUNT(V) ((V & DMA_CH0_TRANSFER_SEG_COUNT_MASK) << DMA_CH0_TRANSFER_SEG_COUNT_OFFS)
+
+#define DMA_CH0_SRC_START_ADDR_OFFS 0
+#define DMA_CH0_SRC_START_ADDR_MASK 0xffffffff
+#define DMA_CH0_SRC_START_ADDR(V) ((V & DMA_CH0_SRC_START_ADDR_MASK) << DMA_CH0_SRC_START_ADDR_OFFS)
+
+#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS 0
+#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
+#define DMA_CH0_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS)
+
+#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
+#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
+#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS)
+
+#define DMA_CH0_DST_START_ADDR_OFFS 0
+#define DMA_CH0_DST_START_ADDR_MASK 0xffffffff
+#define DMA_CH0_DST_START_ADDR(V) ((V & DMA_CH0_DST_START_ADDR_MASK) << DMA_CH0_DST_START_ADDR_OFFS)
+
+#define DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS 0
+#define DMA_CH0_DST_ADDR_INC_DST_STEP_MASK 0xfff
+#define DMA_CH0_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS)
+
+#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS 12
+#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
+#define DMA_CH0_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS)
+
+#define DMA_CH1_EVENT_SELECT_OFFS 0
+#define DMA_CH1_EVENT_SELECT_MASK 0x1f
+#define DMA_CH1_EVENT_SELECT(V) ((V & DMA_CH1_EVENT_SELECT_MASK) << DMA_CH1_EVENT_SELECT_OFFS)
+
+#define DMA_CH1_EVENT_COMBINE_OFFS 31
+#define DMA_CH1_EVENT_COMBINE_MASK 0x1
+#define DMA_CH1_EVENT_COMBINE(V) ((V & DMA_CH1_EVENT_COMBINE_MASK) << DMA_CH1_EVENT_COMBINE_OFFS)
+
+#define DMA_CH1_TRANSFER_WIDTH_OFFS 0
+#define DMA_CH1_TRANSFER_WIDTH_MASK 0x3
+#define DMA_CH1_TRANSFER_WIDTH(V) ((V & DMA_CH1_TRANSFER_WIDTH_MASK) << DMA_CH1_TRANSFER_WIDTH_OFFS)
+
+#define DMA_CH1_TRANSFER_SEG_LENGTH_OFFS 2
+#define DMA_CH1_TRANSFER_SEG_LENGTH_MASK 0x3ff
+#define DMA_CH1_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH1_TRANSFER_SEG_LENGTH_MASK) << DMA_CH1_TRANSFER_SEG_LENGTH_OFFS)
+
+#define DMA_CH1_TRANSFER_SEG_COUNT_OFFS 12
+#define DMA_CH1_TRANSFER_SEG_COUNT_MASK 0xfffff
+#define DMA_CH1_TRANSFER_SEG_COUNT(V) ((V & DMA_CH1_TRANSFER_SEG_COUNT_MASK) << DMA_CH1_TRANSFER_SEG_COUNT_OFFS)
+
+#define DMA_CH1_SRC_START_ADDR_OFFS 0
+#define DMA_CH1_SRC_START_ADDR_MASK 0xffffffff
+#define DMA_CH1_SRC_START_ADDR(V) ((V & DMA_CH1_SRC_START_ADDR_MASK) << DMA_CH1_SRC_START_ADDR_OFFS)
+
+#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS 0
+#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
+#define DMA_CH1_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS)
+
+#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
+#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
+#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS)
+
+#define DMA_CH1_DST_START_ADDR_OFFS 0
+#define DMA_CH1_DST_START_ADDR_MASK 0xffffffff
+#define DMA_CH1_DST_START_ADDR(V) ((V & DMA_CH1_DST_START_ADDR_MASK) << DMA_CH1_DST_START_ADDR_OFFS)
+
+#define DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS 0
+#define DMA_CH1_DST_ADDR_INC_DST_STEP_MASK 0xfff
+#define DMA_CH1_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS)
+
+#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS 12
+#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
+#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
+
+//DMA_CONTROL
+inline uint32_t get_dma_control(volatile dma_t* reg){
+     return reg->CONTROL;
+}
+inline void set_dma_control(volatile dma_t* reg, uint32_t value){
+     reg->CONTROL = value;
+}
+inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg){
+    return (reg->CONTROL >> 0) & 0x1;
+}
+inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg){
+    return (reg->CONTROL >> 1) & 0x1;
+}
+inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
+}
+
+//DMA_STATUS
+inline uint32_t get_dma_status(volatile dma_t* reg){
+     return reg->STATUS;
+}
+inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg){
+    return (reg->STATUS >> 0) & 0x1;
+}
+inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg){
+    return (reg->STATUS >> 1) & 0x1;
+}
+
+//DMA_IE
+inline uint32_t get_dma_ie(volatile dma_t* reg){
+     return reg->IE;
+}
+inline void set_dma_ie(volatile dma_t* reg, uint32_t value){
+     reg->IE = value;
+}
+inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg){
+    return (reg->IE >> 0) & 0x1;
+}
+inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg){
+    return (reg->IE >> 1) & 0x1;
+}
+inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
+}
+inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg){
+    return (reg->IE >> 2) & 0x1;
+}
+inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
+}
+inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg){
+    return (reg->IE >> 3) & 0x1;
+}
+inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
+}
+
+//DMA_IP
+inline uint32_t get_dma_ip(volatile dma_t* reg){
+     return reg->IP;
+}
+inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg){
+    return (reg->IP >> 0) & 0x1;
+}
+inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg){
+    return (reg->IP >> 1) & 0x1;
+}
+inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg){
+    return (reg->IP >> 2) & 0x1;
+}
+inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg){
+    return (reg->IP >> 3) & 0x1;
+}
+
+//DMA_CH0_EVENT
+inline uint32_t get_dma_ch0_event(volatile dma_t* reg){
+     return reg->CH0_EVENT;
+}
+inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value){
+     reg->CH0_EVENT = value;
+}
+inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg){
+    return (reg->CH0_EVENT >> 0) & 0x1f;
+}
+inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value){
+    reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg){
+    return (reg->CH0_EVENT >> 31) & 0x1;
+}
+inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value){
+    reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
+}
+
+//DMA_CH0_TRANSFER
+inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg){
+     return reg->CH0_TRANSFER;
+}
+inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value){
+     reg->CH0_TRANSFER = value;
+}
+inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg){
+    return (reg->CH0_TRANSFER >> 0) & 0x3;
+}
+inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value){
+    reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg){
+    return (reg->CH0_TRANSFER >> 2) & 0x3ff;
+}
+inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value){
+    reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
+}
+inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg){
+    return (reg->CH0_TRANSFER >> 12) & 0xfffff;
+}
+inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value){
+    reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
+}
+
+//DMA_CH0_SRC_START_ADDR
+inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg){
+    return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff;
+}
+inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value){
+    reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//DMA_CH0_SRC_ADDR_INC
+inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg){
+     return reg->CH0_SRC_ADDR_INC;
+}
+inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value){
+     reg->CH0_SRC_ADDR_INC = value;
+}
+inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg){
+    return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff;
+}
+inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
+    reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg){
+    return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff;
+}
+inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
+    reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
+}
+
+//DMA_CH0_DST_START_ADDR
+inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg){
+    return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff;
+}
+inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value){
+    reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//DMA_CH0_DST_ADDR_INC
+inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg){
+     return reg->CH0_DST_ADDR_INC;
+}
+inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value){
+     reg->CH0_DST_ADDR_INC = value;
+}
+inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg){
+    return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff;
+}
+inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
+    reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg){
+    return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff;
+}
+inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
+    reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
+}
+
+//DMA_CH1_EVENT
+inline uint32_t get_dma_ch1_event(volatile dma_t* reg){
+     return reg->CH1_EVENT;
+}
+inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value){
+     reg->CH1_EVENT = value;
+}
+inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg){
+    return (reg->CH1_EVENT >> 0) & 0x1f;
+}
+inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value){
+    reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg){
+    return (reg->CH1_EVENT >> 31) & 0x1;
+}
+inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value){
+    reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
+}
+
+//DMA_CH1_TRANSFER
+inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg){
+     return reg->CH1_TRANSFER;
+}
+inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value){
+     reg->CH1_TRANSFER = value;
+}
+inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg){
+    return (reg->CH1_TRANSFER >> 0) & 0x3;
+}
+inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value){
+    reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg){
+    return (reg->CH1_TRANSFER >> 2) & 0x3ff;
+}
+inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value){
+    reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
+}
+inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg){
+    return (reg->CH1_TRANSFER >> 12) & 0xfffff;
+}
+inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value){
+    reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
+}
+
+//DMA_CH1_SRC_START_ADDR
+inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg){
+    return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff;
+}
+inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value){
+    reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//DMA_CH1_SRC_ADDR_INC
+inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg){
+     return reg->CH1_SRC_ADDR_INC;
+}
+inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value){
+     reg->CH1_SRC_ADDR_INC = value;
+}
+inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg){
+    return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff;
+}
+inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
+    reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg){
+    return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff;
+}
+inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
+    reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
+}
+
+//DMA_CH1_DST_START_ADDR
+inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg){
+    return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff;
+}
+inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value){
+    reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//DMA_CH1_DST_ADDR_INC
+inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg){
+     return reg->CH1_DST_ADDR_INC;
+}
+inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value){
+     reg->CH1_DST_ADDR_INC = value;
+}
+inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg){
+    return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff;
+}
+inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
+    reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg){
+    return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff;
+}
+inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
+    reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
+}
+
+#endif /* _BSP_DMA_H */
--- a/include/ehrenberg/devices/gen/gpio.h
+++ b/include/ehrenberg/devices/gen/gpio.h
@@ -0,0 +1,501 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-12-06 09:43:24 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_GPIO_H
+#define _BSP_GPIO_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t VALUE;
+    volatile uint32_t WRITE;
+    volatile uint32_t WRITEENABLE;
+    volatile uint32_t PULLUP;
+    volatile uint32_t PULDOWN;
+    volatile uint32_t DRIVESTRENGTH_0;
+    volatile uint32_t DRIVESTRENGTH_1;
+    volatile uint32_t DRIVESTRENGTH_2;
+    volatile uint32_t DRIVESTRENGTH_3;
+    volatile uint32_t IE;
+    volatile uint32_t IP;
+    volatile uint32_t IRQ_TRIGGER;
+    volatile uint32_t IRQ_TYPE;
+    volatile uint32_t BOOT_SEL;
+}gpio_t;
+
+#define GPIO_VALUE_OFFS 0
+#define GPIO_VALUE_MASK 0xffffffff
+#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS)
+
+#define GPIO_WRITE_OFFS 0
+#define GPIO_WRITE_MASK 0xffffffff
+#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS)
+
+#define GPIO_WRITEENABLE_OFFS 0
+#define GPIO_WRITEENABLE_MASK 0xffffffff
+#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
+
+#define GPIO_PULLUP_OFFS 0
+#define GPIO_PULLUP_MASK 0xffffffff
+#define GPIO_PULLUP(V) ((V & GPIO_PULLUP_MASK) << GPIO_PULLUP_OFFS)
+
+#define GPIO_PULDOWN_OFFS 0
+#define GPIO_PULDOWN_MASK 0xffffffff
+#define GPIO_PULDOWN(V) ((V & GPIO_PULDOWN_MASK) << GPIO_PULDOWN_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_0_OFFS 0
+#define GPIO_DRIVESTRENGTH_0_PIN_0_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_0(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_0_MASK) << GPIO_DRIVESTRENGTH_0_PIN_0_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_1_OFFS 4
+#define GPIO_DRIVESTRENGTH_0_PIN_1_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_1(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_1_MASK) << GPIO_DRIVESTRENGTH_0_PIN_1_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_2_OFFS 8
+#define GPIO_DRIVESTRENGTH_0_PIN_2_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_2(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_2_MASK) << GPIO_DRIVESTRENGTH_0_PIN_2_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_3_OFFS 12
+#define GPIO_DRIVESTRENGTH_0_PIN_3_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_3(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_3_MASK) << GPIO_DRIVESTRENGTH_0_PIN_3_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_4_OFFS 16
+#define GPIO_DRIVESTRENGTH_0_PIN_4_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_4(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_4_MASK) << GPIO_DRIVESTRENGTH_0_PIN_4_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_5_OFFS 20
+#define GPIO_DRIVESTRENGTH_0_PIN_5_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_5(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_5_MASK) << GPIO_DRIVESTRENGTH_0_PIN_5_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_6_OFFS 24
+#define GPIO_DRIVESTRENGTH_0_PIN_6_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_6(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_6_MASK) << GPIO_DRIVESTRENGTH_0_PIN_6_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_7_OFFS 28
+#define GPIO_DRIVESTRENGTH_0_PIN_7_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_7(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_7_MASK) << GPIO_DRIVESTRENGTH_0_PIN_7_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_8_OFFS 0
+#define GPIO_DRIVESTRENGTH_1_PIN_8_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_8(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_8_MASK) << GPIO_DRIVESTRENGTH_1_PIN_8_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_9_OFFS 4
+#define GPIO_DRIVESTRENGTH_1_PIN_9_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_9(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_9_MASK) << GPIO_DRIVESTRENGTH_1_PIN_9_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_10_OFFS 8
+#define GPIO_DRIVESTRENGTH_1_PIN_10_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_10(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_10_MASK) << GPIO_DRIVESTRENGTH_1_PIN_10_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_11_OFFS 12
+#define GPIO_DRIVESTRENGTH_1_PIN_11_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_11(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_11_MASK) << GPIO_DRIVESTRENGTH_1_PIN_11_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_12_OFFS 16
+#define GPIO_DRIVESTRENGTH_1_PIN_12_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_12(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_12_MASK) << GPIO_DRIVESTRENGTH_1_PIN_12_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_13_OFFS 20
+#define GPIO_DRIVESTRENGTH_1_PIN_13_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_13(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_13_MASK) << GPIO_DRIVESTRENGTH_1_PIN_13_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_14_OFFS 24
+#define GPIO_DRIVESTRENGTH_1_PIN_14_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_14(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_14_MASK) << GPIO_DRIVESTRENGTH_1_PIN_14_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_15_OFFS 28
+#define GPIO_DRIVESTRENGTH_1_PIN_15_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_15(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_15_MASK) << GPIO_DRIVESTRENGTH_1_PIN_15_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_16_OFFS 0
+#define GPIO_DRIVESTRENGTH_2_PIN_16_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_16(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_16_MASK) << GPIO_DRIVESTRENGTH_2_PIN_16_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_17_OFFS 4
+#define GPIO_DRIVESTRENGTH_2_PIN_17_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_17(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_17_MASK) << GPIO_DRIVESTRENGTH_2_PIN_17_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_18_OFFS 8
+#define GPIO_DRIVESTRENGTH_2_PIN_18_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_18(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_18_MASK) << GPIO_DRIVESTRENGTH_2_PIN_18_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_19_OFFS 12
+#define GPIO_DRIVESTRENGTH_2_PIN_19_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_19(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_19_MASK) << GPIO_DRIVESTRENGTH_2_PIN_19_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_20_OFFS 16
+#define GPIO_DRIVESTRENGTH_2_PIN_20_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_20(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_20_MASK) << GPIO_DRIVESTRENGTH_2_PIN_20_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_21_OFFS 20
+#define GPIO_DRIVESTRENGTH_2_PIN_21_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_21(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_21_MASK) << GPIO_DRIVESTRENGTH_2_PIN_21_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_22_OFFS 24
+#define GPIO_DRIVESTRENGTH_2_PIN_22_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_22(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_22_MASK) << GPIO_DRIVESTRENGTH_2_PIN_22_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_23_OFFS 28
+#define GPIO_DRIVESTRENGTH_2_PIN_23_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_23(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_23_MASK) << GPIO_DRIVESTRENGTH_2_PIN_23_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_24_OFFS 0
+#define GPIO_DRIVESTRENGTH_3_PIN_24_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_24(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_24_MASK) << GPIO_DRIVESTRENGTH_3_PIN_24_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_25_OFFS 4
+#define GPIO_DRIVESTRENGTH_3_PIN_25_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_25(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_25_MASK) << GPIO_DRIVESTRENGTH_3_PIN_25_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_26_OFFS 8
+#define GPIO_DRIVESTRENGTH_3_PIN_26_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_26(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_26_MASK) << GPIO_DRIVESTRENGTH_3_PIN_26_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_27_OFFS 12
+#define GPIO_DRIVESTRENGTH_3_PIN_27_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_27(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_27_MASK) << GPIO_DRIVESTRENGTH_3_PIN_27_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_28_OFFS 16
+#define GPIO_DRIVESTRENGTH_3_PIN_28_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_28(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_28_MASK) << GPIO_DRIVESTRENGTH_3_PIN_28_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_29_OFFS 20
+#define GPIO_DRIVESTRENGTH_3_PIN_29_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_29(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_29_MASK) << GPIO_DRIVESTRENGTH_3_PIN_29_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_30_OFFS 24
+#define GPIO_DRIVESTRENGTH_3_PIN_30_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_30(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_30_MASK) << GPIO_DRIVESTRENGTH_3_PIN_30_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_31_OFFS 28
+#define GPIO_DRIVESTRENGTH_3_PIN_31_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_31(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_31_MASK) << GPIO_DRIVESTRENGTH_3_PIN_31_OFFS)
+
+#define GPIO_IE_OFFS 0
+#define GPIO_IE_MASK 0xffffffff
+#define GPIO_IE(V) ((V & GPIO_IE_MASK) << GPIO_IE_OFFS)
+
+#define GPIO_IP_OFFS 0
+#define GPIO_IP_MASK 0xffffffff
+#define GPIO_IP(V) ((V & GPIO_IP_MASK) << GPIO_IP_OFFS)
+
+#define GPIO_IRQ_TRIGGER_OFFS 0
+#define GPIO_IRQ_TRIGGER_MASK 0xffffffff
+#define GPIO_IRQ_TRIGGER(V) ((V & GPIO_IRQ_TRIGGER_MASK) << GPIO_IRQ_TRIGGER_OFFS)
+
+#define GPIO_IRQ_TYPE_OFFS 0
+#define GPIO_IRQ_TYPE_MASK 0xffffffff
+#define GPIO_IRQ_TYPE(V) ((V & GPIO_IRQ_TYPE_MASK) << GPIO_IRQ_TYPE_OFFS)
+
+#define GPIO_BOOT_SEL_OFFS 0
+#define GPIO_BOOT_SEL_MASK 0x7
+#define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS)
+
+//GPIO_VALUE
+inline uint32_t get_gpio_value(volatile gpio_t* reg){
+    return (reg->VALUE >> 0) & 0xffffffff;
+}
+
+//GPIO_WRITE
+inline uint32_t get_gpio_write(volatile gpio_t* reg){
+    return (reg->WRITE >> 0) & 0xffffffff;
+}
+inline void set_gpio_write(volatile gpio_t* reg, uint32_t value){
+    reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_WRITEENABLE
+inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg){
+    return (reg->WRITEENABLE >> 0) & 0xffffffff;
+}
+inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value){
+    reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_PULLUP
+inline uint32_t get_gpio_pullup(volatile gpio_t* reg){
+    return (reg->PULLUP >> 0) & 0xffffffff;
+}
+inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value){
+    reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_PULDOWN
+inline uint32_t get_gpio_puldown(volatile gpio_t* reg){
+    return (reg->PULDOWN >> 0) & 0xffffffff;
+}
+inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value){
+    reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_DRIVESTRENGTH_0
+inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg){
+     return reg->DRIVESTRENGTH_0;
+}
+inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value){
+     reg->DRIVESTRENGTH_0 = value;
+}
+inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 0) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 4) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 8) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 12) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 16) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 20) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 24) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 28) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28);
+}
+
+//GPIO_DRIVESTRENGTH_1
+inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg){
+     return reg->DRIVESTRENGTH_1;
+}
+inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value){
+     reg->DRIVESTRENGTH_1 = value;
+}
+inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 0) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 4) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 8) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 12) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 16) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 20) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 24) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 28) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28);
+}
+
+//GPIO_DRIVESTRENGTH_2
+inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg){
+     return reg->DRIVESTRENGTH_2;
+}
+inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value){
+     reg->DRIVESTRENGTH_2 = value;
+}
+inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 0) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 4) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 8) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 12) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 16) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 20) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 24) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 28) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28);
+}
+
+//GPIO_DRIVESTRENGTH_3
+inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg){
+     return reg->DRIVESTRENGTH_3;
+}
+inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value){
+     reg->DRIVESTRENGTH_3 = value;
+}
+inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 0) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 4) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 8) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 12) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 16) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 20) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 24) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 28) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28);
+}
+
+//GPIO_IE
+inline uint32_t get_gpio_ie(volatile gpio_t* reg){
+    return (reg->IE >> 0) & 0xffffffff;
+}
+inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value){
+    reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_IP
+inline uint32_t get_gpio_ip(volatile gpio_t* reg){
+    return (reg->IP >> 0) & 0xffffffff;
+}
+inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value){
+    reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_IRQ_TRIGGER
+inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg){
+    return (reg->IRQ_TRIGGER >> 0) & 0xffffffff;
+}
+inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value){
+    reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_IRQ_TYPE
+inline uint32_t get_gpio_irq_type(volatile gpio_t* reg){
+    return (reg->IRQ_TYPE >> 0) & 0xffffffff;
+}
+inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value){
+    reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_BOOT_SEL
+inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg){
+     return reg->BOOT_SEL;
+}
+inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg){
+    return (reg->BOOT_SEL >> 0) & 0x7;
+}
+
+#endif /* _BSP_GPIO_H */
--- a/include/ehrenberg/devices/gen/i2s.h
+++ b/include/ehrenberg/devices/gen/i2s.h
@@ -0,0 +1,270 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-12-28 11:01:24 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_I2S_H
+#define _BSP_I2S_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t LEFT_CH;
+    volatile uint32_t RIGHT_CH;
+    volatile uint32_t CONTROL;
+    volatile uint32_t STATUS;
+    volatile uint32_t I2S_CLOCK_CTRL;
+    volatile uint32_t PDM_CLOCK_CTRL;
+    volatile uint32_t PDM_FILTER_CTRL;
+    volatile uint32_t IE;
+    volatile uint32_t IP;
+}i2s_t;
+
+#define I2S_LEFT_CH_OFFS 0
+#define I2S_LEFT_CH_MASK 0xffffffff
+#define I2S_LEFT_CH(V) ((V & I2S_LEFT_CH_MASK) << I2S_LEFT_CH_OFFS)
+
+#define I2S_RIGHT_CH_OFFS 0
+#define I2S_RIGHT_CH_MASK 0xffffffff
+#define I2S_RIGHT_CH(V) ((V & I2S_RIGHT_CH_MASK) << I2S_RIGHT_CH_OFFS)
+
+#define I2S_CONTROL_MODE_OFFS 0
+#define I2S_CONTROL_MODE_MASK 0x3
+#define I2S_CONTROL_MODE(V) ((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS)
+
+#define I2S_CONTROL_DISABLE_LEFT_OFFS 2
+#define I2S_CONTROL_DISABLE_LEFT_MASK 0x1
+#define I2S_CONTROL_DISABLE_LEFT(V) ((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS)
+
+#define I2S_CONTROL_DISABLE_RIGHT_OFFS 3
+#define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1
+#define I2S_CONTROL_DISABLE_RIGHT(V) ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS)
+
+#define I2S_CONTROL_IS_MASTER_OFFS 4
+#define I2S_CONTROL_IS_MASTER_MASK 0x1
+#define I2S_CONTROL_IS_MASTER(V) ((V & I2S_CONTROL_IS_MASTER_MASK) << I2S_CONTROL_IS_MASTER_OFFS)
+
+#define I2S_CONTROL_SAMPLE_SIZE_OFFS 5
+#define I2S_CONTROL_SAMPLE_SIZE_MASK 0x3
+#define I2S_CONTROL_SAMPLE_SIZE(V) ((V & I2S_CONTROL_SAMPLE_SIZE_MASK) << I2S_CONTROL_SAMPLE_SIZE_OFFS)
+
+#define I2S_CONTROL_PDM_SCALE_OFFS 7
+#define I2S_CONTROL_PDM_SCALE_MASK 0x7
+#define I2S_CONTROL_PDM_SCALE(V) ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS)
+
+#define I2S_STATUS_ENABLED_OFFS 0
+#define I2S_STATUS_ENABLED_MASK 0x1
+#define I2S_STATUS_ENABLED(V) ((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS)
+
+#define I2S_STATUS_ACTIVE_OFFS 1
+#define I2S_STATUS_ACTIVE_MASK 0x1
+#define I2S_STATUS_ACTIVE(V) ((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS)
+
+#define I2S_STATUS_LEFT_AVAIL_OFFS 2
+#define I2S_STATUS_LEFT_AVAIL_MASK 0x1
+#define I2S_STATUS_LEFT_AVAIL(V) ((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS)
+
+#define I2S_STATUS_RIGHT_AVAIL_OFFS 3
+#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
+#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
+
+#define I2S_STATUS_LEFT_OVERFLOW_OFFS 4
+#define I2S_STATUS_LEFT_OVERFLOW_MASK 0x1
+#define I2S_STATUS_LEFT_OVERFLOW(V) ((V & I2S_STATUS_LEFT_OVERFLOW_MASK) << I2S_STATUS_LEFT_OVERFLOW_OFFS)
+
+#define I2S_STATUS_RIGHT_OVERFLOW_OFFS 5
+#define I2S_STATUS_RIGHT_OVERFLOW_MASK 0x1
+#define I2S_STATUS_RIGHT_OVERFLOW(V) ((V & I2S_STATUS_RIGHT_OVERFLOW_MASK) << I2S_STATUS_RIGHT_OVERFLOW_OFFS)
+
+#define I2S_I2S_CLOCK_CTRL_OFFS 0
+#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
+#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
+
+#define I2S_PDM_CLOCK_CTRL_OFFS 0
+#define I2S_PDM_CLOCK_CTRL_MASK 0xff
+#define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)
+
+#define I2S_PDM_FILTER_CTRL_OFFS 0
+#define I2S_PDM_FILTER_CTRL_MASK 0x3ff
+#define I2S_PDM_FILTER_CTRL(V) ((V & I2S_PDM_FILTER_CTRL_MASK) << I2S_PDM_FILTER_CTRL_OFFS)
+
+#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0
+#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS)
+
+#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS 1
+#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS)
+
+#define I2S_IP_LEFT_SAMPLE_AVAIL_OFFS 0
+#define I2S_IP_LEFT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IP_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS)
+
+#define I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS 1
+#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
+
+//I2S_LEFT_CH
+inline uint32_t get_i2s_left_ch(volatile i2s_t* reg){
+    return (reg->LEFT_CH >> 0) & 0xffffffff;
+}
+
+//I2S_RIGHT_CH
+inline uint32_t get_i2s_right_ch(volatile i2s_t* reg){
+    return (reg->RIGHT_CH >> 0) & 0xffffffff;
+}
+
+//I2S_CONTROL
+inline uint32_t get_i2s_control(volatile i2s_t* reg){
+     return reg->CONTROL;
+}
+inline void set_i2s_control(volatile i2s_t* reg, uint32_t value){
+     reg->CONTROL = value;
+}
+inline uint32_t get_i2s_control_mode(volatile i2s_t* reg){
+    return (reg->CONTROL >> 0) & 0x3;
+}
+inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg){
+    return (reg->CONTROL >> 2) & 0x1;
+}
+inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
+}
+inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg){
+    return (reg->CONTROL >> 3) & 0x1;
+}
+inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
+}
+inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg){
+    return (reg->CONTROL >> 4) & 0x1;
+}
+inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
+}
+inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg){
+    return (reg->CONTROL >> 5) & 0x3;
+}
+inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
+}
+inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg){
+    return (reg->CONTROL >> 7) & 0x7;
+}
+inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
+}
+
+//I2S_STATUS
+inline uint32_t get_i2s_status(volatile i2s_t* reg){
+     return reg->STATUS;
+}
+inline void set_i2s_status(volatile i2s_t* reg, uint32_t value){
+     reg->STATUS = value;
+}
+inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){
+    return (reg->STATUS >> 0) & 0x1;
+}
+inline uint32_t get_i2s_status_active(volatile i2s_t* reg){
+    return (reg->STATUS >> 1) & 0x1;
+}
+inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){
+    return (reg->STATUS >> 2) & 0x1;
+}
+inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
+    return (reg->STATUS >> 3) & 0x1;
+}
+inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg){
+    return (reg->STATUS >> 4) & 0x1;
+}
+inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value){
+    reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4);
+}
+inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg){
+    return (reg->STATUS >> 5) & 0x1;
+}
+inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value){
+    reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5);
+}
+
+//I2S_I2S_CLOCK_CTRL
+inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){
+     return reg->I2S_CLOCK_CTRL;
+}
+inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value){
+     reg->I2S_CLOCK_CTRL = value;
+}
+inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg){
+    return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
+}
+inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value){
+    reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
+}
+
+//I2S_PDM_CLOCK_CTRL
+inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg){
+     return reg->PDM_CLOCK_CTRL;
+}
+inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value){
+     reg->PDM_CLOCK_CTRL = value;
+}
+inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg){
+    return (reg->PDM_CLOCK_CTRL >> 0) & 0xff;
+}
+inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value){
+    reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0);
+}
+
+//I2S_PDM_FILTER_CTRL
+inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t* reg){
+     return reg->PDM_FILTER_CTRL;
+}
+inline void set_i2s_pdm_filter_ctrl(volatile i2s_t* reg, uint32_t value){
+     reg->PDM_FILTER_CTRL = value;
+}
+inline uint32_t get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg){
+    return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff;
+}
+inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg, uint16_t value){
+    reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0);
+}
+
+//I2S_IE
+inline uint32_t get_i2s_ie(volatile i2s_t* reg){
+     return reg->IE;
+}
+inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value){
+     reg->IE = value;
+}
+inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg){
+    return (reg->IE >> 0) & 0x1;
+}
+inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg){
+    return (reg->IE >> 1) & 0x1;
+}
+inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
+}
+
+//I2S_IP
+inline uint32_t get_i2s_ip(volatile i2s_t* reg){
+     return reg->IP;
+}
+inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg){
+    return (reg->IP >> 0) & 0x1;
+}
+inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg){
+    return (reg->IP >> 1) & 0x1;
+}
+
+#endif /* _BSP_I2S_H */
--- a/include/ehrenberg/devices/gen/mkcontrolclusterstreamcontroller.h
+++ b/include/ehrenberg/devices/gen/mkcontrolclusterstreamcontroller.h
@@ -0,0 +1,207 @@
+/*
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2025-02-18 11:11:47 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
+#define _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t REG_SEND;
+    volatile uint32_t REG_HEADER;
+    volatile uint32_t REG_ACK;
+    volatile uint32_t REG_RECV_ID;
+    volatile uint32_t REG_RECV_PAYLOAD;
+    uint8_t fill0[12];
+    volatile uint32_t REG_PAYLOAD_0;
+    volatile uint32_t REG_PAYLOAD_1;
+    volatile uint32_t REG_PAYLOAD_2;
+    volatile uint32_t REG_PAYLOAD_3;
+    volatile uint32_t REG_PAYLOAD_4;
+    volatile uint32_t REG_PAYLOAD_5;
+    volatile uint32_t REG_PAYLOAD_6;
+    volatile uint32_t REG_PAYLOAD_7;
+}mkcontrolclusterstreamcontroller_t;
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS 4
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS 1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS)
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND
+inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+     reg->REG_SEND = value;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg){
+     return reg->REG_HEADER;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+     reg->REG_HEADER = value;
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_HEADER >> 0) & 0xf;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_HEADER >> 4) & 0xf;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_HEADER >> 8) & 0x7;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_HEADER >> 11) & 0x3;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg){
+     return reg->REG_ACK;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+     reg->REG_ACK = value;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_ACK >> 1) & 0x1;
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
+     return reg->REG_RECV_ID;
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_RECV_ID >> 0) & 0xf;
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H */
--- a/include/ehrenberg/devices/gen/msgif.h
+++ b/include/ehrenberg/devices/gen/msgif.h
@@ -0,0 +1,197 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-11-20 11:54:52 UTC 
+* by peakrdl_mnrs version 1.2.7
+*/
+
+#ifndef _BSP_MSGIF_H
+#define _BSP_MSGIF_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t REG_SEND;
+    volatile uint32_t REG_HEADER;
+    volatile uint32_t REG_ACK;
+    volatile uint32_t REG_RECV_ID;
+    volatile uint32_t REG_RECV_PAYLOAD;
+    uint8_t fill0[12];
+    volatile uint32_t REG_PAYLOAD_0;
+    volatile uint32_t REG_PAYLOAD_1;
+    volatile uint32_t REG_PAYLOAD_2;
+    volatile uint32_t REG_PAYLOAD_3;
+    volatile uint32_t REG_PAYLOAD_4;
+    volatile uint32_t REG_PAYLOAD_5;
+    volatile uint32_t REG_PAYLOAD_6;
+    volatile uint32_t REG_PAYLOAD_7;
+}msgif_t;
+
+#define MSGIF_REG_SEND_OFFS 0
+#define MSGIF_REG_SEND_MASK 0x1
+#define MSGIF_REG_SEND(V) ((V & MSGIF_REG_SEND_MASK) << MSGIF_REG_SEND_OFFS)
+
+#define MSGIF_REG_HEADER_MESSAGE_ID_OFFS 0
+#define MSGIF_REG_HEADER_MESSAGE_ID_MASK 0xf
+#define MSGIF_REG_HEADER_MESSAGE_ID(V) ((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS)
+
+#define MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS 4
+#define MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
+#define MSGIF_REG_HEADER_MESSAGE_LENGTH(V) ((V & MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK) << MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS)
+
+#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
+#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
+#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
+
+#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
+#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
+#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
+
+#define MSGIF_REG_ACK_OFFS 0
+#define MSGIF_REG_ACK_MASK 0x1
+#define MSGIF_REG_ACK(V) ((V & MSGIF_REG_ACK_MASK) << MSGIF_REG_ACK_OFFS)
+
+#define MSGIF_REG_RECV_ID_OFFS 0
+#define MSGIF_REG_RECV_ID_MASK 0xf
+#define MSGIF_REG_RECV_ID(V) ((V & MSGIF_REG_RECV_ID_MASK) << MSGIF_REG_RECV_ID_OFFS)
+
+#define MSGIF_REG_RECV_PAYLOAD_OFFS 0
+#define MSGIF_REG_RECV_PAYLOAD_MASK 0xffffffff
+#define MSGIF_REG_RECV_PAYLOAD(V) ((V & MSGIF_REG_RECV_PAYLOAD_MASK) << MSGIF_REG_RECV_PAYLOAD_OFFS)
+
+#define MSGIF_REG_PAYLOAD_0_OFFS 0
+#define MSGIF_REG_PAYLOAD_0_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_0(V) ((V & MSGIF_REG_PAYLOAD_0_MASK) << MSGIF_REG_PAYLOAD_0_OFFS)
+
+#define MSGIF_REG_PAYLOAD_1_OFFS 0
+#define MSGIF_REG_PAYLOAD_1_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_1(V) ((V & MSGIF_REG_PAYLOAD_1_MASK) << MSGIF_REG_PAYLOAD_1_OFFS)
+
+#define MSGIF_REG_PAYLOAD_2_OFFS 0
+#define MSGIF_REG_PAYLOAD_2_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_2(V) ((V & MSGIF_REG_PAYLOAD_2_MASK) << MSGIF_REG_PAYLOAD_2_OFFS)
+
+#define MSGIF_REG_PAYLOAD_3_OFFS 0
+#define MSGIF_REG_PAYLOAD_3_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_3(V) ((V & MSGIF_REG_PAYLOAD_3_MASK) << MSGIF_REG_PAYLOAD_3_OFFS)
+
+#define MSGIF_REG_PAYLOAD_4_OFFS 0
+#define MSGIF_REG_PAYLOAD_4_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_4(V) ((V & MSGIF_REG_PAYLOAD_4_MASK) << MSGIF_REG_PAYLOAD_4_OFFS)
+
+#define MSGIF_REG_PAYLOAD_5_OFFS 0
+#define MSGIF_REG_PAYLOAD_5_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_5(V) ((V & MSGIF_REG_PAYLOAD_5_MASK) << MSGIF_REG_PAYLOAD_5_OFFS)
+
+#define MSGIF_REG_PAYLOAD_6_OFFS 0
+#define MSGIF_REG_PAYLOAD_6_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_6(V) ((V & MSGIF_REG_PAYLOAD_6_MASK) << MSGIF_REG_PAYLOAD_6_OFFS)
+
+#define MSGIF_REG_PAYLOAD_7_OFFS 0
+#define MSGIF_REG_PAYLOAD_7_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_7(V) ((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS)
+
+//MSGIF_REG_SEND
+inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value){
+     reg->REG_SEND = value;
+}
+inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value){
+    reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
+}
+
+//MSGIF_REG_HEADER
+inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg){
+     return reg->REG_HEADER;
+}
+inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value){
+     reg->REG_HEADER = value;
+}
+inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg){
+    return (reg->REG_HEADER >> 0) & 0xf;
+}
+inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
+}
+inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg){
+    return (reg->REG_HEADER >> 4) & 0xf;
+}
+inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
+}
+inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg){
+    return (reg->REG_HEADER >> 8) & 0x7;
+}
+inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg){
+    return (reg->REG_HEADER >> 11) & 0x3;
+}
+inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
+}
+
+//MSGIF_REG_ACK
+inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value){
+     reg->REG_ACK = value;
+}
+inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value){
+    reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
+}
+
+//MSGIF_REG_RECV_ID
+inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg){
+     return reg->REG_RECV_ID;
+}
+inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg){
+    return (reg->REG_RECV_ID >> 0) & 0xf;
+}
+
+//MSGIF_REG_RECV_PAYLOAD
+inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg){
+    return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
+}
+
+//MSGIF_REG_PAYLOAD_0
+inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_1
+inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_2
+inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_3
+inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_4
+inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_5
+inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_6
+inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_7
+inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_MSGIF_H */
--- a/include/ehrenberg/devices/gen/sysctrl.h
+++ b/include/ehrenberg/devices/gen/sysctrl.h
@@ -0,0 +1,122 @@
+/*
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2025-02-19 17:15:41 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_SYSCTRL_H
+#define _BSP_SYSCTRL_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t SYSCTRL;
+    volatile uint32_t PLLCTRL;
+    volatile uint32_t AXI_BACKUP;
+}sysctrl_t;
+
+#define SYSCTRL_SYSCTRL_CC0_RESET_OFFS 0
+#define SYSCTRL_SYSCTRL_CC0_RESET_MASK 0x3
+#define SYSCTRL_SYSCTRL_CC0_RESET(V) ((V & SYSCTRL_SYSCTRL_CC0_RESET_MASK) << SYSCTRL_SYSCTRL_CC0_RESET_OFFS)
+
+#define SYSCTRL_SYSCTRL_CC1_RESET_OFFS 2
+#define SYSCTRL_SYSCTRL_CC1_RESET_MASK 0x3
+#define SYSCTRL_SYSCTRL_CC1_RESET(V) ((V & SYSCTRL_SYSCTRL_CC1_RESET_MASK) << SYSCTRL_SYSCTRL_CC1_RESET_OFFS)
+
+#define SYSCTRL_SYSCTRL_MEM_RESET_OFFS 4
+#define SYSCTRL_SYSCTRL_MEM_RESET_MASK 0x1
+#define SYSCTRL_SYSCTRL_MEM_RESET(V) ((V & SYSCTRL_SYSCTRL_MEM_RESET_MASK) << SYSCTRL_SYSCTRL_MEM_RESET_OFFS)
+
+#define SYSCTRL_PLLCTRL_P_COUNTER_OFFS 0
+#define SYSCTRL_PLLCTRL_P_COUNTER_MASK 0x3f
+#define SYSCTRL_PLLCTRL_P_COUNTER(V) ((V & SYSCTRL_PLLCTRL_P_COUNTER_MASK) << SYSCTRL_PLLCTRL_P_COUNTER_OFFS)
+
+#define SYSCTRL_PLLCTRL_S_COUNTER_OFFS 6
+#define SYSCTRL_PLLCTRL_S_COUNTER_MASK 0x3
+#define SYSCTRL_PLLCTRL_S_COUNTER(V) ((V & SYSCTRL_PLLCTRL_S_COUNTER_MASK) << SYSCTRL_PLLCTRL_S_COUNTER_OFFS)
+
+#define SYSCTRL_PLLCTRL_CLK_SEL_OFFS 8
+#define SYSCTRL_PLLCTRL_CLK_SEL_MASK 0x3
+#define SYSCTRL_PLLCTRL_CLK_SEL(V) ((V & SYSCTRL_PLLCTRL_CLK_SEL_MASK) << SYSCTRL_PLLCTRL_CLK_SEL_OFFS)
+
+#define SYSCTRL_PLLCTRL_LOCKED_OFFS 31
+#define SYSCTRL_PLLCTRL_LOCKED_MASK 0x1
+#define SYSCTRL_PLLCTRL_LOCKED(V) ((V & SYSCTRL_PLLCTRL_LOCKED_MASK) << SYSCTRL_PLLCTRL_LOCKED_OFFS)
+
+#define SYSCTRL_AXI_BACKUP_OFFS 0
+#define SYSCTRL_AXI_BACKUP_MASK 0x1f
+#define SYSCTRL_AXI_BACKUP(V) ((V & SYSCTRL_AXI_BACKUP_MASK) << SYSCTRL_AXI_BACKUP_OFFS)
+
+//SYSCTRL_SYSCTRL
+inline uint32_t get_sysctrl_sysctrl(volatile sysctrl_t* reg){
+     return reg->SYSCTRL;
+}
+inline void set_sysctrl_sysctrl(volatile sysctrl_t* reg, uint32_t value){
+     reg->SYSCTRL = value;
+}
+inline uint32_t get_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg){
+    return (reg->SYSCTRL >> 0) & 0x3;
+}
+inline void set_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg, uint8_t value){
+    reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg){
+    return (reg->SYSCTRL >> 2) & 0x3;
+}
+inline void set_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg, uint8_t value){
+    reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 2)) | (value << 2);
+}
+inline uint32_t get_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg){
+    return (reg->SYSCTRL >> 4) & 0x1;
+}
+inline void set_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg, uint8_t value){
+    reg->SYSCTRL = (reg->SYSCTRL & ~(0x1U << 4)) | (value << 4);
+}
+
+//SYSCTRL_PLLCTRL
+inline uint32_t get_sysctrl_pllctrl(volatile sysctrl_t* reg){
+     return reg->PLLCTRL;
+}
+inline void set_sysctrl_pllctrl(volatile sysctrl_t* reg, uint32_t value){
+     reg->PLLCTRL = value;
+}
+inline uint32_t get_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg){
+    return (reg->PLLCTRL >> 0) & 0x3f;
+}
+inline void set_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg, uint8_t value){
+    reg->PLLCTRL = (reg->PLLCTRL & ~(0x3fU << 0)) | (value << 0);
+}
+inline uint32_t get_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg){
+    return (reg->PLLCTRL >> 6) & 0x3;
+}
+inline void set_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg, uint8_t value){
+    reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 6)) | (value << 6);
+}
+inline uint32_t get_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg){
+    return (reg->PLLCTRL >> 8) & 0x3;
+}
+inline void set_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg, uint8_t value){
+    reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 8)) | (value << 8);
+}
+inline uint32_t get_sysctrl_pllctrl_locked(volatile sysctrl_t* reg){
+    return (reg->PLLCTRL >> 31) & 0x1;
+}
+
+//SYSCTRL_AXI_BACKUP
+inline uint32_t get_sysctrl_axi_backup(volatile sysctrl_t* reg){
+     return reg->AXI_BACKUP;
+}
+inline void set_sysctrl_axi_backup(volatile sysctrl_t* reg, uint32_t value){
+     reg->AXI_BACKUP = value;
+}
+inline uint32_t get_sysctrl_axi_backup_page(volatile sysctrl_t* reg){
+    return (reg->AXI_BACKUP >> 0) & 0x1f;
+}
+inline void set_sysctrl_axi_backup_page(volatile sysctrl_t* reg, uint8_t value){
+    reg->AXI_BACKUP = (reg->AXI_BACKUP & ~(0x1fU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_SYSCTRL_H */
--- a/include/ehrenberg/devices/gen/timercounter.h
+++ b/include/ehrenberg/devices/gen/timercounter.h
@@ -0,0 +1,141 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-12-26 18:07:07 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_TIMERCOUNTER_H
+#define _BSP_TIMERCOUNTER_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t PRESCALER;
+    volatile uint32_t T0_CTRL;
+    volatile uint32_t T0_OVERFLOW;
+    volatile uint32_t T0_COUNTER;
+    volatile uint32_t T1_CTRL;
+    volatile uint32_t T1_OVERFLOW;
+    volatile uint32_t T1_COUNTER;
+}timercounter_t;
+
+#define TIMERCOUNTER_PRESCALER_OFFS 0
+#define TIMERCOUNTER_PRESCALER_MASK 0xffff
+#define TIMERCOUNTER_PRESCALER(V) ((V & TIMERCOUNTER_PRESCALER_MASK) << TIMERCOUNTER_PRESCALER_OFFS)
+
+#define TIMERCOUNTER_T0_CTRL_ENABLE_OFFS 0
+#define TIMERCOUNTER_T0_CTRL_ENABLE_MASK 0x7
+#define TIMERCOUNTER_T0_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T0_CTRL_ENABLE_MASK) << TIMERCOUNTER_T0_CTRL_ENABLE_OFFS)
+
+#define TIMERCOUNTER_T0_CTRL_CLEAR_OFFS 3
+#define TIMERCOUNTER_T0_CTRL_CLEAR_MASK 0x3
+#define TIMERCOUNTER_T0_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T0_CTRL_CLEAR_MASK) << TIMERCOUNTER_T0_CTRL_CLEAR_OFFS)
+
+#define TIMERCOUNTER_T0_OVERFLOW_OFFS 0
+#define TIMERCOUNTER_T0_OVERFLOW_MASK 0xffffffff
+#define TIMERCOUNTER_T0_OVERFLOW(V) ((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS)
+
+#define TIMERCOUNTER_T0_COUNTER_OFFS 0
+#define TIMERCOUNTER_T0_COUNTER_MASK 0xffffffff
+#define TIMERCOUNTER_T0_COUNTER(V) ((V & TIMERCOUNTER_T0_COUNTER_MASK) << TIMERCOUNTER_T0_COUNTER_OFFS)
+
+#define TIMERCOUNTER_T1_CTRL_ENABLE_OFFS 0
+#define TIMERCOUNTER_T1_CTRL_ENABLE_MASK 0x7
+#define TIMERCOUNTER_T1_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T1_CTRL_ENABLE_MASK) << TIMERCOUNTER_T1_CTRL_ENABLE_OFFS)
+
+#define TIMERCOUNTER_T1_CTRL_CLEAR_OFFS 3
+#define TIMERCOUNTER_T1_CTRL_CLEAR_MASK 0x3
+#define TIMERCOUNTER_T1_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T1_CTRL_CLEAR_MASK) << TIMERCOUNTER_T1_CTRL_CLEAR_OFFS)
+
+#define TIMERCOUNTER_T1_OVERFLOW_OFFS 0
+#define TIMERCOUNTER_T1_OVERFLOW_MASK 0xffffffff
+#define TIMERCOUNTER_T1_OVERFLOW(V) ((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS)
+
+#define TIMERCOUNTER_T1_COUNTER_OFFS 0
+#define TIMERCOUNTER_T1_COUNTER_MASK 0xffffffff
+#define TIMERCOUNTER_T1_COUNTER(V) ((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS)
+
+//TIMERCOUNTER_PRESCALER
+inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg){
+     return reg->PRESCALER;
+}
+inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value){
+     reg->PRESCALER = value;
+}
+inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg){
+    return (reg->PRESCALER >> 0) & 0xffff;
+}
+inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value){
+    reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
+}
+
+//TIMERCOUNTER_T0_CTRL
+inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg){
+     return reg->T0_CTRL;
+}
+inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value){
+     reg->T0_CTRL = value;
+}
+inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg){
+    return (reg->T0_CTRL >> 0) & 0x7;
+}
+inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
+    reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg){
+    return (reg->T0_CTRL >> 3) & 0x3;
+}
+inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
+    reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
+}
+
+//TIMERCOUNTER_T0_OVERFLOW
+inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg){
+    return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
+}
+inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value){
+    reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//TIMERCOUNTER_T0_COUNTER
+inline uint32_t get_timercounter_t0_counter(volatile timercounter_t* reg){
+    return (reg->T0_COUNTER >> 0) & 0xffffffff;
+}
+
+//TIMERCOUNTER_T1_CTRL
+inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg){
+     return reg->T1_CTRL;
+}
+inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value){
+     reg->T1_CTRL = value;
+}
+inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg){
+    return (reg->T1_CTRL >> 0) & 0x7;
+}
+inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
+    reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg){
+    return (reg->T1_CTRL >> 3) & 0x3;
+}
+inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
+    reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
+}
+
+//TIMERCOUNTER_T1_OVERFLOW
+inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg){
+    return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
+}
+inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value){
+    reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//TIMERCOUNTER_T1_COUNTER
+inline uint32_t get_timercounter_t1_counter(volatile timercounter_t* reg){
+    return (reg->T1_COUNTER >> 0) & 0xffffffff;
+}
+
+#endif /* _BSP_TIMERCOUNTER_H */
--- a/include/ehrenberg/devices/gen/uart.h
+++ b/include/ehrenberg/devices/gen/uart.h
@@ -0,0 +1,236 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-08-02 08:46:07 UTC 
+* by peakrdl_mnrs version 1.2.7
+*/
+
+#ifndef _BSP_UART_H
+#define _BSP_UART_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t RX_TX_REG;
+    volatile uint32_t INT_CTRL_REG;
+    volatile uint32_t CLK_DIVIDER_REG;
+    volatile uint32_t FRAME_CONFIG_REG;
+    volatile uint32_t STATUS_REG;
+}uart_t;
+
+#define UART_RX_TX_REG_DATA_OFFS 0
+#define UART_RX_TX_REG_DATA_MASK 0xff
+#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
+
+#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
+#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
+#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
+
+#define UART_RX_TX_REG_TX_FREE_OFFS 15
+#define UART_RX_TX_REG_TX_FREE_MASK 0x1
+#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
+
+#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
+#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
+#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
+
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2
+#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
+
+#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
+#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
+
+#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10
+#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS)
+
+#define UART_CLK_DIVIDER_REG_OFFS 0
+#define UART_CLK_DIVIDER_REG_MASK 0xfffff
+#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
+
+#define UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS 0
+#define UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK 0x7
+#define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS)
+
+#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
+#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
+#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
+
+#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
+#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
+#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
+
+#define UART_STATUS_REG_READ_ERROR_OFFS 0
+#define UART_STATUS_REG_READ_ERROR_MASK 0x1
+#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
+
+#define UART_STATUS_REG_STALL_OFFS 1
+#define UART_STATUS_REG_STALL_MASK 0x1
+#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
+
+#define UART_STATUS_REG_BREAK_LINE_OFFS 8
+#define UART_STATUS_REG_BREAK_LINE_MASK 0x1
+#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
+
+#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
+#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
+#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
+
+#define UART_STATUS_REG_SET_BREAK_OFFS 10
+#define UART_STATUS_REG_SET_BREAK_MASK 0x1
+#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
+
+#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
+#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
+#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
+
+//UART_RX_TX_REG
+inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg){
+     return reg->RX_TX_REG;
+}
+inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value){
+     reg->RX_TX_REG = value;
+}
+inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg){
+    return (reg->RX_TX_REG >> 0) & 0xff;
+}
+inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value){
+    reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
+}
+inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg){
+    return (reg->RX_TX_REG >> 14) & 0x1;
+}
+inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){
+    return (reg->RX_TX_REG >> 15) & 0x1;
+}
+inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg){
+    return (reg->RX_TX_REG >> 16) & 0x1;
+}
+
+//UART_INT_CTRL_REG
+inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){
+     return reg->INT_CTRL_REG;
+}
+inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value){
+     reg->INT_CTRL_REG = value;
+}
+inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 0) & 0x1;
+}
+inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 1) & 0x1;
+}
+inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
+}
+inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 2) & 0x1;
+}
+inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
+}
+inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 8) & 0x1;
+}
+inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 9) & 0x1;
+}
+inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 10) & 0x1;
+}
+
+//UART_CLK_DIVIDER_REG
+inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg){
+     return reg->CLK_DIVIDER_REG;
+}
+inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value){
+     reg->CLK_DIVIDER_REG = value;
+}
+inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg){
+    return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
+}
+inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value){
+    reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
+}
+
+//UART_FRAME_CONFIG_REG
+inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg){
+     return reg->FRAME_CONFIG_REG;
+}
+inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value){
+     reg->FRAME_CONFIG_REG = value;
+}
+inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg){
+    return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
+}
+inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value){
+    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg){
+    return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
+}
+inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value){
+    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
+}
+inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg){
+    return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
+}
+inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value){
+    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
+}
+
+//UART_STATUS_REG
+inline uint32_t get_uart_status_reg(volatile uart_t* reg){
+     return reg->STATUS_REG;
+}
+inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value){
+     reg->STATUS_REG = value;
+}
+inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 0) & 0x1;
+}
+inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 1) & 0x1;
+}
+inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 8) & 0x1;
+}
+inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 9) & 0x1;
+}
+inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value){
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
+}
+inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 10) & 0x1;
+}
+inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value){
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
+}
+inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 11) & 0x1;
+}
+inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value){
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
+}
+
+#endif /* _BSP_UART_H */
--- a/include/ehrenberg/devices/gpio.h
+++ b/include/ehrenberg/devices/gpio.h
@@ -1,14 +1,12 @@
-#ifndef _BSP_GPIO_H
-#define _BSP_GPIO_H
+#ifndef _DEVICES_GPIO_H
+#define _DEVICES_GPIO_H

 #include <stdint.h>
-#include "gen/Apb3Gpio.h"
+#include "gen/gpio.h"

-#define gpio_t apb3gpio_t
-
-inline void gpio_init(gpio_t* reg) {
+inline void gpio_init(volatile gpio_t* reg) {
    set_gpio_write(reg, 0);
    set_gpio_writeEnable(reg, 0);
 }

-#endif /* _BSP_GPIO_H */
+#endif /* _DEVICES_GPIO_H */
--- a/include/ehrenberg/devices/i2s.h
+++ b/include/ehrenberg/devices/i2s.h
@@ -0,0 +1,9 @@
+#ifndef _DEVICES_IIS_H
+#define _DEVICES_IIS_H
+
+#include "gen/i2s.h"
+
+#define MODE_I2S 1
+#define MODE_PDM 2
+
+#endif /* _DEVICES_IIS_H */
--- a/include/ehrenberg/devices/interrupt.h
+++ b/include/ehrenberg/devices/interrupt.h
@@ -1,14 +1,11 @@
-#ifndef _BSP_INTERRUPT_H
-#define _BSP_INTERRUPT_H
+#ifndef _DEVICES_INTERRUPT_H
+#define _DEVICES_INTERRUPT_H

 #include <stdint.h>
-#include "gen/Apb3IrqCtrl.h"

-#define irq_t apb3irqctrl_t
+#define irq_t void*

-inline void irq_init(irq_t* reg){
-    set_irq_masksReg(reg, 0);
-    set_irq_pendingsReg(reg, 0xff);
+inline void irq_init(volatile irq_t* reg){
 }

-#endif /* _BSP_INTERRUPT_H */
+#endif /* _DEVICES_INTERRUPT_H */
--- a/include/ehrenberg/devices/msg_if.h
+++ b/include/ehrenberg/devices/msg_if.h
@@ -0,0 +1,6 @@
+#ifndef _DEVICES_MSG_IF_H
+#define _DEVICES_MSG_IF_H
+
+#include "gen/mkcontrolclusterstreamcontroller.h"
+
+#endif /* _DEVICES_MSG_IF_H */
--- a/include/ehrenberg/devices/qspi.h
+++ b/include/ehrenberg/devices/qspi.h
@@ -1,10 +1,10 @@
-#ifndef _BSP_QSPI_H
-#define _BSP_QSPI_H
+#ifndef _DEVICES_QSPI_H
+#define _DEVICES_QSPI_H

 #include <stdint.h>
-#include "gen/Apb3SpiXdrMasterCtrl.h"
+#include "gen/apb3spi.h"

-#define qspi_t apb3spixdrmasterctrl_t
+#define qspi_t apb3spi_t
 typedef struct {
    uint32_t cpol;
    uint32_t cpha;
@@ -26,12 +26,12 @@ typedef struct {
 #define SPI_STATUS_CMD_INT_FLAG = (1 << 8)
 #define SPI_STATUS_RSP_INT_FLAG = (1 << 9)

-static inline void spi_configure(volatile qspi_t* reg, spi_cfg *config){
-    reg->CONFIG        = (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4);
-    reg->SCLK_CONFIG   = config->clkDivider;
-    reg->SSGEN_SETUP   = config->ssSetup;
-    reg->SSGEN_HOLD    = config->ssHold;
-    reg->SSGEN_DISABLE = config->ssDisable;
+static inline void spi_configure(volatile qspi_t* qspi, spi_cfg *config){
+    set_apb3spi_config(qspi, (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4));
+    set_apb3spi_sclk_config(qspi, config->clkDivider);
+    set_apb3spi_ssgen_setup(qspi, config->ssSetup);
+    set_apb3spi_ssgen_hold(qspi, config->ssHold);
+    set_apb3spi_ssgen_disable(qspi, config->ssDisable);
 }

 static inline void spi_init(volatile qspi_t* spi){
@@ -46,45 +46,37 @@ static inline void spi_init(volatile qspi_t* spi){
    spi_configure(spi, &spiCfg);
 }

-static inline uint32_t spi_cmd_avail(volatile qspi_t* reg){
-    return reg->STATUS & 0xFFFF;
+static inline uint32_t spi_cmd_avail(volatile qspi_t* qspi){
+    return qspi->STATUS & 0xFFFF;
 }
-static inline uint32_t spi_rsp_occupied(volatile qspi_t* reg){
-    return reg->STATUS >> 16;
+static inline uint32_t spi_rsp_occupied(volatile qspi_t* qspi){
+    return qspi->STATUS >> 16;
 }

-static inline void spi_write(volatile qspi_t* reg, uint8_t data){
-    while(spi_cmd_avail(reg) == 0);
-    reg->DATA = data | SPI_CMD_WRITE;
+static inline void spi_write(volatile qspi_t* qspi, uint8_t data){
+    while(spi_cmd_avail(qspi) == 0);
+    qspi->DATA = data | SPI_CMD_WRITE;
 }

-static inline uint8_t spi_write_read(volatile qspi_t* reg, uint8_t data){
-    while(spi_cmd_avail(reg) == 0);
-    reg->DATA = data | SPI_CMD_READ | SPI_CMD_WRITE;
-    while(spi_rsp_occupied(reg) == 0);
-    return reg->DATA;
+static inline uint8_t spi_read(volatile qspi_t* qspi){
+    while(spi_cmd_avail(qspi) == 0);
+    qspi->DATA = SPI_CMD_READ;
+    while(spi_rsp_occupied(qspi) == 0);
+    while((qspi->DATA & 0x80000000)==0);
+    return qspi->DATA;
 }

-
-static inline uint8_t spi_read(volatile qspi_t* reg){
-    while(spi_cmd_avail(reg) == 0);
-    reg->DATA = SPI_CMD_READ;
-    while(spi_rsp_occupied(reg) == 0);
-    while((reg->DATA & 0x80000000)==0);
-    return reg->DATA;
+static inline void spi_select(volatile qspi_t* qspi, uint32_t slaveId){
+    while(spi_cmd_avail(qspi) == 0);
+    qspi->DATA = slaveId | 0x80 | SPI_CMD_SS;
 }

-static inline void spi_select(volatile qspi_t* reg, uint32_t slaveId){
-    while(spi_cmd_avail(reg) == 0);
-    reg->DATA = slaveId | 0x80 | SPI_CMD_SS;
+static inline void spi_deselect(volatile qspi_t* qspi, uint32_t slaveId){
+    while(spi_cmd_avail(qspi) == 0);
+    qspi->DATA = slaveId | SPI_CMD_SS;
 }

-static inline void spi_deselect(volatile qspi_t* reg, uint32_t slaveId){
-    while(spi_cmd_avail(reg) == 0);
-    reg->DATA = slaveId | SPI_CMD_SS;
+static inline void spi_wait_tx_idle(volatile qspi_t* qspi){
+    while(spi_cmd_avail(qspi) < 0x20);
 }
-
-static inline void spi_wait_tx_idle(volatile qspi_t* reg){
-    while(spi_cmd_avail(reg) < 0x20);
-}
-#endif /* _BSP_QSPI_H */
+#endif /* _DEVICES_QSPI_H */
--- a/include/ehrenberg/devices/sysctrl.h
+++ b/include/ehrenberg/devices/sysctrl.h
@@ -0,0 +1,6 @@
+#ifndef _DEVICES_SYSCTRL_IF_H
+#define _DEVICES_SYSCTRL_IF_H
+
+#include "gen/sysctrl.h"
+
+#endif /* _DEVICES_sysctrl_IF_H */
--- a/include/ehrenberg/devices/timer.h
+++ b/include/ehrenberg/devices/timer.h
@@ -1,19 +1,19 @@
-#ifndef _BSP_TIMER_H
-#define _BSP_TIMER_H
+#ifndef _DEVICES_TIMER_H
+#define _DEVICES_TIMER_H

-#include "gen/Apb3Timer.h"
 #include <stdint.h>
+#include "gen/timercounter.h"

-inline void prescaler_init(apb3timer_t *reg, uint16_t value) {
-  set_timer_prescaler(reg, value);
+inline void prescaler_init(timercounter_t* reg, uint16_t value){
+    set_timercounter_prescaler(reg, value);
 }

-inline void timer_t0__init(apb3timer_t *reg) {
-  set_timer_t0_overflow(reg, 0xffffffff);
+inline void timer_t0__init(timercounter_t *reg){
+    set_timercounter_t0_overflow(reg, 0xffffffff);
 }

-inline void timer_t1__init(apb3timer_t *reg) {
-  set_timer_t1_overflow(reg, 0xffffffff);
+inline void timer_t1__init(timercounter_t *reg){
+    set_timercounter_t1_overflow(reg, 0xffffffff);
 }

-#endif /* _BSP_TIMER_H */
+#endif /* _DEVICES_TIMER_H */
--- a/include/ehrenberg/devices/uart.h
+++ b/include/ehrenberg/devices/uart.h
@@ -1,28 +1,30 @@
-#ifndef _BSP_UART_H
-#define _BSP_UART_H
+#ifndef _DEVICES_UART_H
+#define _DEVICES_UART_H

 #include <stdint.h>
-#include "gen/Apb3Uart.h"
+#include "gen/uart.h"

-#define uart_t apb3uart_t
-
-static inline uint32_t uart_get_tx_free(volatile uart_t *reg){
-    return (reg->STATUS_REG >> 16) & 0xFF;
+static inline uint32_t uart_get_tx_free(volatile uart_t* reg){
+    return get_uart_rx_tx_reg_tx_free(reg);
 }

-static inline uint32_t uart_get_rx_avail(volatile uart_t *reg){
-    return reg->STATUS_REG >> 24;
+static inline uint32_t uart_get_tx_empty(volatile uart_t* reg){
+    return get_uart_rx_tx_reg_tx_empty(reg);
 }

-static inline void uart_write(volatile uart_t *reg, uint8_t data){
+static inline uint32_t uart_get_rx_avail(volatile uart_t* reg){
+    return get_uart_rx_tx_reg_rx_avail(reg);
+}
+
+static inline void uart_write(volatile uart_t* reg, uint8_t data){
    while(get_uart_rx_tx_reg_tx_free(reg) == 0);
    set_uart_rx_tx_reg_data(reg, data);
 }

-static inline inline uint8_t uart_read(volatile uart_t *reg){
+static inline inline uint8_t uart_read(volatile uart_t* reg){
    uint32_t res = get_uart_rx_tx_reg_data(reg);
    while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
    return res;
 }

-#endif /* _BSP_UART_H */
+#endif /* _DEVICES_UART_H */
--- a/libwrap/CMakeLists.txt
+++ b/libwrap/CMakeLists.txt
@@ -0,0 +1,55 @@
+
+IF(NOT DEFINED _MK_LIBWRAP)
+
+SET(_MK_LIBWRAP TRUE)
+
+SET(LIBWRAP_DIR ${CMAKE_CURRENT_LIST_DIR})
+
+SET(LIBWRAP_SRCS
+    ${LIBWRAP_DIR}/stdlib/malloc.c
+    ${LIBWRAP_DIR}/sys/open.c
+    ${LIBWRAP_DIR}/sys/lseek.c
+    ${LIBWRAP_DIR}/sys/read.c
+    ${LIBWRAP_DIR}/sys/write.c
+    ${LIBWRAP_DIR}/sys/fstat.c
+    ${LIBWRAP_DIR}/sys/stat.c
+    ${LIBWRAP_DIR}/sys/close.c
+    ${LIBWRAP_DIR}/sys/link.c
+    ${LIBWRAP_DIR}/sys/unlink.c
+    ${LIBWRAP_DIR}/sys/execve.c
+    ${LIBWRAP_DIR}/sys/fork.c
+    ${LIBWRAP_DIR}/sys/getpid.c
+    ${LIBWRAP_DIR}/sys/kill.c
+    ${LIBWRAP_DIR}/sys/wait.c
+    ${LIBWRAP_DIR}/sys/isatty.c
+    ${LIBWRAP_DIR}/sys/times.c
+    ${LIBWRAP_DIR}/sys/sbrk.c
+    ${LIBWRAP_DIR}/sys/_exit.c
+    ${LIBWRAP_DIR}/misc/write_hex.c
+    ${LIBWRAP_DIR}/sys/printf.c
+    ${LIBWRAP_DIR}/sys/puts.c
+)
+IF(${SEMIHOSTING})
+    SET(LIBWRAP_SRCS ${LIBWRAP_SRCS} ${LIBWRAP_DIR}/semihosting/semihosting.c ${LIBWRAP_DIR}/semihosting/trap.c)
+ENDIF()
+
+SET(LIBWRAP_SYMS malloc free open lseek read write fstat stat close link unlink execve fork getpid jukk wait isatty times sbrk _exit printf puts)
+# Includes
+INCLUDE_DIRECTORIES(
+    ${LIBWRAP_DIR}
+    ${LIBWRAP_DIR}/../include
+    ${LIBWRAP_DIR}/../drivers
+    ${LIBWRAP_DIR}/../env
+    ${LIBWRAP_DIR}/../env/iss
+)
+
+ADD_LIBRARY(LIBWRAP_TGC STATIC ${LIBWRAP_SRCS})
+TARGET_COMPILE_OPTIONS(LIBWRAP_TGC PRIVATE -march=${RISCV_ARCH}_zicsr_zifencei -mabi=${RISCV_ABI} "-DBOARD_${BOARD}")
+
+FOREACH(SYM ${LIBWRAP_SYMS})
+    LIST(APPEND WRAP_LDFLAGS "-Wl,--wrap=${SYM}")
+ENDFOREACH()
+
+SET(LIBWRAP_TGC_LDFLAGS ${WRAP_LDFLAGS} "-Wl,--start-group" "-Wl,--end-group" "-L. -lLIBWRAP_TGC")
+
+ENDIF(NOT DEFINED _MK_LIBWRAP)
--- a/libwrap/semihosting/semihosting.c
+++ b/libwrap/semihosting/semihosting.c
@@ -0,0 +1,195 @@
+#include <stdarg.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+#include <sys/types.h>
+
+#include "semihosting.h"
+
+#define SEMIHOSTING_SYS_OPEN 0x01
+#define SEMIHOSTING_SYS_CLOSE 0x02
+#define SEMIHOSTING_SYS_WRITEC 0x03
+#define SEMIHOSTING_SYS_WRITE0 0x04
+#define SEMIHOSTING_SYS_WRITE 0x05
+#define SEMIHOSTING_SYS_READ 0x06
+#define SEMIHOSTING_SYS_READC 0x07
+#define SEMIHOSTING_SYS_ISERROR 0x08
+#define SEMIHOSTING_SYS_ISTTY 0x09
+#define SEMIHOSTING_SYS_SEEK 0x0A
+#define SEMIHOSTING_SYS_FLEN 0x0C
+#define SEMIHOSTING_SYS_TMPNAM 0x0D
+#define SEMIHOSTING_SYS_REMOVE 0x0E
+#define SEMIHOSTING_SYS_RENAME 0x0F
+#define SEMIHOSTING_SYS_CLOCK 0x10
+#define SEMIHOSTING_SYS_TIME 0x11
+#define SEMIHOSTING_SYS_SYSTEM 0x12
+#define SEMIHOSTING_SYS_ERRNO 0x13
+#define SEMIHOSTING_SYS_GET_CMDLINE 0x15
+#define SEMIHOSTING_SYS_HEAPINFO 0x16
+#define SEMIHOSTING_EnterSVC 0x17
+#define SEMIHOSTING_SYS_EXIT 0x18
+#define SEMIHOSTING_SYS_EXIT_EXTENDED 0x20
+#define SEMIHOSTING_SYS_ELAPSED 0x30
+#define SEMIHOSTING_SYS_TICKFREQ 0x31
+
+#define RISCV_SEMIHOSTING_CALL_NUMBER 7
+
+typedef struct {
+  char *str;
+  int mode;
+  size_t length;
+} OpenVector;
+
+typedef struct {
+  char *old;
+  int old_len;
+  char *new;
+  int new_len;
+} RenameVector;
+
+typedef struct {
+  char *path;
+  size_t len;
+} RemoveVector;
+
+typedef struct {
+  int fd;
+  off_t pos;
+} SeekVector;
+
+static inline int __attribute__((always_inline))
+call_host(int reason, void *arg) {
+#if 1
+  // This must always be set back to 0 to cover the case where a host wasn't
+  // initially present, but only connected while the program was already up and
+  // running. In that case, trap() suddenly won't be called anymore, so we have
+  // to clear this variable *before* EBREAK is called.
+  sh_missing_host = 0;
+
+  register int value asm("a0") = reason;
+  register void *ptr asm("a1") = arg;
+  asm volatile(
+      // Workaround for RISC-V lack of multiple EBREAKs.
+      " .option push \n"
+      " .option norvc \n"
+      // Force 16-byte alignment to make sure that the 3 instruction fall
+      // within the same virtual page. If you the instruction straddle a page
+      // boundary the debugger fetching the instructions could lead to a page
+      // fault. Note: align 4 means, align by 2 to the power of 4!
+      " .align 4 \n"
+      " slli x0, x0, 0x1f \n"
+      " ebreak \n"
+      " srai x0, x0, 0x07 \n"
+      " .option pop \n"
+
+      : "=r"(value) /* Outputs */
+      : "0"(value),
+        "r"(ptr), [swi] "i"(RISCV_SEMIHOSTING_CALL_NUMBER) /* Inputs */
+      : "memory"                                           /* Clobbers */
+  );
+  return value;
+#else
+  return 0;
+#endif
+}
+
+int sh_errno(void) { return call_host(SEMIHOSTING_SYS_ERRNO, (void *)NULL); }
+
+int sh_time(void) { return call_host(SEMIHOSTING_SYS_TIME, (void *)NULL); }
+
+int sh_remove(char *path) {
+  size_t len = strlen(path);
+  RemoveVector vec = {path, len};
+  return call_host(SEMIHOSTING_SYS_REMOVE, &vec);
+}
+
+void sh_seek(int file_handle, off_t pos) {
+  SeekVector vec = {file_handle, pos};
+  call_host(SEMIHOSTING_SYS_SEEK, &vec);
+  return;
+}
+
+void sh_write(char *str, int file_handle) {
+  size_t length = strlen(str);
+  OpenVector vec = {str, file_handle, length};
+  call_host(SEMIHOSTING_SYS_WRITE, &vec);
+  return;
+}
+
+int sh_close(int file_handle) {
+  return call_host(SEMIHOSTING_SYS_CLOSE, file_handle);
+}
+
+void sh_exit(void) {
+  call_host(SEMIHOSTING_SYS_EXIT, (void *)NULL);
+  return;
+}
+
+void sh_exit_extended(void) {
+  call_host(SEMIHOSTING_SYS_EXIT_EXTENDED, (void *)NULL);
+  return;
+}
+
+int sh_flen(int file_handle) {
+  return call_host(SEMIHOSTING_SYS_FLEN, file_handle);
+}
+
+int sh_iserror(int num) { return call_host(SEMIHOSTING_SYS_ISERROR, num); }
+
+int sh_istty(int file_handle) {
+  return call_host(SEMIHOSTING_SYS_ISTTY, file_handle);
+}
+/*
+int sh_remove(char* path) {
+    size_t len = strlen(path);
+    RemoveVector vec = {path, len};
+    return call_host(SEMIHOSTING_SYS_REMOVE, &vec);
+}*/
+
+void sh_rename(char *old, char *new) {
+  int old_len = strlen(old);
+  int new_len = strlen(new);
+  RenameVector vec = {old, old_len, new, new_len};
+  call_host(SEMIHOSTING_SYS_RENAME, &vec);
+  return;
+}
+
+void sh_write0(const char *buf) {
+  // Print zero-terminated string
+  call_host(SEMIHOSTING_SYS_WRITE0, (void *)buf);
+}
+
+void sh_writec(char c) {
+  // Print single character
+  call_host(SEMIHOSTING_SYS_WRITEC, (void *)&c);
+}
+
+char sh_readc(void) {
+  // Read character from keyboard. (Blocking operation!)
+  char c = call_host(SEMIHOSTING_SYS_READC, (void *)NULL);
+  return c;
+}
+
+int sh_open(char *str, int mode) {
+  // mode = 0;
+  // int length = 44;
+  size_t length = strlen(str);
+  OpenVector vec = {str, mode, length};
+  return call_host(SEMIHOSTING_SYS_OPEN, &vec);
+}
+
+int sh_read(char *buf, int file_handle, size_t length) {
+  OpenVector vec = {buf, file_handle, length};
+  int i = call_host(SEMIHOSTING_SYS_READ, &vec);
+  return i;
+}
+
+int sh_clock(void) {
+  int clock = call_host(SEMIHOSTING_SYS_CLOCK, (void *)NULL);
+  return clock;
+}
+
+/*
+void sh_write(char* str, int file_handle) {
+    return;
+}*/
--- a/libwrap/semihosting/semihosting.h
+++ b/libwrap/semihosting/semihosting.h
@@ -0,0 +1,31 @@
+#ifndef SEMIHOSTING_H
+#define SEMIHOSTING_H
+
+#include <sys/types.h>
+#include <unistd.h>
+// int32_t trace_write(const char* buf, uint32_t nbyte);
+
+void sh_seek(int, off_t);
+void sh_write0(const char *buf);
+void sh_writec(char c);
+char sh_readc(void);
+int sh_clock(void);
+int sh_read(char *, int, size_t);
+void sh_write(char *, int);
+int sh_open(char *, int);
+void sh_rename(char *, char *);
+int sh_remove(char *);
+int sh_istty(int);
+int sh_iserror(int);
+int sh_flen(int);
+void sh_exit(void);
+void sh_exit_extended(void);
+int sh_close(int);
+int sh_time(void);
+int sh_errno(void);
+
+int getchar(void);
+
+extern int sh_missing_host;
+
+#endif
--- a/libwrap/semihosting/trap.c
+++ b/libwrap/semihosting/trap.c
@@ -0,0 +1,60 @@
+#include <math.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "encoding.h"
+
+#if defined(SEMIHOSTING)
+#define EBREAK_OPCODE 0x00100073
+#define EBREAK_MCAUSE 0x00000003
+
+#define SLLI_X0_X0_0X1F_OPCODE 0x01f01013
+#define SRAI_X0_X0_0X07_OPCODE 0x40705013
+
+int sh_missing_host = 0;
+
+void trap() { // ToDo: Check why macro CSR_MEPC and others are not
+              // resolved
+  uint32_t mepc = read_csr(0x341);   // Address of trap
+  uint32_t mtval = read_csr(0x343);  // Instruction value of trap
+  uint32_t mcause = read_csr(0x342); // Reason for the trap
+
+  if (mcause == EBREAK_MCAUSE && mtval == EBREAK_OPCODE) {
+    // This trap was caused by an EBREAK...
+
+    int aligned = ((mepc - 4) & 0x0f) == 0;
+    if (aligned && *(uint32_t *)mepc == EBREAK_OPCODE &&
+        *(uint32_t *)(mepc - 4) == SLLI_X0_X0_0X1F_OPCODE &&
+        *(uint32_t *)(mepc + 4) == SRAI_X0_X0_0X07_OPCODE) {
+      // The EBREAK was part of the semihosting call. (See semihosting.c)
+      //
+      // If a debugger were connected, this would have resulted in a CPU halt,
+      // and the debugger would have serviced the the semihosting call.
+      //
+      // However, the semihosting function was called without a debugger being
+      // attached. The best course of action is to simply return from the trap
+      // and let the semihosting function continue after the call to EBREAK to
+      // prevent the CPU from hanging in the trap handler.
+      write_csr(mepc, mepc + 4);
+
+      // Set a global variable to tell the semihosting code the the semihosting
+      // call
+      // didn't execute on the host.
+      sh_missing_host = 1;
+
+      return;
+    }
+
+    // EBREAK was not part of a semihosting call. This should not have happened.
+    // Hang forever.
+    while (1)
+      ;
+  }
+
+  // Trap was issued for another reason than an EBREAK.
+  // Replace the code below with whatever trap handler you'd normally use. (e.g.
+  // interrupt processing.)
+  while (1)
+    ;
+}
+#endif
--- a/libwrap/sys/_exit.c
+++ b/libwrap/sys/_exit.c
@@ -1,8 +1,11 @@
 /* See LICENSE of license details. */

-#include <unistd.h>
 #include "platform.h"
 #include "weak_under_alias.h"
+#include <unistd.h>
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

 #if defined(BOARD_hifive1)
 static volatile uint32_t tohost;
@@ -14,17 +17,21 @@ extern volatile uint32_t fromhost;

 void write_hex(int fd, uint32_t hex);

-void __wrap_exit(int code)
-{
-//volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET);
+void __wrap_exit(int code) {
+  /*#if defined(SEMIHOSTING)
+    sh_exit();
+    return;
+  #endif*/
+  // volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET);
  const char message[] = "\nProgam has exited with code:";
-//*leds = (~(code));
+  //*leds = (~(code));

  write(STDERR_FILENO, message, sizeof(message) - 1);
  write_hex(STDERR_FILENO, code);
  write(STDERR_FILENO, "\n", 1);
-  tohost = code+1;
+  tohost = code + 1;
  write(STDERR_FILENO, "\x04", 1);
-  for (;;);
+  for (;;)
+    ;
 }
 weak_under_alias(exit);
--- a/libwrap/sys/close.c
+++ b/libwrap/sys/close.c
@@ -1,13 +1,18 @@
 /* See LICENSE of license details. */

-#include <errno.h>
 #include "stub.h"
 #include "weak_under_alias.h"
+#include <errno.h>
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

-int __wrap_close(int fd)
-{
+int __wrap_close(int fd) {
+#if defined(SEMIHOTING)
+  int i = sh_close(fd);
+  return i;
+#endif
  return _stub(EBADF);
 }

 weak_under_alias(close);
-
--- a/libwrap/sys/isatty.c
+++ b/libwrap/sys/isatty.c
@@ -1,10 +1,16 @@
 /* See LICENSE of license details. */

-#include <unistd.h>
 #include "weak_under_alias.h"
+#include <unistd.h>
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

-int __wrap_isatty(int fd)
-{
+int __wrap_isatty(int fd) {
+#if defined(SEMIHOSTING)
+  int i = sh_istty(fd);
+  return i;
+#endif
  if (fd == STDOUT_FILENO || fd == STDERR_FILENO)
    return 1;

--- a/libwrap/sys/lseek.c
+++ b/libwrap/sys/lseek.c
@@ -1,13 +1,21 @@
 /* See LICENSE of license details. */

-#include <errno.h>
-#include <unistd.h>
-#include <sys/types.h>
 #include "stub.h"
 #include "weak_under_alias.h"
+#include <errno.h>
+#include <sys/types.h>
+#include <unistd.h>
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

-off_t __wrap_lseek(int fd, off_t ptr, int dir)
-{
+off_t __wrap_lseek(int fd, off_t ptr, int dir) {
+#if defined(SEMIHOSTING)
+  if (sh_istty(fd))
+    return 0;
+  sh_seek(fd, ptr);
+  return ptr;
+#endif
  if (isatty(fd))
    return 0;

@@ -15,4 +23,3 @@ off_t __wrap_lseek(int fd, off_t ptr, int dir)
 }

 weak_under_alias(lseek);
-
--- a/libwrap/sys/open.c
+++ b/libwrap/sys/open.c
@@ -1,11 +1,17 @@
 /* See LICENSE of license details. */

-#include <errno.h>
 #include "stub.h"
 #include "weak_under_alias.h"
+#include <errno.h>
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

-int __wrap_open(const char* name, int flags, int mode)
-{
+int __wrap_open(const char *name, int flags, int mode) {
+#if defined(SEMIHOSTING)
+  int fd = sh_open(name, mode);
+  return fd;
+#endif
  return _stub(ENOENT);
 }
 weak_under_alias(open);
--- a/libwrap/sys/printf.c
+++ b/libwrap/sys/printf.c
@@ -3,59 +3,49 @@

 #include <stdarg.h>
 #include <stddef.h>
-#include <stdio.h>
 #include <stdint.h>
+#include <stdio.h>
 #include <string.h>
 #include <unistd.h>

 #undef putchar
-int putchar(int ch)
-{
-  return write(STDOUT_FILENO, &ch, 1) == 1 ? ch : -1;
-}
+int putchar(int ch) { return write(STDOUT_FILENO, &ch, 1) == 1 ? ch : -1; }

-size_t strnlen (const char *str, size_t n)
-{
+size_t strnlen(const char *str, size_t n) {
  const char *start = str;
-  while (n-- > 0 && *str) str++;
+  while (n-- > 0 && *str)
+    str++;
  return str - start;
 }

-static void fprintf_putch(int ch, void** data)
-{
-  putchar(ch);
-}
-static void sprintf_putch(int ch, void** data)
-{
-  char** pstr = (char**)data;
+static void fprintf_putch(int ch, void **data) { putchar(ch); }
+static void sprintf_putch(int ch, void **data) {
+  char **pstr = (char **)data;
  **pstr = ch;
  (*pstr)++;
 }

-static unsigned long getuint(va_list *ap, int lflag)
-{
+static unsigned long getuint(va_list *ap, int lflag) {
  if (lflag)
    return va_arg(*ap, unsigned long);
  else
    return va_arg(*ap, unsigned int);
 }

-static long getint(va_list *ap, int lflag)
-{
+static long getint(va_list *ap, int lflag) {
  if (lflag)
    return va_arg(*ap, long);
  else
    return va_arg(*ap, int);
 }

-static inline void printnum(void (*putch)(int, void**), void **putdat,
-                    unsigned long num, unsigned base, int width, int padc)
-{
-  unsigned digs[sizeof(num)*8];
+static inline void printnum(void (*putch)(int, void **), void **putdat,
+                            unsigned long num, unsigned base, int width,
+                            int padc) {
+  unsigned digs[sizeof(num) * 8];
  int pos = 0;

-  while (1)
-  {
+  while (1) {
    digs[pos++] = num % base;
    if (num < base)
      break;
@@ -69,9 +59,8 @@ static inline void printnum(void (*putch)(int, void**), void **putdat,
    putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat);
 }

-static inline void print_double(void (*putch)(int, void**), void **putdat,
-                                double num, int width, int prec)
-{
+static inline void print_double(void (*putch)(int, void **), void **putdat,
+                                double num, int width, int prec) {
  union {
    double d;
    uint64_t u;
@@ -87,30 +76,30 @@ static inline void print_double(void (*putch)(int, void**), void **putdat,
    u.d *= 10;

  char buf[32], *pbuf = buf;
-  printnum(sprintf_putch, (void**)&pbuf, (unsigned long)u.d, 10, 0, 0);
+  printnum(sprintf_putch, (void **)&pbuf, (unsigned long)u.d, 10, 0, 0);
  if (prec > 0) {
    for (int i = 0; i < prec; i++) {
-      pbuf[-i] = pbuf[-i-1];
+      pbuf[-i] = pbuf[-i - 1];
    }
    pbuf[-prec] = '.';
    pbuf++;
  }

-  for (char* p = buf; p < pbuf; p++)
+  for (char *p = buf; p < pbuf; p++)
    putch(*p, putdat);
 }

-static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap)
-{
-  register const char* p;
-  const char* last_fmt;
+static void vprintfmt(void (*putch)(int, void **), void **putdat,
+                      const char *fmt, va_list ap) {
+  register const char *p;
+  const char *last_fmt;
  register int ch;
  unsigned long num;
  int base, lflag, width, precision;
  char padc;

  while (1) {
-    while ((ch = *(const char *) fmt) != '%') {
+    while ((ch = *(const char *)fmt) != '%') {
      if (ch == '\0')
        return;
      fmt++;
@@ -125,13 +114,13 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
    precision = -1;
    lflag = 0;
  reswitch:
-    switch (ch = *(const char *) fmt++) {
+    switch (ch = *(const char *)fmt++) {

    // flag to pad on the right
    case '-':
      padc = '-';
      goto reswitch;
-      
+
    // flag to pad with 0's instead of spaces
    case '0':
      padc = '0';
@@ -147,7 +136,7 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
    case '7':
    case '8':
    case '9':
-      for (precision = 0; ; ++fmt) {
+      for (precision = 0;; ++fmt) {
        precision = precision * 10 + ch - '0';
        ch = *fmt;
        if (ch < '0' || ch > '9')
@@ -172,61 +161,62 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
        width = precision, precision = -1;
      goto reswitch;

-    case 'l':    // long flag
+    case 'l': // long flag
      if (lflag)
        goto bad;
      goto reswitch;
-    case 'c':    // character
+    case 'c': // character
      putch(va_arg(ap, int), putdat);
      break;
-    case 'f':    // double
+    case 'f': // double
      print_double(putch, putdat, va_arg(ap, double), width, precision);
      break;
-    case 's':    // string
+    case 's': // string
      if ((p = va_arg(ap, char *)) == NULL)
        p = "(null)";
      if (width > 0 && padc != '-')
        for (width -= strnlen(p, precision); width > 0; width--)
          putch(padc, putdat);
-      for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) {
+      for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0);
+           width--) {
        putch(ch, putdat);
        p++;
      }
      for (; width > 0; width--)
        putch(' ', putdat);
      break;
-    case 'd':    // (signed) decimal
+    case 'd': // (signed) decimal
      num = getint(&ap, lflag);
-      if ((long) num < 0) {
+      if ((long)num < 0) {
        putch('-', putdat);
-        num = -(long) num;
+        num = -(long)num;
      }
      base = 10;
      goto signed_number;
-    case 'u':    // unsigned decimal
+    case 'u': // unsigned decimal
      base = 10;
      goto unsigned_number;
    case 'o': // (unsigned) octal
      // should do something with padding so it's always 3 octits
      base = 8;
      goto unsigned_number;
-    case 'p':// pointer
+    case 'p': // pointer
      lflag = 1;
      putch('0', putdat);
      putch('x', putdat);
      /* fall through to 'x' */
      __attribute__((fallthrough));
-    case 'x':    // (unsigned) hexadecimal
+    case 'x': // (unsigned) hexadecimal
      base = 16;
-      unsigned_number:
+    unsigned_number:
      num = getuint(&ap, lflag);
-      signed_number:
+    signed_number:
      printnum(putch, putdat, num, base, width, padc);
      break;
-    case '%':    // escaped '%' character
+    case '%': // escaped '%' character
      putch(ch, putdat);
      break;
-    default:    // unrecognized escape sequence - just print it literally
+    default: // unrecognized escape sequence - just print it literally
    bad:
      putch('%', putdat);
      fmt = last_fmt;
@@ -235,8 +225,7 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
  }
 }

-int __wrap_printf(const char* fmt, ...)
-{
+int __wrap_printf(const char *fmt, ...) {
  va_list ap;
  va_start(ap, fmt);

@@ -246,13 +235,12 @@ int __wrap_printf(const char* fmt, ...)
  return 0; // incorrect return value, but who cares, anyway?
 }

-int __wrap_sprintf(char* str, const char* fmt, ...)
-{
+int __wrap_sprintf(char *str, const char *fmt, ...) {
  va_list ap;
-  char* str0 = str;
+  char *str0 = str;
  va_start(ap, fmt);

-  vprintfmt(sprintf_putch, (void**)&str, fmt, ap);
+  vprintfmt(sprintf_putch, (void **)&str, fmt, ap);
  *str = 0;

  va_end(ap);
--- a/libwrap/sys/puts.c
+++ b/libwrap/sys/puts.c
@@ -8,8 +8,15 @@
 #include "platform.h"
 #include "stub.h"
 #include "weak_under_alias.h"
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

 int __wrap_puts(const char *s) {
+#if defined(SEMIHOSTING)
+  sh_write0(s);
+  return 0;
+#endif
  while (*s != '\0') {
 #if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
    while (get_uart_rx_tx_reg_tx_free(uart) == 0)
--- a/libwrap/sys/read.c
+++ b/libwrap/sys/read.c
@@ -1,15 +1,23 @@
 /* See LICENSE of license details. */

-#include "platform.h"
-#include "stub.h"
-#include "weak_under_alias.h"
 #include <errno.h>
 #include <stdint.h>
 #include <sys/types.h>
 #include <unistd.h>

+#include "platform.h"
+#include "stub.h"
+#include "weak_under_alias.h"
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif
+
 ssize_t __wrap_read(int fd, void *ptr, size_t len) {
  uint8_t *current = (uint8_t *)ptr;
+#if defined(SEMIHOSTING)
+  int i = sh_read(current, fd, len);
+  return i;
+#endif
 #if defined(BOARD_hifive1)
  volatile uint32_t *uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
  volatile uint8_t *uart_rx_cnt =
--- a/libwrap/sys/unlink.c
+++ b/libwrap/sys/unlink.c
@@ -1,11 +1,16 @@
 /* See LICENSE of license details. */

-#include <errno.h>
 #include "stub.h"
 #include "weak_under_alias.h"
+#include <errno.h>
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif

-int __wrap_unlink(const char* name)
-{
+int __wrap_unlink(const char *name) {
+#if defined(SEMIHOSTING)
+  return sh_remove(name);
+#endif
  return _stub(ENOENT);
 }
 weak_under_alias(unlink);
--- a/libwrap/sys/write.c
+++ b/libwrap/sys/write.c
@@ -8,8 +8,24 @@
 #include "platform.h"
 #include "stub.h"
 #include "weak_under_alias.h"
+#if defined(SEMIHOSTING)
+#include "semihosting.h"
+#endif
+
 ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
  const uint8_t *current = (const uint8_t *)ptr;
+#if defined(SEMIHOSTING)
+  if (isatty(fd)) {
+    for (size_t jj = 0; jj < len; jj++) {
+      sh_writec(current[jj]);
+    }
+    return len;
+  } else {
+    sh_write(current, fd);
+    return len;
+  }
+  // return len;
+#endif
  if (isatty(fd)) {
    for (size_t jj = 0; jj < len; jj++) {
 #if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
Author	SHA1	Message	Date
Eyck Jentzsch	428d3ac285	fixes linker script	2025-03-06 11:24:43 +01:00
mihir	141a4ed247	sysctrl.h added	2025-03-05 09:59:33 +01:00
Florian Kriebel	19e7a3e85e	adapts to changed field layout in config registers of the camera module	2025-03-03 11:05:04 +01:00
stas	e372f59715	update camera interface	2025-02-26 17:10:46 +01:00
Johannes Wirth	b34365534c	Add header library with cluster config information	2025-02-24 17:05:51 +01:00
Eyck Jentzsch	06cbc26688	fixes memory layout of moonlight	2025-02-24 10:14:10 +01:00
Eyck Jentzsch	25623e74a0	fixes memory layout wrt to latest changes	2025-02-23 08:08:34 +01:00
Eyck Jentzsch	2231ae4106	updates sysctrl register declarations	2025-02-19 17:17:04 +01:00
Eyck Jentzsch	c37b7243b4	adds sysctrl peripheral	2025-02-19 16:27:01 +01:00
Johannes Wirth	42a696bebd	fix case in header library	2025-02-18 12:13:44 +01:00
Johannes Wirth	08846df05e	Merge branch 'develop' of https://git.minres.com/Firmware/MNRS-BM-BSP into develop	2025-02-18 11:36:09 +01:00
Eyck Jentzsch	669c85afa2	updates bsp based on RDL changes	2025-02-18 11:15:18 +01:00
Johannes Wirth	db3ff44066	add basic library for flexki messaging	2025-02-18 09:54:19 +01:00
stas	a9aa746f81	add StreamController pending irq register	2025-02-17 15:59:33 +01:00
Eyck Jentzsch	bfc7e9f00b	adds missing peripheral header files	2025-02-12 08:58:43 +01:00
Eyck Jentzsch	fcf8543c06	corrects UART base addr wrt. HW	2025-01-21 17:35:12 +01:00
stas	74b43d9bc1	add linker file for camera test	2025-01-21 10:16:24 +01:00
Eyck Jentzsch	71217499f2	fixes changed base addresses	2025-01-19 20:12:35 +01:00
Eyck Jentzsch	b921b9c71f	fixes moonlight/ehrenberg ram size	2025-01-14 20:41:26 +01:00
Eyck Jentzsch	9770c7b86c	updates I2S registers adding fifo overflow status (#624 )	2024-12-28 11:03:49 +01:00
Eyck Jentzsch	deba022043	updates timer and i2s register names	2024-12-28 10:05:13 +01:00
stas	7a3360d072	update SPI register interface	2024-12-09 12:09:22 +01:00
stas	097765d92b	update GPIO regs	2024-12-06 10:10:02 +01:00
stas	bd02644a2f	fix readout datasize connection	2024-11-27 09:42:43 +01:00
stas	800dd52519	update camera module	2024-11-27 09:02:20 +01:00
stas	7fc7e97fe3	CCC msg if update	2024-11-20 13:05:43 +01:00
stas	5eac63d773	fix timer macro	2024-11-06 11:24:09 +01:00
stas	e8cfbbdab0	add communication controller register interface	2024-11-05 13:01:57 +01:00
stas	8e62de5cdf	add RAM linker file	2024-10-01 10:56:40 +02:00
stas	3484dc66e3	fix interrupt handler and Moonlight ROM size	2024-09-26 12:18:50 +02:00
Eyck Jentzsch	ea5d61ec0b	adds some cosmetic fixes	2024-09-14 09:58:57 +02:00
stas	b36a42b386	update moonlight register headers. Remove unused control register in camera	2024-09-10 15:46:32 +02:00
stas	f632436fda	rename SDMA to DMA	2024-08-28 16:18:18 +02:00
Eyck Jentzsch	7a065a1d24	adds non-vectored interrupt handler	2024-08-23 21:56:15 +02:00
Eyck Jentzsch	ac3ef788f9	fixes naming in qspi header	2024-08-18 20:27:41 +02:00
Eyck Jentzsch	a00e57a8d2	does some cleanup	2024-08-11 17:30:16 +02:00
Eyck Jentzsch	5d78f839a5	removes attribute packed as it disables word access generation by gcc	2024-08-11 17:29:43 +02:00
Eyck Jentzsch	46d55f353e	adds signature to start of firmware	2024-08-11 17:29:13 +02:00
Eyck Jentzsch	d621264ef7	updates gpio registers	2024-08-09 14:20:00 +02:00
Eyck Jentzsch	785cf20e8e	fixes include guards	2024-08-04 13:27:53 +02:00
stas	85ae6c1c59	simpledma renamed to dma	2024-08-02 12:36:38 +02:00
stas	2e98acdeb2	Ehrenberg firmware headers generated with peakrdl 1.2.8	2024-08-02 09:55:38 +02:00
Eyck Jentzsch	79a245b7f2	updates Ehrenberg device files	2024-07-16 16:22:42 +02:00
Eyck Jentzsch	1f4b4d2bb9	updates ehrenberg dma device to support dual channel	2024-07-11 22:36:41 +02:00
Eyck Jentzsch	9d607e932a	updates BSP definitions for Ehrenberg	2024-07-01 11:41:28 +02:00
Eyck Jentzsch	daa1ed184d	adds missing ehrenberg devices	2024-06-10 12:21:20 +02:00
Eyck Jentzsch	231366cc94	updates ehrenberg devices and BSP	2024-06-10 10:13:07 +02:00
gabriel	c94eb7c61a	update include path	2024-05-31 09:21:57 +02:00
gabriel	9407d2cec5	Merge branch 'develop' of https://git.minres.com/Firmware/MNRS-BM-BSP into develop	2024-05-31 08:58:05 +02:00
gabriel	092f0fdfd3	update include paths	2024-05-31 08:56:21 +02:00
Eyck Jentzsch	05062c5be4	updates Ehrenberg register description	2024-05-30 18:33:53 +02:00
Eyck Jentzsch	442384574b	Merge branch 'develop' of https://git.minres.com/Firmware/MNRS-BM-BSP.git into develop	2024-05-30 18:33:35 +02:00
gabriel	ff8b3bb39c	merge semihosting and bsp	2024-04-30 08:56:57 +02:00
gabriel	9aaf428620	further semihosting support	2024-04-30 08:48:44 +02:00
gabriel	e83f7996bc	Adding semihosting support for bmsp	2024-04-08 14:36:22 +02:00
gabriel	39ee91af7d	first semihosting integration	2024-02-26 20:41:15 +01:00