fixes linker script

env/ehrenberg/camera.lds

@@ -0,0 +1,167 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  rom (rxai!w) : ORIGIN = 0x80000000, LENGTH = 16k
+  ram (wxa!ri) : ORIGIN = 0x80004000, LENGTH = 112k
+}
+
+PHDRS
+{
+  rom PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+  .init ORIGIN(rom)        :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >rom AT>rom :rom
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >rom AT>rom :rom
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >rom AT>rom :rom
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >rom AT>rom :rom
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >rom AT>rom :rom
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >rom AT>rom :rom
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >rom AT>rom :rom
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >rom AT>rom :rom
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >rom AT>rom :rom
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >rom AT>rom :rom
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>rom :ram_init
+
+  .data          :
+  {
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+  } >ram AT>rom :ram_init
+
+  .srodata        :
+  {
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>rom :ram_init
+
+  .sdata          :
+  {
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>rom :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+}

env/ehrenberg/link.lds

@@ -4,10 +4,10 @@ ENTRY( _start )
 
 MEMORY
 {
-  rom   (rxai!w) : ORIGIN = 0xFFFFE000, LENGTH = 4k
-  flash (rxai!w) : ORIGIN = 0xE0000000, LENGTH = 4M
-  ram (wxa!ri) :   ORIGIN = 0x80000000, LENGTH = 32K
-  dram (wxa!ri) :  ORIGIN = 0x00000000, LENGTH = 256M
+  rom   (rxai!w) : ORIGIN = 0xFFFFE000, LENGTH = 2k
+  flash (rxai!w) : ORIGIN = 0xE0000000, LENGTH = 16M
+  ram   (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 128K
+  dram  (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 2048M
 }
 
 PHDRS
@@ -107,6 +107,11 @@ SECTIONS
     KEEP (*(.dtors))
   } >flash AT>flash :flash
 
+  .dummy          :
+  {
+	*(.comment.*)
+
+  }
   .lalign         :
   {
     . = ALIGN(4);

env/ehrenberg/platform.h

@@ -4,40 +4,43 @@
 #define _ISS_PLATFORM_H
 
 #if __riscv_xlen == 32
-#define MCAUSE_INT         0x80000000UL
-#define MCAUSE_CAUSE       0x000003FFUL
+#define MCAUSE_INT 0x80000000UL
+#define MCAUSE_CAUSE 0x000003FFUL
 #else
-#define MCAUSE_INT         0x8000000000000000UL
-#define MCAUSE_CAUSE       0x00000000000003FFUL
+#define MCAUSE_INT 0x8000000000000000UL
+#define MCAUSE_CAUSE 0x00000000000003FFUL
 #endif
 
 #define APB_BUS
 
-#include "ehrenberg/devices/gpio.h"
-#include "ehrenberg/devices/uart.h"
-#include "ehrenberg/devices/timer.h"
 #include "ehrenberg/devices/aclint.h"
-#include "ehrenberg/devices/qspi.h"
-#include "ehrenberg/devices/i2s.h"
 #include "ehrenberg/devices/camera.h"
 #include "ehrenberg/devices/dma.h"
+#include "ehrenberg/devices/gen/sysctrl.h"
+#include "ehrenberg/devices/gpio.h"
+#include "ehrenberg/devices/i2s.h"
 #include "ehrenberg/devices/msg_if.h"
+#include "ehrenberg/devices/qspi.h"
+#include "ehrenberg/devices/timer.h"
+#include "ehrenberg/devices/uart.h"
 
-#define PERIPH(TYPE, ADDR) ((volatile TYPE*) (ADDR))
+#define PERIPH(TYPE, ADDR) ((volatile TYPE *)(ADDR))
 
 #define APB_BASE 0xF0000000
 
-#define gpio        PERIPH(gpio_t,         APB_BASE+0x0000)
-#define uart        PERIPH(uart_t,         APB_BASE+0x1000)
-#define timer       PERIPH(timercounter_t, APB_BASE+0x20000)
-#define aclint      PERIPH(aclint_t,       APB_BASE+0x30000)
-#define irq         PERIPH(irq_t,          APB_BASE+0x40000)
-#define qspi        PERIPH(qspi_t,         APB_BASE+0x50000)
-#define i2s         PERIPH(i2s_t,          APB_BASE+0x90000)
-#define camera      PERIPH(camera_t,       APB_BASE+0xA0000)
-#define dma         PERIPH(dma_t,          APB_BASE+0xB0000)
-#define msgif       PERIPH(msgif_t,        APB_BASE+0xC0000)
+#define gpio PERIPH(gpio_t, APB_BASE + 0x0000)
+#define uart PERIPH(uart_t, APB_BASE + 0x01000)
+#define timer PERIPH(timercounter_t, APB_BASE + 0x20000)
+#define aclint PERIPH(aclint_t, APB_BASE + 0x30000)
+#define sysctrl PERIPH(sysctrl_t, APB_BASE + 0x40000)
+#define qspi PERIPH(qspi_t, APB_BASE + 0x50000)
+#define i2s PERIPH(i2s_t, APB_BASE + 0x90000)
+#define camera PERIPH(camera_t, APB_BASE + 0xA0000)
+#define dma PERIPH(dma_t, APB_BASE + 0xB0000)
+#define msgif PERIPH(mkcontrolclusterstreamcontroller_t, APB_BASE + 0xC0000)
 
+#include "ehrenberg/devices/flexki_messages.h"
+#include "ehrenberg/devices/fki_cluster_info.h"
 
 #define XIP_START_LOC 0xE0040000
 #define RAM_START_LOC 0x80000000

env/ehrenberg/ram.lds

@@ -4,8 +4,8 @@ ENTRY( _start )
 
 MEMORY
 {
-  rom (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128k
-  ram (wxa!ri) : ORIGIN = 0x80004000, LENGTH = 128k
+  rom (rxai!w) : ORIGIN = 0xC0000000, LENGTH = 64k
+  ram (wxa!ri) : ORIGIN = 0xC0010000, LENGTH = 64k
 }
 
 PHDRS

env/ehrenberg/rom.lds

@@ -5,7 +5,7 @@ ENTRY( _start )
 MEMORY
 {
   rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 4k
-  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32k
+  ram (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 32k
 }
 
 PHDRS

include/ehrenberg/devices/fki_cluster_info.h

@@ -0,0 +1,316 @@
+#pragma once
+#ifndef _FKI_CLUSTER_INFO_H
+#define _FKI_CLUSTER_INFO_H
+
+
+static uint8_t fki_ccc(uint8_t cluster);
+static uint8_t fki_dma(uint8_t cluster);
+static uint8_t fki_axi2stream(uint8_t cluster);
+static uint8_t fki_stream2axi(uint8_t cluster);
+static uint8_t fki_dma_adapter(uint8_t cluster);
+static uint64_t fki_addr_ccc_peMapping(uint8_t cluster);
+static uint64_t fki_addr_sram1(uint8_t cluster);
+static uint64_t fki_addr_ccc_configMem(uint8_t cluster);
+static uint64_t fki_addr_sram2(uint8_t cluster);
+static uint64_t fki_addr_cntrl_cva5(uint8_t cluster);
+static uint64_t fki_addr_cntrl_tgc(uint8_t cluster);
+static uint64_t fki_addr_ccc_idxTasks(uint8_t cluster);
+static uint64_t fki_addr_ccc_idxJobs(uint8_t cluster);
+static uint64_t fki_addr_aes_adapter(uint8_t cluster);
+static uint64_t fki_addr_ut_adapter(uint8_t cluster);
+static uint64_t fki_addr_sram0(uint8_t cluster);
+static uint64_t fki_addr_sram3(uint8_t cluster);
+static uint64_t fki_addr_hide_adapter(uint8_t cluster);
+
+#define Compute0 2
+#define Compute0_ccc 2,0
+#define Compute0_stream2axi 2,1
+#define Compute0_axi2stream 2,2
+#define Compute0_dma 2,4
+#define Compute0_dma_adapter 2,5
+#define ADDR_Compute0_ccc_idxJobs 0x80004000
+#define ADDR_Compute0_ccc_idxTasks 0x80005000
+#define ADDR_Compute0_ccc_configMem 0x80000000
+#define ADDR_Compute0_ccc_peMapping 0x80006000
+#define ADDR_Compute0_aes_adapter 0x80007000
+#define ADDR_Compute0_hide_adapter 0x80008000
+#define ADDR_Compute0_cntrl_cva5 0x80009000
+#define ADDR_Compute0_cntrl_tgc 0x8000a000
+#define ADDR_Compute0_ut_adapter 0x8000b000
+#define ADDR_Compute0_sram0 0x8000c000
+#define ADDR_Compute0_sram1 0x8010c000
+#define ADDR_Compute0_sram2 0x8018c000
+#define ADDR_Compute0_sram3 0x8020c000
+#define Compute1 3
+#define Compute1_ccc 3,0
+#define Compute1_stream2axi 3,1
+#define Compute1_axi2stream 3,2
+#define Compute1_dma 3,4
+#define Compute1_dma_adapter 3,5
+#define ADDR_Compute1_ccc_idxJobs 0x90004000
+#define ADDR_Compute1_ccc_idxTasks 0x90005000
+#define ADDR_Compute1_ccc_configMem 0x90000000
+#define ADDR_Compute1_ccc_peMapping 0x90006000
+#define ADDR_Compute1_aes_adapter 0x90007000
+#define ADDR_Compute1_hide_adapter 0x90008000
+#define ADDR_Compute1_cntrl_cva5 0x90009000
+#define ADDR_Compute1_cntrl_tgc 0x9000a000
+#define ADDR_Compute1_ut_adapter 0x9000b000
+#define ADDR_Compute1_sram0 0x9000c000
+#define ADDR_Compute1_sram1 0x9010c000
+#define ADDR_Compute1_sram2 0x9018c000
+#define ADDR_Compute1_sram3 0x9020c000
+
+static uint8_t fki_ccc(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0;
+		}
+		case 3: {
+			return 0;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_dma(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 4;
+		}
+		case 2: {
+			return 4;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_axi2stream(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 2;
+		}
+		case 2: {
+			return 2;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_stream2axi(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 1;
+		}
+		case 2: {
+			return 1;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_dma_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 5;
+		}
+		case 3: {
+			return 5;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_ccc_peMapping(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80006000;
+		}
+		case 3: {
+			return 0x90006000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_sram1(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x9010c000;
+		}
+		case 2: {
+			return 0x8010c000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_ccc_configMem(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x90000000;
+		}
+		case 2: {
+			return 0x80000000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_sram2(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x8018c000;
+		}
+		case 3: {
+			return 0x9018c000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_cntrl_cva5(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80009000;
+		}
+		case 3: {
+			return 0x90009000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_cntrl_tgc(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x8000a000;
+		}
+		case 3: {
+			return 0x9000a000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_ccc_idxTasks(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80005000;
+		}
+		case 3: {
+			return 0x90005000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_ccc_idxJobs(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80004000;
+		}
+		case 3: {
+			return 0x90004000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_aes_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80007000;
+		}
+		case 3: {
+			return 0x90007000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_ut_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x9000b000;
+		}
+		case 2: {
+			return 0x8000b000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_sram0(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x8000c000;
+		}
+		case 3: {
+			return 0x9000c000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_sram3(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x8020c000;
+		}
+		case 3: {
+			return 0x9020c000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint64_t fki_addr_hide_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80008000;
+		}
+		case 3: {
+			return 0x90008000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+#endif //_FKI_CLUSTER_INFO_H

include/ehrenberg/devices/flexki_messages.h

@@ -0,0 +1,77 @@
+#ifndef _FLEXKI_MESSAGES_H
+#define _FLEXKI_MESSAGES_H
+
+#include "fki_cluster_info.h"
+
+#include <stdbool.h>
+
+static void send_msg(uint32_t cluster, uint32_t component, uint32_t msg_len, uint32_t msg_id, uint32_t* words) {
+    set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(msgif, component);
+	set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(msgif, cluster);
+	set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(msgif, msg_len);
+	set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(msgif, msg_id);
+    for (uint32_t i = 0; i < msg_len; i = i + 1) {
+        switch (i) {
+            case 0:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(msgif, words[i]);
+                break;
+            case 1:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(msgif, words[i]);
+                break;
+            case 2:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(msgif, words[i]);
+                break;
+            case 3:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(msgif, words[i]);
+                break;
+            case 4:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(msgif, words[i]);
+                break;
+            case 5:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(msgif, words[i]);
+                break;
+            case 6:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(msgif, words[i]);
+                break;
+            case 7:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(msgif, words[i]);
+                break;
+            default:
+                break;
+        }
+    }
+    set_mkcontrolclusterstreamcontroller_REG_SEND(msgif, 1);
+}
+
+static uint32_t check_response(void) {
+    while (true) {
+        if (get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(msgif) != 0) {
+            return get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(msgif);
+        }
+    }
+}
+
+static uint32_t wait_response(uint32_t msg_id) {
+    while (true) {
+        if (get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(msgif) != 0) {
+            if (get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(msgif) == msg_id) {
+                break;
+            }
+        }
+    }
+	uint32_t response_payload = get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(msgif);
+	set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(msgif, 1);
+	return response_payload;
+}
+
+static void fki_dma_transfer(uint32_t cluster, uint32_t msg_id, uint32_t srcAddr, uint32_t destAddr, uint32_t bytes) {
+    uint32_t values[] = {
+        0,
+        srcAddr,
+        destAddr,
+        bytes
+    };
+    send_msg(cluster, fki_dma(cluster), 4, msg_id, values);
+}
+
+#endif /* _FLEXKI_MESSAGES_H */

include/ehrenberg/devices/gen/apb3spi.h

@@ -1,9 +1,9 @@
 /*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-09-10 14:29:50 UTC 
+* Generated at 2025-02-17 15:56:47 UTC 
 * by peakrdl_mnrs version 1.2.9
 */
 
@@ -45,9 +45,9 @@ typedef struct {
 #define APB3SPI_DATA_READ_MASK 0x1
 #define APB3SPI_DATA_READ(V) ((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS)
 
-#define APB3SPI_DATA_KIND_OFFS 11
-#define APB3SPI_DATA_KIND_MASK 0x1
-#define APB3SPI_DATA_KIND(V) ((V & APB3SPI_DATA_KIND_MASK) << APB3SPI_DATA_KIND_OFFS)
+#define APB3SPI_DATA_SSGEN_OFFS 11
+#define APB3SPI_DATA_SSGEN_MASK 0x1
+#define APB3SPI_DATA_SSGEN(V) ((V & APB3SPI_DATA_SSGEN_MASK) << APB3SPI_DATA_SSGEN_OFFS)
 
 #define APB3SPI_DATA_RX_DATA_INVALID_OFFS 31
 #define APB3SPI_DATA_RX_DATA_INVALID_MASK 0x1
@@ -179,10 +179,10 @@ inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg){
 inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value){
     reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
 }
-inline uint32_t get_apb3spi_data_kind(volatile apb3spi_t* reg){
+inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t* reg){
     return (reg->DATA >> 11) & 0x1;
 }
-inline void set_apb3spi_data_kind(volatile apb3spi_t* reg, uint8_t value){
+inline void set_apb3spi_data_ssgen(volatile apb3spi_t* reg, uint8_t value){
     reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
 }
 inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg){
@@ -242,9 +242,15 @@ inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value){
 inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg){
     return (reg->INTR >> 8) & 0x1;
 }
+inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t* reg, uint8_t value){
+    reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8);
+}
 inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg){
     return (reg->INTR >> 9) & 0x1;
 }
+inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t* reg, uint8_t value){
+    reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9);
+}
 inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg){
     return (reg->INTR >> 16) & 0x1;
 }

include/ehrenberg/devices/gen/camera.h

@@ -1,9 +1,9 @@
 /*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-09-10 14:29:50 UTC 
+* Generated at 2025-02-28 17:25:03 UTC 
 * by peakrdl_mnrs version 1.2.9
 */
 
@@ -14,6 +14,10 @@
 
 typedef struct {
     volatile uint32_t PIXEL;
+    volatile uint32_t CONFIG;
+    volatile uint32_t CONFIG2;
+    volatile uint32_t DATA_SIZE;
+    volatile uint32_t START;
     volatile uint32_t STATUS;
     volatile uint32_t CAMERA_CLOCK_CTRL;
     volatile uint32_t IE;
@@ -21,15 +25,87 @@ typedef struct {
 }camera_t;
 
 #define CAMERA_PIXEL_OFFS 0
-#define CAMERA_PIXEL_MASK 0x7ff
+#define CAMERA_PIXEL_MASK 0xffffffff
 #define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS)
 
+#define CAMERA_CONFIG_OUTPUT_CURR_OFFS 0
+#define CAMERA_CONFIG_OUTPUT_CURR_MASK 0x3
+#define CAMERA_CONFIG_OUTPUT_CURR(V) ((V & CAMERA_CONFIG_OUTPUT_CURR_MASK) << CAMERA_CONFIG_OUTPUT_CURR_OFFS)
+
+#define CAMERA_CONFIG_OFFSET_RAMP_OFFS 2
+#define CAMERA_CONFIG_OFFSET_RAMP_MASK 0x3
+#define CAMERA_CONFIG_OFFSET_RAMP(V) ((V & CAMERA_CONFIG_OFFSET_RAMP_MASK) << CAMERA_CONFIG_OFFSET_RAMP_OFFS)
+
+#define CAMERA_CONFIG_RAMP_GAIN_OFFS 4
+#define CAMERA_CONFIG_RAMP_GAIN_MASK 0x3
+#define CAMERA_CONFIG_RAMP_GAIN(V) ((V & CAMERA_CONFIG_RAMP_GAIN_MASK) << CAMERA_CONFIG_RAMP_GAIN_OFFS)
+
+#define CAMERA_CONFIG_VRST_PIX_OFFS 6
+#define CAMERA_CONFIG_VRST_PIX_MASK 0x3
+#define CAMERA_CONFIG_VRST_PIX(V) ((V & CAMERA_CONFIG_VRST_PIX_MASK) << CAMERA_CONFIG_VRST_PIX_OFFS)
+
+#define CAMERA_CONFIG_ROWS_IN_RESET_OFFS 8
+#define CAMERA_CONFIG_ROWS_IN_RESET_MASK 0xff
+#define CAMERA_CONFIG_ROWS_IN_RESET(V) ((V & CAMERA_CONFIG_ROWS_IN_RESET_MASK) << CAMERA_CONFIG_ROWS_IN_RESET_OFFS)
+
+#define CAMERA_CONFIG_HIGH_SPEED_OFFS 16
+#define CAMERA_CONFIG_HIGH_SPEED_MASK 0x1
+#define CAMERA_CONFIG_HIGH_SPEED(V) ((V & CAMERA_CONFIG_HIGH_SPEED_MASK) << CAMERA_CONFIG_HIGH_SPEED_OFFS)
+
+#define CAMERA_CONFIG_IDLE_MODE_OFFS 17
+#define CAMERA_CONFIG_IDLE_MODE_MASK 0x1
+#define CAMERA_CONFIG_IDLE_MODE(V) ((V & CAMERA_CONFIG_IDLE_MODE_MASK) << CAMERA_CONFIG_IDLE_MODE_OFFS)
+
+#define CAMERA_CONFIG_CVC_CURR_OFFS 18
+#define CAMERA_CONFIG_CVC_CURR_MASK 0x3
+#define CAMERA_CONFIG_CVC_CURR(V) ((V & CAMERA_CONFIG_CVC_CURR_MASK) << CAMERA_CONFIG_CVC_CURR_OFFS)
+
+#define CAMERA_CONFIG_VREF_OFFS 20
+#define CAMERA_CONFIG_VREF_MASK 0x3
+#define CAMERA_CONFIG_VREF(V) ((V & CAMERA_CONFIG_VREF_MASK) << CAMERA_CONFIG_VREF_OFFS)
+
+#define CAMERA_CONFIG_MCLK_MODE_OFFS 22
+#define CAMERA_CONFIG_MCLK_MODE_MASK 0x3
+#define CAMERA_CONFIG_MCLK_MODE(V) ((V & CAMERA_CONFIG_MCLK_MODE_MASK) << CAMERA_CONFIG_MCLK_MODE_OFFS)
+
+#define CAMERA_CONFIG_OUTPUT_MODE_OFFS 24
+#define CAMERA_CONFIG_OUTPUT_MODE_MASK 0x1
+#define CAMERA_CONFIG_OUTPUT_MODE(V) ((V & CAMERA_CONFIG_OUTPUT_MODE_MASK) << CAMERA_CONFIG_OUTPUT_MODE_OFFS)
+
+#define CAMERA_CONFIG_CDS_GAIN_OFFS 25
+#define CAMERA_CONFIG_CDS_GAIN_MASK 0x1
+#define CAMERA_CONFIG_CDS_GAIN(V) ((V & CAMERA_CONFIG_CDS_GAIN_MASK) << CAMERA_CONFIG_CDS_GAIN_OFFS)
+
+#define CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS 26
+#define CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK 0x1
+#define CAMERA_CONFIG_BIAS_CURR_INCREASE(V) ((V & CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK) << CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS)
+
+#define CAMERA_CONFIG_ROWS_DELAY_OFFS 27
+#define CAMERA_CONFIG_ROWS_DELAY_MASK 0x1f
+#define CAMERA_CONFIG_ROWS_DELAY(V) ((V & CAMERA_CONFIG_ROWS_DELAY_MASK) << CAMERA_CONFIG_ROWS_DELAY_OFFS)
+
+#define CAMERA_CONFIG2_AUTO_IDLE_OFFS 0
+#define CAMERA_CONFIG2_AUTO_IDLE_MASK 0x1
+#define CAMERA_CONFIG2_AUTO_IDLE(V) ((V & CAMERA_CONFIG2_AUTO_IDLE_MASK) << CAMERA_CONFIG2_AUTO_IDLE_OFFS)
+
+#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS 1
+#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK 0x1
+#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME(V) ((V & CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK) << CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS)
+
+#define CAMERA_DATA_SIZE_OFFS 0
+#define CAMERA_DATA_SIZE_MASK 0x3
+#define CAMERA_DATA_SIZE(V) ((V & CAMERA_DATA_SIZE_MASK) << CAMERA_DATA_SIZE_OFFS)
+
+#define CAMERA_START_OFFS 0
+#define CAMERA_START_MASK 0x1
+#define CAMERA_START(V) ((V & CAMERA_START_MASK) << CAMERA_START_OFFS)
+
 #define CAMERA_STATUS_OFFS 0
 #define CAMERA_STATUS_MASK 0x1
 #define CAMERA_STATUS(V) ((V & CAMERA_STATUS_MASK) << CAMERA_STATUS_OFFS)
 
 #define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0
-#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfffff
+#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfff
 #define CAMERA_CAMERA_CLOCK_CTRL(V) ((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS)
 
 #define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0
@@ -50,16 +126,150 @@ typedef struct {
 
 //CAMERA_PIXEL
 inline uint32_t get_camera_pixel(volatile camera_t* reg){
-     return reg->PIXEL;
+    return (reg->PIXEL >> 0) & 0xffffffff;
 }
 inline void set_camera_pixel(volatile camera_t* reg, uint32_t value){
-     reg->PIXEL = value;
+    reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0);
 }
-inline uint32_t get_camera_pixel_data(volatile camera_t* reg){
-    return (reg->PIXEL >> 0) & 0x7ff;
+
+//CAMERA_CONFIG
+inline uint32_t get_camera_config(volatile camera_t* reg){
+     return reg->CONFIG;
 }
-inline void set_camera_pixel_data(volatile camera_t* reg, uint16_t value){
-    reg->PIXEL = (reg->PIXEL & ~(0x7ffU << 0)) | (value << 0);
+inline void set_camera_config(volatile camera_t* reg, uint32_t value){
+     reg->CONFIG = value;
+}
+inline uint32_t get_camera_config_output_curr(volatile camera_t* reg){
+    return (reg->CONFIG >> 0) & 0x3;
+}
+inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg){
+    return (reg->CONFIG >> 2) & 0x3;
+}
+inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2);
+}
+inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg){
+    return (reg->CONFIG >> 4) & 0x3;
+}
+inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
+}
+inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg){
+    return (reg->CONFIG >> 6) & 0x3;
+}
+inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6);
+}
+inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg){
+    return (reg->CONFIG >> 8) & 0xff;
+}
+inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8);
+}
+inline uint32_t get_camera_config_high_speed(volatile camera_t* reg){
+    return (reg->CONFIG >> 16) & 0x1;
+}
+inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16);
+}
+inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg){
+    return (reg->CONFIG >> 17) & 0x1;
+}
+inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17);
+}
+inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg){
+    return (reg->CONFIG >> 18) & 0x3;
+}
+inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18);
+}
+inline uint32_t get_camera_config_vref(volatile camera_t* reg){
+    return (reg->CONFIG >> 20) & 0x3;
+}
+inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20);
+}
+inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg){
+    return (reg->CONFIG >> 22) & 0x3;
+}
+inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22);
+}
+inline uint32_t get_camera_config_output_mode(volatile camera_t* reg){
+    return (reg->CONFIG >> 24) & 0x1;
+}
+inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24);
+}
+inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg){
+    return (reg->CONFIG >> 25) & 0x1;
+}
+inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25);
+}
+inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg){
+    return (reg->CONFIG >> 26) & 0x1;
+}
+inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26);
+}
+inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg){
+    return (reg->CONFIG >> 27) & 0x1f;
+}
+inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27);
+}
+
+//CAMERA_CONFIG2
+inline uint32_t get_camera_config2(volatile camera_t* reg){
+     return reg->CONFIG2;
+}
+inline void set_camera_config2(volatile camera_t* reg, uint32_t value){
+     reg->CONFIG2 = value;
+}
+inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg){
+    return (reg->CONFIG2 >> 0) & 0x1;
+}
+inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg){
+    return (reg->CONFIG2 >> 1) & 0x1;
+}
+inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1);
+}
+
+//CAMERA_DATA_SIZE
+inline uint32_t get_camera_data_size(volatile camera_t* reg){
+     return reg->DATA_SIZE;
+}
+inline void set_camera_data_size(volatile camera_t* reg, uint32_t value){
+     reg->DATA_SIZE = value;
+}
+inline uint32_t get_camera_data_size_data_size(volatile camera_t* reg){
+    return (reg->DATA_SIZE >> 0) & 0x3;
+}
+inline void set_camera_data_size_data_size(volatile camera_t* reg, uint8_t value){
+    reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0);
+}
+
+//CAMERA_START
+inline uint32_t get_camera_start(volatile camera_t* reg){
+     return reg->START;
+}
+inline void set_camera_start(volatile camera_t* reg, uint32_t value){
+     reg->START = value;
+}
+inline uint32_t get_camera_start_start(volatile camera_t* reg){
+    return (reg->START >> 0) & 0x1;
+}
+inline void set_camera_start_start(volatile camera_t* reg, uint8_t value){
+    reg->START = (reg->START & ~(0x1U << 0)) | (value << 0);
 }
 
 //CAMERA_STATUS
@@ -78,10 +288,10 @@ inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value)
      reg->CAMERA_CLOCK_CTRL = value;
 }
 inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg){
-    return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfffff;
+    return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff;
 }
-inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint32_t value){
-    reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
+inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value){
+    reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0);
 }
 
 //CAMERA_IE

include/ehrenberg/devices/gen/gpio.h

@@ -3,8 +3,8 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-08-09 14:18:51 UTC 
-* by peakrdl_mnrs version 1.2.8
+* Generated at 2024-12-06 09:43:24 UTC 
+* by peakrdl_mnrs version 1.2.9
 */
 
 #ifndef _BSP_GPIO_H
@@ -16,6 +16,12 @@ typedef struct {
     volatile uint32_t VALUE;
     volatile uint32_t WRITE;
     volatile uint32_t WRITEENABLE;
+    volatile uint32_t PULLUP;
+    volatile uint32_t PULDOWN;
+    volatile uint32_t DRIVESTRENGTH_0;
+    volatile uint32_t DRIVESTRENGTH_1;
+    volatile uint32_t DRIVESTRENGTH_2;
+    volatile uint32_t DRIVESTRENGTH_3;
     volatile uint32_t IE;
     volatile uint32_t IP;
     volatile uint32_t IRQ_TRIGGER;
@@ -35,6 +41,142 @@ typedef struct {
 #define GPIO_WRITEENABLE_MASK 0xffffffff
 #define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
 
+#define GPIO_PULLUP_OFFS 0
+#define GPIO_PULLUP_MASK 0xffffffff
+#define GPIO_PULLUP(V) ((V & GPIO_PULLUP_MASK) << GPIO_PULLUP_OFFS)
+
+#define GPIO_PULDOWN_OFFS 0
+#define GPIO_PULDOWN_MASK 0xffffffff
+#define GPIO_PULDOWN(V) ((V & GPIO_PULDOWN_MASK) << GPIO_PULDOWN_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_0_OFFS 0
+#define GPIO_DRIVESTRENGTH_0_PIN_0_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_0(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_0_MASK) << GPIO_DRIVESTRENGTH_0_PIN_0_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_1_OFFS 4
+#define GPIO_DRIVESTRENGTH_0_PIN_1_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_1(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_1_MASK) << GPIO_DRIVESTRENGTH_0_PIN_1_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_2_OFFS 8
+#define GPIO_DRIVESTRENGTH_0_PIN_2_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_2(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_2_MASK) << GPIO_DRIVESTRENGTH_0_PIN_2_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_3_OFFS 12
+#define GPIO_DRIVESTRENGTH_0_PIN_3_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_3(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_3_MASK) << GPIO_DRIVESTRENGTH_0_PIN_3_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_4_OFFS 16
+#define GPIO_DRIVESTRENGTH_0_PIN_4_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_4(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_4_MASK) << GPIO_DRIVESTRENGTH_0_PIN_4_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_5_OFFS 20
+#define GPIO_DRIVESTRENGTH_0_PIN_5_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_5(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_5_MASK) << GPIO_DRIVESTRENGTH_0_PIN_5_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_6_OFFS 24
+#define GPIO_DRIVESTRENGTH_0_PIN_6_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_6(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_6_MASK) << GPIO_DRIVESTRENGTH_0_PIN_6_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_7_OFFS 28
+#define GPIO_DRIVESTRENGTH_0_PIN_7_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_7(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_7_MASK) << GPIO_DRIVESTRENGTH_0_PIN_7_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_8_OFFS 0
+#define GPIO_DRIVESTRENGTH_1_PIN_8_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_8(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_8_MASK) << GPIO_DRIVESTRENGTH_1_PIN_8_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_9_OFFS 4
+#define GPIO_DRIVESTRENGTH_1_PIN_9_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_9(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_9_MASK) << GPIO_DRIVESTRENGTH_1_PIN_9_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_10_OFFS 8
+#define GPIO_DRIVESTRENGTH_1_PIN_10_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_10(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_10_MASK) << GPIO_DRIVESTRENGTH_1_PIN_10_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_11_OFFS 12
+#define GPIO_DRIVESTRENGTH_1_PIN_11_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_11(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_11_MASK) << GPIO_DRIVESTRENGTH_1_PIN_11_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_12_OFFS 16
+#define GPIO_DRIVESTRENGTH_1_PIN_12_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_12(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_12_MASK) << GPIO_DRIVESTRENGTH_1_PIN_12_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_13_OFFS 20
+#define GPIO_DRIVESTRENGTH_1_PIN_13_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_13(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_13_MASK) << GPIO_DRIVESTRENGTH_1_PIN_13_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_14_OFFS 24
+#define GPIO_DRIVESTRENGTH_1_PIN_14_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_14(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_14_MASK) << GPIO_DRIVESTRENGTH_1_PIN_14_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_15_OFFS 28
+#define GPIO_DRIVESTRENGTH_1_PIN_15_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_15(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_15_MASK) << GPIO_DRIVESTRENGTH_1_PIN_15_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_16_OFFS 0
+#define GPIO_DRIVESTRENGTH_2_PIN_16_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_16(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_16_MASK) << GPIO_DRIVESTRENGTH_2_PIN_16_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_17_OFFS 4
+#define GPIO_DRIVESTRENGTH_2_PIN_17_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_17(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_17_MASK) << GPIO_DRIVESTRENGTH_2_PIN_17_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_18_OFFS 8
+#define GPIO_DRIVESTRENGTH_2_PIN_18_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_18(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_18_MASK) << GPIO_DRIVESTRENGTH_2_PIN_18_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_19_OFFS 12
+#define GPIO_DRIVESTRENGTH_2_PIN_19_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_19(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_19_MASK) << GPIO_DRIVESTRENGTH_2_PIN_19_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_20_OFFS 16
+#define GPIO_DRIVESTRENGTH_2_PIN_20_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_20(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_20_MASK) << GPIO_DRIVESTRENGTH_2_PIN_20_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_21_OFFS 20
+#define GPIO_DRIVESTRENGTH_2_PIN_21_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_21(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_21_MASK) << GPIO_DRIVESTRENGTH_2_PIN_21_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_22_OFFS 24
+#define GPIO_DRIVESTRENGTH_2_PIN_22_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_22(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_22_MASK) << GPIO_DRIVESTRENGTH_2_PIN_22_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_23_OFFS 28
+#define GPIO_DRIVESTRENGTH_2_PIN_23_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_23(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_23_MASK) << GPIO_DRIVESTRENGTH_2_PIN_23_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_24_OFFS 0
+#define GPIO_DRIVESTRENGTH_3_PIN_24_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_24(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_24_MASK) << GPIO_DRIVESTRENGTH_3_PIN_24_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_25_OFFS 4
+#define GPIO_DRIVESTRENGTH_3_PIN_25_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_25(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_25_MASK) << GPIO_DRIVESTRENGTH_3_PIN_25_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_26_OFFS 8
+#define GPIO_DRIVESTRENGTH_3_PIN_26_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_26(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_26_MASK) << GPIO_DRIVESTRENGTH_3_PIN_26_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_27_OFFS 12
+#define GPIO_DRIVESTRENGTH_3_PIN_27_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_27(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_27_MASK) << GPIO_DRIVESTRENGTH_3_PIN_27_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_28_OFFS 16
+#define GPIO_DRIVESTRENGTH_3_PIN_28_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_28(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_28_MASK) << GPIO_DRIVESTRENGTH_3_PIN_28_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_29_OFFS 20
+#define GPIO_DRIVESTRENGTH_3_PIN_29_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_29(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_29_MASK) << GPIO_DRIVESTRENGTH_3_PIN_29_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_30_OFFS 24
+#define GPIO_DRIVESTRENGTH_3_PIN_30_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_30(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_30_MASK) << GPIO_DRIVESTRENGTH_3_PIN_30_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_31_OFFS 28
+#define GPIO_DRIVESTRENGTH_3_PIN_31_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_31(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_31_MASK) << GPIO_DRIVESTRENGTH_3_PIN_31_OFFS)
+
 #define GPIO_IE_OFFS 0
 #define GPIO_IE_MASK 0xffffffff
 #define GPIO_IE(V) ((V & GPIO_IE_MASK) << GPIO_IE_OFFS)
@@ -76,6 +218,246 @@ inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value){
     reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
 }
 
+//GPIO_PULLUP
+inline uint32_t get_gpio_pullup(volatile gpio_t* reg){
+    return (reg->PULLUP >> 0) & 0xffffffff;
+}
+inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value){
+    reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_PULDOWN
+inline uint32_t get_gpio_puldown(volatile gpio_t* reg){
+    return (reg->PULDOWN >> 0) & 0xffffffff;
+}
+inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value){
+    reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_DRIVESTRENGTH_0
+inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg){
+     return reg->DRIVESTRENGTH_0;
+}
+inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value){
+     reg->DRIVESTRENGTH_0 = value;
+}
+inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 0) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 4) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 8) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 12) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 16) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 20) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 24) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24);
+}
+inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_0 >> 28) & 0x7;
+}
+inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28);
+}
+
+//GPIO_DRIVESTRENGTH_1
+inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg){
+     return reg->DRIVESTRENGTH_1;
+}
+inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value){
+     reg->DRIVESTRENGTH_1 = value;
+}
+inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 0) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 4) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 8) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 12) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 16) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 20) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 24) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24);
+}
+inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_1 >> 28) & 0x7;
+}
+inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28);
+}
+
+//GPIO_DRIVESTRENGTH_2
+inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg){
+     return reg->DRIVESTRENGTH_2;
+}
+inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value){
+     reg->DRIVESTRENGTH_2 = value;
+}
+inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 0) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 4) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 8) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 12) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 16) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 20) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 24) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24);
+}
+inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_2 >> 28) & 0x7;
+}
+inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28);
+}
+
+//GPIO_DRIVESTRENGTH_3
+inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg){
+     return reg->DRIVESTRENGTH_3;
+}
+inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value){
+     reg->DRIVESTRENGTH_3 = value;
+}
+inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 0) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 4) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 8) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 12) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 16) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 20) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 24) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24);
+}
+inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg){
+    return (reg->DRIVESTRENGTH_3 >> 28) & 0x7;
+}
+inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value){
+    reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28);
+}
+
 //GPIO_IE
 inline uint32_t get_gpio_ie(volatile gpio_t* reg){
     return (reg->IE >> 0) & 0xffffffff;
@@ -116,4 +498,4 @@ inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg){
     return (reg->BOOT_SEL >> 0) & 0x7;
 }
 
-#endif /* _BSP_GPIO_H */
+#endif /* _BSP_GPIO_H */

include/ehrenberg/devices/gen/i2s.h

@@ -3,7 +3,7 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-09-10 14:29:50 UTC 
+* Generated at 2024-12-28 11:01:24 UTC 
 * by peakrdl_mnrs version 1.2.9
 */
 
@@ -19,6 +19,7 @@ typedef struct {
     volatile uint32_t STATUS;
     volatile uint32_t I2S_CLOCK_CTRL;
     volatile uint32_t PDM_CLOCK_CTRL;
+    volatile uint32_t PDM_FILTER_CTRL;
     volatile uint32_t IE;
     volatile uint32_t IP;
 }i2s_t;
@@ -71,14 +72,26 @@ typedef struct {
 #define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
 #define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
 
+#define I2S_STATUS_LEFT_OVERFLOW_OFFS 4
+#define I2S_STATUS_LEFT_OVERFLOW_MASK 0x1
+#define I2S_STATUS_LEFT_OVERFLOW(V) ((V & I2S_STATUS_LEFT_OVERFLOW_MASK) << I2S_STATUS_LEFT_OVERFLOW_OFFS)
+
+#define I2S_STATUS_RIGHT_OVERFLOW_OFFS 5
+#define I2S_STATUS_RIGHT_OVERFLOW_MASK 0x1
+#define I2S_STATUS_RIGHT_OVERFLOW(V) ((V & I2S_STATUS_RIGHT_OVERFLOW_MASK) << I2S_STATUS_RIGHT_OVERFLOW_OFFS)
+
 #define I2S_I2S_CLOCK_CTRL_OFFS 0
 #define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
 #define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
 
 #define I2S_PDM_CLOCK_CTRL_OFFS 0
-#define I2S_PDM_CLOCK_CTRL_MASK 0x3ff
+#define I2S_PDM_CLOCK_CTRL_MASK 0xff
 #define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)
 
+#define I2S_PDM_FILTER_CTRL_OFFS 0
+#define I2S_PDM_FILTER_CTRL_MASK 0x3ff
+#define I2S_PDM_FILTER_CTRL(V) ((V & I2S_PDM_FILTER_CTRL_MASK) << I2S_PDM_FILTER_CTRL_OFFS)
+
 #define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0
 #define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1
 #define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS)
@@ -153,6 +166,9 @@ inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
 inline uint32_t get_i2s_status(volatile i2s_t* reg){
      return reg->STATUS;
 }
+inline void set_i2s_status(volatile i2s_t* reg, uint32_t value){
+     reg->STATUS = value;
+}
 inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){
     return (reg->STATUS >> 0) & 0x1;
 }
@@ -165,6 +181,18 @@ inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){
 inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
     return (reg->STATUS >> 3) & 0x1;
 }
+inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg){
+    return (reg->STATUS >> 4) & 0x1;
+}
+inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value){
+    reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4);
+}
+inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg){
+    return (reg->STATUS >> 5) & 0x1;
+}
+inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value){
+    reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5);
+}
 
 //I2S_I2S_CLOCK_CTRL
 inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){
@@ -188,10 +216,24 @@ inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value){
      reg->PDM_CLOCK_CTRL = value;
 }
 inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg){
-    return (reg->PDM_CLOCK_CTRL >> 0) & 0x3ff;
+    return (reg->PDM_CLOCK_CTRL >> 0) & 0xff;
 }
-inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint16_t value){
-    reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0x3ffU << 0)) | (value << 0);
+inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value){
+    reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0);
+}
+
+//I2S_PDM_FILTER_CTRL
+inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t* reg){
+     return reg->PDM_FILTER_CTRL;
+}
+inline void set_i2s_pdm_filter_ctrl(volatile i2s_t* reg, uint32_t value){
+     reg->PDM_FILTER_CTRL = value;
+}
+inline uint32_t get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg){
+    return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff;
+}
+inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg, uint16_t value){
+    reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0);
 }
 
 //I2S_IE

include/ehrenberg/devices/gen/mkcontrolclusterstreamcontroller.h

@@ -0,0 +1,207 @@
+/*
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2025-02-18 11:11:47 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
+#define _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t REG_SEND;
+    volatile uint32_t REG_HEADER;
+    volatile uint32_t REG_ACK;
+    volatile uint32_t REG_RECV_ID;
+    volatile uint32_t REG_RECV_PAYLOAD;
+    uint8_t fill0[12];
+    volatile uint32_t REG_PAYLOAD_0;
+    volatile uint32_t REG_PAYLOAD_1;
+    volatile uint32_t REG_PAYLOAD_2;
+    volatile uint32_t REG_PAYLOAD_3;
+    volatile uint32_t REG_PAYLOAD_4;
+    volatile uint32_t REG_PAYLOAD_5;
+    volatile uint32_t REG_PAYLOAD_6;
+    volatile uint32_t REG_PAYLOAD_7;
+}mkcontrolclusterstreamcontroller_t;
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS 4
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS 1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS)
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND
+inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+     reg->REG_SEND = value;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg){
+     return reg->REG_HEADER;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+     reg->REG_HEADER = value;
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_HEADER >> 0) & 0xf;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_HEADER >> 4) & 0xf;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_HEADER >> 8) & 0x7;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_HEADER >> 11) & 0x3;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg){
+     return reg->REG_ACK;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+     reg->REG_ACK = value;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_ACK >> 1) & 0x1;
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
+     return reg->REG_RECV_ID;
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_RECV_ID >> 0) & 0xf;
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H */

include/ehrenberg/devices/gen/msgif.h

@@ -3,7 +3,7 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-11-05 12:12:15 UTC 
+* Generated at 2024-11-20 11:54:52 UTC 
 * by peakrdl_mnrs version 1.2.7
 */
 
@@ -33,21 +33,21 @@ typedef struct {
 #define MSGIF_REG_SEND_MASK 0x1
 #define MSGIF_REG_SEND(V) ((V & MSGIF_REG_SEND_MASK) << MSGIF_REG_SEND_OFFS)
 
-#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 0
-#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
-#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
+#define MSGIF_REG_HEADER_MESSAGE_ID_OFFS 0
+#define MSGIF_REG_HEADER_MESSAGE_ID_MASK 0xf
+#define MSGIF_REG_HEADER_MESSAGE_ID(V) ((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS)
 
-#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 3
-#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
-#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
-
-#define MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS 5
+#define MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS 4
 #define MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
 #define MSGIF_REG_HEADER_MESSAGE_LENGTH(V) ((V & MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK) << MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS)
 
-#define MSGIF_REG_HEADER_MESSAGE_ID_OFFS 9
-#define MSGIF_REG_HEADER_MESSAGE_ID_MASK 0xf
-#define MSGIF_REG_HEADER_MESSAGE_ID(V) ((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS)
+#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
+#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
+#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
+
+#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
+#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
+#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
 
 #define MSGIF_REG_ACK_OFFS 0
 #define MSGIF_REG_ACK_MASK 0x1
@@ -108,29 +108,29 @@ inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg){
 inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value){
      reg->REG_HEADER = value;
 }
-inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg){
-    return (reg->REG_HEADER >> 0) & 0x7;
-}
-inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value){
-    reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 0)) | (value << 0);
-}
-inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg){
-    return (reg->REG_HEADER >> 3) & 0x3;
-}
-inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value){
-    reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 3)) | (value << 3);
-}
-inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg){
-    return (reg->REG_HEADER >> 5) & 0xf;
-}
-inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value){
-    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 5)) | (value << 5);
-}
 inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg){
-    return (reg->REG_HEADER >> 9) & 0xf;
+    return (reg->REG_HEADER >> 0) & 0xf;
 }
 inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value){
-    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 9)) | (value << 9);
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
+}
+inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg){
+    return (reg->REG_HEADER >> 4) & 0xf;
+}
+inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
+}
+inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg){
+    return (reg->REG_HEADER >> 8) & 0x7;
+}
+inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg){
+    return (reg->REG_HEADER >> 11) & 0x3;
+}
+inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
 }
 
 //MSGIF_REG_ACK

include/ehrenberg/devices/gen/sysctrl.h

@@ -0,0 +1,122 @@
+/*
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2025-02-19 17:15:41 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_SYSCTRL_H
+#define _BSP_SYSCTRL_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t SYSCTRL;
+    volatile uint32_t PLLCTRL;
+    volatile uint32_t AXI_BACKUP;
+}sysctrl_t;
+
+#define SYSCTRL_SYSCTRL_CC0_RESET_OFFS 0
+#define SYSCTRL_SYSCTRL_CC0_RESET_MASK 0x3
+#define SYSCTRL_SYSCTRL_CC0_RESET(V) ((V & SYSCTRL_SYSCTRL_CC0_RESET_MASK) << SYSCTRL_SYSCTRL_CC0_RESET_OFFS)
+
+#define SYSCTRL_SYSCTRL_CC1_RESET_OFFS 2
+#define SYSCTRL_SYSCTRL_CC1_RESET_MASK 0x3
+#define SYSCTRL_SYSCTRL_CC1_RESET(V) ((V & SYSCTRL_SYSCTRL_CC1_RESET_MASK) << SYSCTRL_SYSCTRL_CC1_RESET_OFFS)
+
+#define SYSCTRL_SYSCTRL_MEM_RESET_OFFS 4
+#define SYSCTRL_SYSCTRL_MEM_RESET_MASK 0x1
+#define SYSCTRL_SYSCTRL_MEM_RESET(V) ((V & SYSCTRL_SYSCTRL_MEM_RESET_MASK) << SYSCTRL_SYSCTRL_MEM_RESET_OFFS)
+
+#define SYSCTRL_PLLCTRL_P_COUNTER_OFFS 0
+#define SYSCTRL_PLLCTRL_P_COUNTER_MASK 0x3f
+#define SYSCTRL_PLLCTRL_P_COUNTER(V) ((V & SYSCTRL_PLLCTRL_P_COUNTER_MASK) << SYSCTRL_PLLCTRL_P_COUNTER_OFFS)
+
+#define SYSCTRL_PLLCTRL_S_COUNTER_OFFS 6
+#define SYSCTRL_PLLCTRL_S_COUNTER_MASK 0x3
+#define SYSCTRL_PLLCTRL_S_COUNTER(V) ((V & SYSCTRL_PLLCTRL_S_COUNTER_MASK) << SYSCTRL_PLLCTRL_S_COUNTER_OFFS)
+
+#define SYSCTRL_PLLCTRL_CLK_SEL_OFFS 8
+#define SYSCTRL_PLLCTRL_CLK_SEL_MASK 0x3
+#define SYSCTRL_PLLCTRL_CLK_SEL(V) ((V & SYSCTRL_PLLCTRL_CLK_SEL_MASK) << SYSCTRL_PLLCTRL_CLK_SEL_OFFS)
+
+#define SYSCTRL_PLLCTRL_LOCKED_OFFS 31
+#define SYSCTRL_PLLCTRL_LOCKED_MASK 0x1
+#define SYSCTRL_PLLCTRL_LOCKED(V) ((V & SYSCTRL_PLLCTRL_LOCKED_MASK) << SYSCTRL_PLLCTRL_LOCKED_OFFS)
+
+#define SYSCTRL_AXI_BACKUP_OFFS 0
+#define SYSCTRL_AXI_BACKUP_MASK 0x1f
+#define SYSCTRL_AXI_BACKUP(V) ((V & SYSCTRL_AXI_BACKUP_MASK) << SYSCTRL_AXI_BACKUP_OFFS)
+
+//SYSCTRL_SYSCTRL
+inline uint32_t get_sysctrl_sysctrl(volatile sysctrl_t* reg){
+     return reg->SYSCTRL;
+}
+inline void set_sysctrl_sysctrl(volatile sysctrl_t* reg, uint32_t value){
+     reg->SYSCTRL = value;
+}
+inline uint32_t get_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg){
+    return (reg->SYSCTRL >> 0) & 0x3;
+}
+inline void set_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg, uint8_t value){
+    reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg){
+    return (reg->SYSCTRL >> 2) & 0x3;
+}
+inline void set_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg, uint8_t value){
+    reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 2)) | (value << 2);
+}
+inline uint32_t get_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg){
+    return (reg->SYSCTRL >> 4) & 0x1;
+}
+inline void set_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg, uint8_t value){
+    reg->SYSCTRL = (reg->SYSCTRL & ~(0x1U << 4)) | (value << 4);
+}
+
+//SYSCTRL_PLLCTRL
+inline uint32_t get_sysctrl_pllctrl(volatile sysctrl_t* reg){
+     return reg->PLLCTRL;
+}
+inline void set_sysctrl_pllctrl(volatile sysctrl_t* reg, uint32_t value){
+     reg->PLLCTRL = value;
+}
+inline uint32_t get_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg){
+    return (reg->PLLCTRL >> 0) & 0x3f;
+}
+inline void set_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg, uint8_t value){
+    reg->PLLCTRL = (reg->PLLCTRL & ~(0x3fU << 0)) | (value << 0);
+}
+inline uint32_t get_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg){
+    return (reg->PLLCTRL >> 6) & 0x3;
+}
+inline void set_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg, uint8_t value){
+    reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 6)) | (value << 6);
+}
+inline uint32_t get_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg){
+    return (reg->PLLCTRL >> 8) & 0x3;
+}
+inline void set_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg, uint8_t value){
+    reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 8)) | (value << 8);
+}
+inline uint32_t get_sysctrl_pllctrl_locked(volatile sysctrl_t* reg){
+    return (reg->PLLCTRL >> 31) & 0x1;
+}
+
+//SYSCTRL_AXI_BACKUP
+inline uint32_t get_sysctrl_axi_backup(volatile sysctrl_t* reg){
+     return reg->AXI_BACKUP;
+}
+inline void set_sysctrl_axi_backup(volatile sysctrl_t* reg, uint32_t value){
+     reg->AXI_BACKUP = value;
+}
+inline uint32_t get_sysctrl_axi_backup_page(volatile sysctrl_t* reg){
+    return (reg->AXI_BACKUP >> 0) & 0x1f;
+}
+inline void set_sysctrl_axi_backup_page(volatile sysctrl_t* reg, uint8_t value){
+    reg->AXI_BACKUP = (reg->AXI_BACKUP & ~(0x1fU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_SYSCTRL_H */

include/ehrenberg/devices/gen/timercounter.h

@@ -3,8 +3,8 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-08-02 08:46:07 UTC 
-* by peakrdl_mnrs version 1.2.7
+* Generated at 2024-12-26 18:07:07 UTC 
+* by peakrdl_mnrs version 1.2.9
 */
 
 #ifndef _BSP_TIMERCOUNTER_H
@@ -16,10 +16,10 @@ typedef struct {
     volatile uint32_t PRESCALER;
     volatile uint32_t T0_CTRL;
     volatile uint32_t T0_OVERFLOW;
-    volatile uint32_t T0_VALUE;
+    volatile uint32_t T0_COUNTER;
     volatile uint32_t T1_CTRL;
     volatile uint32_t T1_OVERFLOW;
-    volatile uint32_t T1_VALUE;
+    volatile uint32_t T1_COUNTER;
 }timercounter_t;
 
 #define TIMERCOUNTER_PRESCALER_OFFS 0
@@ -38,9 +38,9 @@ typedef struct {
 #define TIMERCOUNTER_T0_OVERFLOW_MASK 0xffffffff
 #define TIMERCOUNTER_T0_OVERFLOW(V) ((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS)
 
-#define TIMERCOUNTER_T0_VALUE_OFFS 0
-#define TIMERCOUNTER_T0_VALUE_MASK 0xffffffff
-#define TIMERCOUNTER_T0_VALUE(V) ((V & TIMERCOUNTER_T0_VALUE_MASK) << TIMERCOUNTER_T0_VALUE_OFFS)
+#define TIMERCOUNTER_T0_COUNTER_OFFS 0
+#define TIMERCOUNTER_T0_COUNTER_MASK 0xffffffff
+#define TIMERCOUNTER_T0_COUNTER(V) ((V & TIMERCOUNTER_T0_COUNTER_MASK) << TIMERCOUNTER_T0_COUNTER_OFFS)
 
 #define TIMERCOUNTER_T1_CTRL_ENABLE_OFFS 0
 #define TIMERCOUNTER_T1_CTRL_ENABLE_MASK 0x7
@@ -54,9 +54,9 @@ typedef struct {
 #define TIMERCOUNTER_T1_OVERFLOW_MASK 0xffffffff
 #define TIMERCOUNTER_T1_OVERFLOW(V) ((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS)
 
-#define TIMERCOUNTER_T1_VALUE_OFFS 0
-#define TIMERCOUNTER_T1_VALUE_MASK 0xffffffff
-#define TIMERCOUNTER_T1_VALUE(V) ((V & TIMERCOUNTER_T1_VALUE_MASK) << TIMERCOUNTER_T1_VALUE_OFFS)
+#define TIMERCOUNTER_T1_COUNTER_OFFS 0
+#define TIMERCOUNTER_T1_COUNTER_MASK 0xffffffff
+#define TIMERCOUNTER_T1_COUNTER(V) ((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS)
 
 //TIMERCOUNTER_PRESCALER
 inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg){
@@ -100,9 +100,9 @@ inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t
     reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
 }
 
-//TIMERCOUNTER_T0_VALUE
-inline uint32_t get_timercounter_t0_value(volatile timercounter_t* reg){
-    return (reg->T0_VALUE >> 0) & 0xffffffff;
+//TIMERCOUNTER_T0_COUNTER
+inline uint32_t get_timercounter_t0_counter(volatile timercounter_t* reg){
+    return (reg->T0_COUNTER >> 0) & 0xffffffff;
 }
 
 //TIMERCOUNTER_T1_CTRL
@@ -133,9 +133,9 @@ inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t
     reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
 }
 
-//TIMERCOUNTER_T1_VALUE
-inline uint32_t get_timercounter_t1_value(volatile timercounter_t* reg){
-    return (reg->T1_VALUE >> 0) & 0xffffffff;
+//TIMERCOUNTER_T1_COUNTER
+inline uint32_t get_timercounter_t1_counter(volatile timercounter_t* reg){
+    return (reg->T1_COUNTER >> 0) & 0xffffffff;
 }
 
-#endif /* _BSP_TIMERCOUNTER_H */
+#endif /* _BSP_TIMERCOUNTER_H */

include/ehrenberg/devices/msg_if.h

@@ -1,6 +1,6 @@
 #ifndef _DEVICES_MSG_IF_H
 #define _DEVICES_MSG_IF_H
 
-#include "gen/msgif.h"
+#include "gen/mkcontrolclusterstreamcontroller.h"
 
 #endif /* _DEVICES_MSG_IF_H */

include/ehrenberg/devices/sysctrl.h

@@ -0,0 +1,6 @@
+#ifndef _DEVICES_SYSCTRL_IF_H
+#define _DEVICES_SYSCTRL_IF_H
+
+#include "gen/sysctrl.h"
+
+#endif /* _DEVICES_sysctrl_IF_H */