 Eyck Jentzsch
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b5101117aa
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cleans bsp a bit up
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2024-01-14 08:14:57 +01:00 |
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Eyck Jentzsch
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5e7c2cbce9
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add default linker file for flash
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2024-01-13 23:24:39 +01:00 |
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Eyck Jentzsch
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13cd5cc76d
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adds ehrenberg platform
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2024-01-13 23:06:01 +01:00 |
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Eyck Jentzsch
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1d55083a55
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updates LICENSE
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2024-01-13 08:30:30 +01:00 |
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Eyck Jentzsch
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1c600a0458
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removes firmwares to just keep BSP
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2024-01-13 08:28:11 +01:00 |
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Eyck Jentzsch
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7728785e27
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Merge remote-tracking branch 'origin/develop'
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2024-01-13 08:23:56 +01:00 |
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Eyck Jentzsch
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51c8a93336
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fixes march definitions for dhrystone and coremark
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2023-12-09 16:38:45 +01:00 |
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Eyck Jentzsch
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fe1136c7ce
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fixes ISA handling
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2023-12-06 10:00:33 +01:00 |
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Eyck Jentzsch
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6ff0161882
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adds some consistency fixes for variable ISA settings
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2023-12-02 17:41:14 +01:00 |
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Eyck Jentzsch
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8c1c2766e8
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Merge branch 'develop' into main
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2023-12-02 16:27:30 +01:00 |
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Eyck Jentzsch
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1b8f78fe78
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makes build more configurable by CLI
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2023-11-27 10:13:22 +01:00 |
 Stanislaw Kaushanski
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d20582d7aa
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fix prci build
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2023-11-24 13:06:31 +01:00 |
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Eyck Jentzsch
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0188d404de
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fixes hifive1 build
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2023-11-24 11:39:23 +01:00 |
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Stanislaw Kaushanski
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77ca8a01b4
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add hifive1
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2023-11-24 09:36:53 +01:00 |
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Eyck Jentzsch
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db53376533
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Merge branch 'develop' into main
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2023-11-23 18:30:43 +01:00 |
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Eyck Jentzsch
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41f204e304
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adds wrapping to all clib symbols
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2023-11-23 18:29:26 +01:00 |
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Eyck Jentzsch
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acf20a4818
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adds missing files
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2023-11-23 18:14:41 +01:00 |
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Eyck Jentzsch
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aab4d1f2a0
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adds missing symbols and sources for libwrap
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2023-11-23 18:14:41 +01:00 |
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Eyck Jentzsch
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e91ce0148b
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adds build targets
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2023-10-30 07:51:59 +01:00 |
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Eyck Jentzsch
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7093e47c08
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adds a CMakeLists.txt message to indicate board selection
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2023-10-27 22:16:21 +02:00 |
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Eyck Jentzsch
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63f57b9ba1
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extends eclipse build configs
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2023-10-26 06:11:12 +02:00 |
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Eyck Jentzsch
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af3a154882
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adds tgc-vp environment
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2023-10-25 20:35:44 +02:00 |
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Eyck Jentzsch
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b082091db2
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adds missing files
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2023-09-30 20:31:58 +02:00 |
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Eyck Jentzsch
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eeb17437ee
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adds missing symbols and sources for libwrap
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2023-09-28 11:51:20 +02:00 |
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Eyck Jentzsch
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9c0047b3ea
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updates linker script for rtl env
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2023-08-30 15:07:56 +02:00 |
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Eyck Jentzsch
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ca1adccb2b
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fixes TGC5L settings
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2023-08-28 10:01:06 +02:00 |
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Eyck Jentzsch
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3217871752
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extends build system to propagate more settings
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2023-08-20 16:45:54 +02:00 |
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Eyck Jentzsch
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9dd7dcb4ce
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adds TGC5L environment
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2023-08-20 16:39:20 +02:00 |
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Eyck Jentzsch
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3403edcde9
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adds CMakeLists.txt
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2023-08-20 15:50:00 +02:00 |
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Eyck Jentzsch
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3a3cbf38c3
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re-adds coremark as submodule
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2023-08-20 15:23:05 +02:00 |
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Eyck Jentzsch
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822696ae0d
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cleanup
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2023-08-20 15:20:39 +02:00 |
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Eyck Jentzsch
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314ceeb072
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rework structure
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2023-08-20 15:00:51 +02:00 |
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Eyck Jentzsch
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4c2208c1ac
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fix wrong exit call
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2022-11-06 17:33:39 +01:00 |
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Stanislaw Kaushanski
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36a6de6dc0
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remove raven dirs
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2022-05-02 13:21:12 +02:00 |
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Stanislaw Kaushanski
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d2cb78724a
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move RAVEN FW into Validation-VP repo
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2022-05-02 13:19:36 +02:00 |
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Stanislaw Kaushanski
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0de438dc52
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avoid interrupts while printing
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2022-05-02 09:51:05 +02:00 |
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Stanislaw Kaushanski
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5f44f8df98
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Improve wait for interrupt routines
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2022-04-28 19:20:32 +02:00 |
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Stanislaw Kaushanski
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02ce96eed8
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improve interrupt handling
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2022-04-26 15:29:49 +02:00 |
 Johannes Wirth
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46f197c287
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Add additional registers for input to FW
(number of XSPNs, batch size, iterations)
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2022-03-11 14:21:25 +01:00 |
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Johannes Wirth
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43e2a299db
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fpga_spn: add check if input-/ref-data fits into memory
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2022-03-10 14:17:52 +01:00 |
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Johannes Wirth
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8450f85c93
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raven_spn: add check if input-/ref-data fits into memory
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2022-03-10 13:11:10 +01:00 |
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Johannes Wirth
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a14ff554b0
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Move XSPN input and ref data to Validation-VP
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2022-03-10 13:09:11 +01:00 |
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Stanislaw Kaushanski
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588ca3c7ba
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Merge pull request 'Add allocate+free functionality for fpga' (#1) from feature/fpga-alloc-free into master
Reviewed-on: VP/Firmwares#1
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2022-02-11 16:12:21 +01:00 |
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Johannes Wirth
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91f28e9f2b
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Add allocate+free functionality for fpga
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2022-01-20 18:22:21 +01:00 |
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Johannes Wirth
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446af340c8
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fpga_spn: use separate reset for DMA
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2021-11-10 09:51:19 +01:00 |
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Johannes Wirth
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89ea594399
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Update FPGA Firmware for bigger batch sizes
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2021-07-13 10:51:28 +02:00 |
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Stanislaw Kaushanski
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a70f5bb09c
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add wait for both spn interrupts
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2021-05-17 11:54:37 +02:00 |
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Stanislaw Kaushanski
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1b09899d2a
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XSPN hybrid simulation passed in MINRES environment
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2021-04-22 14:50:21 +02:00 |
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Stanislaw Kaushanski
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5ba7d5dd24
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extend spn_checker to comapre the results from 2nd XSPN accelerator
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2021-04-20 20:36:00 +02:00 |
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Stanislaw Kaushanski
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26d7560891
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add second XSPN partition
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2021-04-20 08:30:39 +02:00 |