fixes literal type

.project

@@ -23,6 +23,5 @@
 		<nature>org.eclipse.cdt.core.ccnature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-		<nature>org.eclipse.linuxtools.tmf.project.nature</nature>
 	</natures>
 </projectDescription>

CMakeLists.txt

@@ -32,49 +32,41 @@ add_subdirectory(softfloat)
 set(LIB_SOURCES 
     src/iss/plugin/instruction_count.cpp
 	src/iss/arch/tgc_c.cpp
+	src/vm/tcc/vm_tgc_c.cpp
 	src/vm/interp/vm_tgc_c.cpp
 	src/vm/fp_functions.cpp
 )
+if(WITH_TCC)
+	list(APPEND LIB_SOURCES src/vm/tcc/vm_tgc_c.cpp)
+endif()
 
 # library files
-if(TARGET ${CORE_NAME}_cpp)
-    list(APPEND LIB_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
-else()
-    FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
-    FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
-    list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
-    foreach(FILEPATH ${GEN_ISS_SOURCES})
-        get_filename_component(CORE ${FILEPATH} NAME_WE)
-        string(TOUPPER ${CORE} CORE)
-        list(APPEND LIB_DEFINES CORE_${CORE})
-    endforeach()
-    message("Defines are ${LIB_DEFINES}")
+FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
+FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
+list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
+foreach(FILEPATH ${GEN_ISS_SOURCES})
+    get_filename_component(CORE ${FILEPATH} NAME_WE)
+    string(TOUPPER ${CORE} CORE)
+    list(APPEND LIB_DEFINES CORE_${CORE})
+endforeach()
+message("Core defines are ${LIB_DEFINES}")
+
+if(WITH_LLVM)
+	FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp)
+	list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
+endif()
+
+if(WITH_TCC)
+	FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/tcc/vm_*.cpp)
+	list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
 endif()
 
 if(TARGET RapidJSON OR TARGET RapidJSON::RapidJSON)
     list(APPEND LIB_SOURCES src/iss/plugin/cycle_estimate.cpp src/iss/plugin/pctrace.cpp)
 endif()
 
-if(WITH_LLVM)
-	FILE(GLOB LLVM_GEN_SOURCES
-	    ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp
-	)
-	list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
-endif()
-
-if(WITH_TCC)
-	FILE(GLOB TCC_GEN_SOURCES
-	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/tcc/vm_*.cpp
-	)
-	list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
-endif()
-
 # Define the library
 add_library(${PROJECT_NAME} ${LIB_SOURCES})
-# list code gen dependencies
-if(TARGET ${CORE_NAME}_cpp)
-    add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp)
-endif()
 
 if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
      target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
@@ -185,32 +177,40 @@ install(TARGETS tgc-sim
 #
 ###############################################################################
 if(TARGET scc-sysc)
+	if(BUILD_SHARED_LIBS)
+		set(DBT_RISE_SC_LIB_NAME dbt-rise-tgc_sc)
+	else()
+		set(DBT_RISE_SC_LIB_NAME dbt-rise-tgc_sc_lib)
+		set(CREATE_INTERFACE_LIB ON)
+	endif()
 	project(dbt-rise-tgc_sc VERSION 1.0.0)
-    add_library(${PROJECT_NAME} 
+
+    add_library(${DBT_RISE_SC_LIB_NAME} 
     	src/sysc/core_complex.cpp
     	src/sysc/register_tgc_c.cpp
     )
-    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
-    target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    target_include_directories(${DBT_RISE_SC_LIB_NAME} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src)
+    target_compile_definitions(${DBT_RISE_SC_LIB_NAME} PUBLIC WITH_SYSTEMC)
+    target_compile_definitions(${DBT_RISE_SC_LIB_NAME} PRIVATE CORE_${CORE_NAME})
     foreach(F IN LISTS TGC_SOURCES)
         if (${F} MATCHES ".*/arch/([^/]*)\.cpp")
             string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
             string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
-            target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+            target_compile_definitions(${DBT_RISE_SC_LIB_NAME} PRIVATE CORE_${CORE_NAME})
         endif()
     endforeach()
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
+    target_link_libraries(${DBT_RISE_SC_LIB_NAME} PUBLIC dbt-rise-tgc scc-sysc)
     if(WITH_LLVM)
-        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+        target_link_libraries(${DBT_RISE_SC_LIB_NAME} PUBLIC ${llvm_libs})
     endif()
     
 	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
-    set_target_properties(${PROJECT_NAME} PROPERTIES
+    set_target_properties(${DBT_RISE_SC_LIB_NAME} PROPERTIES
       VERSION ${PROJECT_VERSION}
       FRAMEWORK FALSE
       PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
     )
-    install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
+    install(TARGETS ${DBT_RISE_SC_LIB_NAME} COMPONENT ${PROJECT_NAME}
 	  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
 	  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
 	  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
@@ -219,5 +219,14 @@ if(TARGET scc-sysc)
 	  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc   # headers for mac (note the different component -> different package)
 	  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
 	)    
+	if(CREATE_INTERFACE_LIB)
+		add_library(dbt-rise-tgc_sc INTERFACE)
+	    target_include_directories(dbt-rise-tgc_sc INTERFACE 
+	       $<TARGET_PROPERTY:${DBT_RISE_SC_LIB_NAME},INTERFACE_INCLUDE_DIRECTORIES>)
+	    target_link_libraries(dbt-rise-tgc_sc INTERFACE 
+	    	-Wl,--whole-archive,$<TARGET_FILE:${DBT_RISE_SC_LIB_NAME}>,--no-whole-archive
+	    	$<TARGET_PROPERTY:${DBT_RISE_SC_LIB_NAME},INTERFACE_LINK_LIBRARIES>
+	    	scc-sysc)
+	endif()
 endif()
 

gen_input/templates/CORENAME.h.gtl

@@ -55,7 +55,7 @@ def byteSize(int size){
     return 128;
 }
 def getCString(def val){
-    return val.toString()
+    return val.toString()+'ULL'
 }
 %>
 #ifndef _${coreDef.name.toUpperCase()}_H_
@@ -111,7 +111,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
     
-    enum class opcode_e : unsigned short {<%instructions.eachWithIndex{instr, index -> %>
+    enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
         ${instr.instruction.name} = ${index},<%}%>
         MAX_OPCODE
     };

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -304,7 +304,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
     return pc;
 }
 
-}
+} // namespace ${coreDef.name.toLowerCase()}
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -321,13 +321,17 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()|m_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* lcpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()>();
-            return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
         }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()|mu_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* lcpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()>();
-            return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
         })
 };
 }

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -206,7 +206,7 @@ private:
             ${it}<%}%>
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc=pc+4;
+        pc=pc+ ${instr.length/8};
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();<%instr.behavior.eachLine{%>
         ${it}<%}%>
@@ -301,7 +301,7 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu("return *next_pc;");
 }
 
-} // namespace mnrv32
+} // namespace ${coreDef.name.toLowerCase()}
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -318,13 +318,17 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()|m_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* lcpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()>();
-            return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
         }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()|mu_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* lcpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()>();
-            return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
+		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
         })
 };
 }

src/iss/arch/riscv_hart_m_p.h

@@ -619,9 +619,9 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
             }
             return std::make_pair(entry, true);
         }
-        throw std::runtime_error("memory load file is not a valid elf file");
+        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
     }
-    throw std::runtime_error("memory load file not found");
+    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
 }
 
 template<typename BASE, features_e FEAT>

src/iss/arch/riscv_hart_msu_vp.h

@@ -588,9 +588,9 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
             }
             return std::make_pair(entry, true);
         }
-        throw std::runtime_error("memory load file is not a valid elf file");
+        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
     }
-    throw std::runtime_error("memory load file not found");
+    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
 }
 
 template <typename BASE>

src/iss/arch/riscv_hart_mu_p.h

@@ -690,9 +690,9 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
             }
             return std::make_pair(entry, true);
         }
-        throw std::runtime_error("memory load file is not a valid elf file");
+        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
     }
-    throw std::runtime_error("memory load file not found");
+    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
 }
 
 template<typename BASE, features_e FEAT>

src/iss/arch/tgc_c.h

@@ -53,7 +53,7 @@ template <> struct traits<tgc_c> {
     static constexpr std::array<const char*, 36> reg_aliases{
         {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
 
-    enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};
+    enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL};
 
     constexpr static unsigned FP_REGS_SIZE = 0;
 
@@ -83,7 +83,7 @@ template <> struct traits<tgc_c> {
 
     enum mem_type_e { MEM, FENCE, RES, CSR };
     
-    enum class opcode_e : unsigned short {
+    enum class opcode_e {
         LUI = 0,
         AUIPC = 1,
         JAL = 2,

src/sysc/core_complex.cpp

@@ -37,10 +37,11 @@
 #include <iss/debugger/target_adapter_if.h>
 #include <iss/iss.h>
 #include <iss/vm_types.h>
+#include <iss/factory.h>
 #ifndef WIN32
 #include <iss/plugin/loader.h>
 #endif
-#include "core_complex.h"
+#include "sc_core_adapter_if.h"
 #include <iss/arch/tgc_mapper.h>
 #include <scc/report.h>
 #include <util/ities.h>
@@ -85,136 +86,9 @@ using namespace sc_core;
 
 namespace {
 iss::debugger::encoder_decoder encdec;
-
 std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
 }
 
-template<typename PLAT>
-class core_wrapper_t : public PLAT {
-public:
-    using reg_t       = typename arch::traits<typename PLAT::core>::reg_t;
-    using phys_addr_t = typename arch::traits<typename PLAT::core>::phys_addr_t;
-    using heart_state_t = typename PLAT::hart_state_type;
-    core_wrapper_t(core_complex *owner)
-    : owner(owner) { }
-
-    uint32_t get_mode() { return this->reg.PRIV; }
-
-    inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
-
-    inline bool get_interrupt_execution() { return this->interrupt_sim; }
-
-    heart_state_t &get_state() { return this->state; }
-
-    void notify_phase(iss::arch_if::exec_phase p) override {
-        if (p == iss::arch_if::ISTART)
-            owner->sync(this->instr_if.get_total_cycles());
-    }
-
-    sync_type needed_sync() const override { return PRE_SYNC; }
-
-    void disass_output(uint64_t pc, const std::string instr) override {
-        if (!owner->disass_output(pc, instr)) {
-            std::stringstream s;
-            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
-              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
-              << this->reg.icount + this->cycle_offset << "]";
-            SCCDEBUG(owner->name())<<"disass: "
-                << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
-                << std::setfill(' ') << std::left << instr << s.str();
-        }
-    };
-
-    status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
-        if (addr.access && access_type::DEBUG)
-            return owner->read_mem_dbg(addr.val, length, data) ? Ok : Err;
-        else {
-            return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? Ok : Err;
-        }
-    }
-
-    status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) override {
-        if (addr.access && access_type::DEBUG)
-            return owner->write_mem_dbg(addr.val, length, data) ? Ok : Err;
-        else {
-            auto res = owner->write_mem(addr.val, length, data) ? Ok : Err;
-            // clear MTIP on mtimecmp write
-            if (addr.val == 0x2004000) {
-                reg_t val;
-                this->read_csr(arch::mip, val);
-                if (val & (1ULL << 7)) this->write_csr(arch::mip, val & ~(1ULL << 7));
-            }
-            return res;
-        }
-    }
-
-    status read_csr(unsigned addr, reg_t &val) override {
-#ifndef CWR_SYSTEMC
-        if((addr==arch::time || addr==arch::timeh) && owner->mtime_o.get_interface(0)){
-            uint64_t time_val;
-            bool ret = owner->mtime_o->nb_peek(time_val);
-            if (addr == iss::arch::time) {
-                val = static_cast<reg_t>(time_val);
-            } else if (addr == iss::arch::timeh) {
-                if (sizeof(reg_t) != 4) return iss::Err;
-                val = static_cast<reg_t>(time_val >> 32);
-            }
-            return ret?Ok:Err;
-#else
-		if((addr==arch::time || addr==arch::timeh)){
-			uint64_t time_val = owner->mtime_i.read();
-			if (addr == iss::arch::time) {
-				val = static_cast<reg_t>(time_val);
-			} else if (addr == iss::arch::timeh) {
-				if (sizeof(reg_t) != 4) return iss::Err;
-				val = static_cast<reg_t>(time_val >> 32);
-			}
-			return Ok;
-#endif
-        } else {
-            return PLAT::read_csr(addr, val);
-        }
-    }
-
-    void wait_until(uint64_t flags) override {
-        SCCDEBUG(owner->name()) << "Sleeping until interrupt";
-        while(this->reg.pending_trap == 0 && (this->csr[arch::mip] & this->csr[arch::mie]) == 0) {
-            sc_core::wait(wfi_evt);
-        }
-        PLAT::wait_until(flags);
-    }
-
-    void local_irq(short id, bool value) {
-        reg_t mask = 0;
-        switch (id) {
-        case 3: // SW
-            mask = 1 << 3;
-            break;
-        case 7: // timer
-            mask = 1 << 7;
-            break;
-        case 11: // external
-            mask = 1 << 11;
-            break;
-        default:
-            if(id>15) mask = 1 << id;
-            break;
-        }
-        if (value) {
-            this->csr[arch::mip] |= mask;
-            wfi_evt.notify();
-        } else
-            this->csr[arch::mip] &= ~mask;
-        this->check_interrupt();
-        if(value)
-            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
-    }
-
-private:
-    core_complex *const owner;
-    sc_event wfi_evt;
-};
-
 int cmd_sysc(int argc, char *argv[], debugger::out_func of, debugger::data_func df,
              debugger::target_adapter_if *tgt_adapter) {
     if (argc > 1) {
@@ -262,45 +136,34 @@ public:
     std::function<void(bool)> set_interrupt_execution;
     std::function<void(short, bool)> local_irq;
 
-    template<typename PLAT>
-    std::tuple<cpu_ptr, vm_ptr> create_core(std::string const& backend, unsigned gdb_port, uint32_t hart_id){
-        auto* lcpu = new core_wrapper_t<PLAT>(owner);
-        lcpu->set_mhartid(hart_id);
-        get_mode = [lcpu]() { return lcpu->get_mode(); };
-        get_state = [lcpu]() { return lcpu->get_state().mstatus.backing.val; };
-        get_interrupt_execution = [lcpu]() { return lcpu->get_interrupt_execution(); };
-        set_interrupt_execution = [lcpu](bool b) { return lcpu->set_interrupt_execution(b); };
-        local_irq = [lcpu](short s, bool b) { return lcpu->local_irq(s, b); };
-        if(backend == "interp")
-            return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(static_cast<typename PLAT::core*>(lcpu), gdb_port)}};
-#ifdef WITH_LLVM
-        if(backend == "llvm")
-            return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
-#endif
-#ifdef WITH_TCC
-        if(backend == "tcc")
-    s        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
-#endif
-        return {nullptr, nullptr};
-    }
-
     void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id){
-        CREATE_CORE(tgc_c)
-#ifdef CORE_TGC_B
-        CREATE_CORE(tgc_b)
-#endif
-#ifdef CORE_TGC_D
-        CREATE_CORE(tgc_d)
-#endif
-#ifdef CORE_TGC_D_XRB_MAC
-        CREATE_CORE(tgc_d_xrb_mac)
-#endif
-#ifdef CORE_TGC_D_XRB_NN
-        CREATE_CORE(tgc_d_xrb_nn)
-#endif
-        {
-            LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
+        auto & f = iss::core_factory::instance();
+        if(type.size()==0 || type == "?") {
+            std::cout<<"Available cores: "<<util::join(f.get_names(), ", ")<<std::endl;
+            sc_core::sc_stop();
+        } else if (type.find('|') != std::string::npos) {
+            std::tie(cpu, vm) = f.create(type+"|"+backend);
+        } else {
+            auto base_isa = type.substr(0, 5);
+            if(base_isa=="tgc_d" || base_isa=="tgc_e") {
+                std::tie(cpu, vm) = f.create(type + "|mu_p_clic_pmp|" + backend, gdb_port);
+            } else {
+                std::tie(cpu, vm) = f.create(type + "|m_p|" + backend, gdb_port);
+           }
         }
+        if(!cpu ){
+            SCCFATAL() << "Could not create cpu for isa " << type << " and backend " <<backend;
+        }
+        if(!vm ){
+            SCCFATAL() << "Could not create vm for isa " << type << " and backend " <<backend;
+        }
+        reinterpret_cast<sc_core_adapter_if&>(*cpu).set_mhartid(hart_id);
+        get_mode = [this]() { return reinterpret_cast<sc_core_adapter_if&>(*cpu).get_mode(); };
+        get_state = [this]() { return reinterpret_cast<sc_core_adapter_if&>(*cpu).get_state(); };
+        get_interrupt_execution = [this]() { return reinterpret_cast<sc_core_adapter_if&>(*cpu).get_interrupt_execution(); };
+        set_interrupt_execution = [this](bool b) { return reinterpret_cast<sc_core_adapter_if&>(*cpu).set_interrupt_execution(b); };
+        local_irq = [this](short s, bool b) { return reinterpret_cast<sc_core_adapter_if&>(*cpu).local_irq(s, b); };
+
         auto *srv = debugger::server<debugger::gdb_session>::get();
         if (srv) tgt_adapter = srv->get_target();
         if (tgt_adapter)
@@ -634,5 +497,5 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *
     gp.set_streaming_width(length);
     return dbus->transport_dbg(gp) == length;
 }
-} /* namespace SiFive */
+} /* namespace tgfs */
 } /* namespace sysc */

src/sysc/register_tgc_c.cpp

@@ -1,12 +1,34 @@
-/*
- * register_tgc_c.cpp
+/*******************************************************************************
+ * Copyright (C) 2023 MINRES Technologies GmbH
+ * All rights reserved.
  *
- *  Created on: Jul 5, 2023
- *      Author: eyck
- */
-
-
-
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
 
 #include <iss/factory.h>
 #include <iss/arch/tgc_c.h>
@@ -16,18 +38,34 @@
 #include "core_complex.h"
 
 namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
+namespace interp {
+volatile std::array<bool, 2> tgc_init = {
         core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            arch::tgc_c* lcpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
-            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
+            arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
+            return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
         }),
         core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            arch::tgc_c* lcpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
-            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
+            arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
+            return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
         })
 };
 }
+#if defined(WITH_TCC)
+namespace tcc {
+volatile std::array<bool, 2> tgc_init = {
+        core_factory::instance().register_creator("tgc_c|m_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
+            return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
+        }),
+        core_factory::instance().register_creator("tgc_c|mu_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
+            return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
+        })
+};
+}
+#endif
 }

src/sysc/sc_core_adapter.h

@@ -11,14 +11,13 @@
 
 #include <scc/report.h>
 #include <util/ities.h>
-#include "core_complex.h"
+#include "sc_core_adapter_if.h"
 #include <iss/iss.h>
 #include <iss/vm_types.h>
 #include <iostream>
 
-
 template<typename PLAT>
-class sc_core_adapter : public PLAT {
+class sc_core_adapter : public PLAT, public sc_core_adapter_if {
 public:
     using reg_t       = typename iss::arch::traits<typename PLAT::core>::reg_t;
     using phys_addr_t = typename iss::arch::traits<typename PLAT::core>::phys_addr_t;
@@ -26,13 +25,15 @@ public:
     sc_core_adapter(sysc::tgfs::core_complex *owner)
     : owner(owner) { }
 
-    uint32_t get_mode() { return this->reg.PRIV; }
+    void set_mhartid(unsigned id) override { PLAT::set_mhartid(id); }
 
-    inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
+    uint32_t get_mode() override { return this->reg.PRIV; }
 
-    inline bool get_interrupt_execution() { return this->interrupt_sim; }
+    void set_interrupt_execution(bool v) override { this->interrupt_sim = v?1:0; }
 
-    heart_state_t &get_state() { return this->state; }
+    bool get_interrupt_execution() override { return this->interrupt_sim; }
+
+    uint64_t get_state() override { return this->state.mstatus.backing.val; }
 
     void notify_phase(iss::arch_if::exec_phase p) override {
         if (p == iss::arch_if::ISTART)
@@ -88,7 +89,7 @@ public:
                 if (sizeof(reg_t) != 4) return iss::Err;
                 val = static_cast<reg_t>(time_val >> 32);
             }
-            return ret?Ok:Err;
+            return ret?iss::Ok:iss::Err;
 #else
         if((addr==iss::arch::time || addr==iss::arch::timeh)){
             uint64_t time_val = owner->mtime_i.read();
@@ -113,7 +114,7 @@ public:
         PLAT::wait_until(flags);
     }
 
-    void local_irq(short id, bool value) {
+    void local_irq(short id, bool value) override {
         reg_t mask = 0;
         switch (id) {
         case 3: // SW
@@ -141,7 +142,7 @@ public:
 
 private:
     sysc::tgfs::core_complex *const owner;
-    sc_event wfi_evt;
+    sc_core::sc_event wfi_evt;
 };
 
 

src/sysc/sc_core_adapter_if.h

@@ -0,0 +1,30 @@
+/*
+ * sc_core_adapter.h
+ *
+ *  Created on: Jul 5, 2023
+ *      Author: eyck
+ */
+
+#ifndef _SYSC_SC_CORE_ADAPTER_IF_H_
+#define _SYSC_SC_CORE_ADAPTER_IF_H_
+
+
+#include <scc/report.h>
+#include <util/ities.h>
+#include "core_complex.h"
+#include <iss/iss.h>
+#include <iss/vm_types.h>
+#include <iostream>
+
+struct sc_core_adapter_if {
+    virtual void set_mhartid(unsigned) = 0;
+    virtual uint32_t get_mode() = 0;
+    virtual uint64_t get_state() = 0;
+    virtual bool get_interrupt_execution() = 0;
+    virtual void set_interrupt_execution(bool v) = 0;
+    virtual void local_irq(short id, bool value) = 0;
+    virtual ~sc_core_adapter_if() = default;
+};
+
+
+#endif /* _SYSC_SC_CORE_ADAPTER_IF_H_ */

src/vm/interp/vm_tgc_c.cpp

@@ -388,7 +388,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = *PC + (int32_t)imm;
+                                        *(X+rd) = (uint32_t)(*PC + (int32_t)imm);
                                     }
                                 }
                             }
@@ -418,9 +418,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         if(rd !=  0) {
-                                            *(X+rd) = *PC +  4;
+                                            *(X+rd) = (uint32_t)(*PC +  4);
                                         }
-                                        *NEXT_PC = *PC + (int32_t)sext<21>(imm);
+                                        *NEXT_PC = (uint32_t)(*PC + (int32_t)sext<21>(imm));
                                         this->core.reg.last_branch = 1;
                                     }
                                 }
@@ -447,13 +447,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 0x1;
+                                    uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 0x1);
                                     if(new_pc % traits::INSTR_ALIGNMENT) {
                                         raise(0,  0);
                                     }
                                     else {
                                         if(rd !=  0) {
-                                            *(X+rd) = *PC +  4;
+                                            *(X+rd) = (uint32_t)(*PC +  4);
                                         }
                                         *NEXT_PC = new_pc & ~ 0x1;
                                         this->core.reg.last_branch = 1;
@@ -487,7 +487,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
+                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -520,7 +520,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
+                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -553,7 +553,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
+                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -586,7 +586,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
+                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -619,7 +619,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
+                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -652,7 +652,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
+                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -680,7 +680,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
+                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
                                     int8_t read_res = super::template read_mem<int8_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LB;
                                     int8_t res = (int8_t)read_res;
@@ -711,7 +711,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
+                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
                                     int16_t read_res = super::template read_mem<int16_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LH;
                                     int16_t res = (int16_t)read_res;
@@ -742,7 +742,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
+                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
                                     int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LW;
                                     int32_t res = (int32_t)read_res;
@@ -773,10 +773,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
+                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
                                     uint8_t read_res = super::template read_mem<uint8_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LBU;
-                                    uint8_t res = (uint8_t)read_res;
+                                    uint8_t res = read_res;
                                     if(rd !=  0) {
                                         *(X+rd) = (uint32_t)res;
                                     }
@@ -804,10 +804,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
+                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
                                     uint16_t read_res = super::template read_mem<uint16_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LHU;
-                                    uint16_t res = (uint16_t)read_res;
+                                    uint16_t res = read_res;
                                     if(rd !=  0) {
                                         *(X+rd) = (uint32_t)res;
                                     }
@@ -835,8 +835,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
-                                    super::template write_mem<uint8_t>(traits::MEM, store_address, (int8_t)*(X+rs2));
+                                    uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                    super::template write_mem<uint8_t>(traits::MEM, store_address, (uint8_t)*(X+rs2));
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_SB;
                                 }
                             }
@@ -862,8 +862,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
-                                    super::template write_mem<uint16_t>(traits::MEM, store_address, (int16_t)*(X+rs2));
+                                    uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                    super::template write_mem<uint16_t>(traits::MEM, store_address, (uint16_t)*(X+rs2));
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_SH;
                                 }
                             }
@@ -889,8 +889,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
-                                    super::template write_mem<uint32_t>(traits::MEM, store_address, (int32_t)*(X+rs2));
+                                    uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                    super::template write_mem<uint32_t>(traits::MEM, store_address, (uint32_t)*(X+rs2));
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_SW;
                                 }
                             }
@@ -917,7 +917,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = *(X+rs1) + (int16_t)sext<12>(imm);
+                                        *(X+rd) = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
                                     }
                                 }
                             }
@@ -1133,7 +1133,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (int32_t)*(X+rs1) >> shamt;
+                                        *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt);
                                     }
                                 }
                             }
@@ -1160,7 +1160,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = *(X+rs1) + *(X+rs2);
+                                        *(X+rd) = (uint32_t)(*(X+rs1) + *(X+rs2));
                                     }
                                 }
                             }
@@ -1187,7 +1187,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = *(X+rs1) - *(X+rs2);
+                                        *(X+rd) = (uint32_t)(*(X+rs1) - *(X+rs2));
                                     }
                                 }
                             }
@@ -1349,7 +1349,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN -  1));
+                                        *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN -  1)));
                                     }
                                 }
                             }
@@ -1426,7 +1426,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
-                                super::template write_mem<uint8_t>(traits::FENCE, traits::fence, pred <<  4 | succ);
+                                super::template write_mem<uint32_t>(traits::FENCE, traits::fence, (uint8_t)pred <<  4 | succ);
                                 if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_FENCE;
                             }
                 TRAP_FENCE:break;
@@ -1705,7 +1705,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
-                                super::template write_mem<uint16_t>(traits::FENCE, traits::fencei, imm);
+                                super::template write_mem<uint32_t>(traits::FENCE, traits::fencei, imm);
                                 if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_FENCE_I;
                             }
                 TRAP_FENCE_I:break;
@@ -1730,7 +1730,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
+                                    int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2));
                                     if(rd != 0) {
                                         *(X+rd) = (uint32_t)res;
                                     }
@@ -1758,7 +1758,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
+                                    int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2));
                                     if(rd != 0) {
                                         *(X+rd) = (uint32_t)(res >> traits::XLEN);
                                     }
@@ -1786,7 +1786,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    int64_t res = (int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2);
+                                    int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2));
                                     if(rd != 0) {
                                         *(X+rd) = (uint32_t)(res >> traits::XLEN);
                                     }
@@ -1814,7 +1814,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint64_t res = (uint64_t)*(X+rs1) * (uint64_t)*(X+rs2);
+                                    uint64_t res = (uint64_t)((uint64_t)*(X+rs1) * (uint64_t)*(X+rs2));
                                     if(rd != 0) {
                                         *(X+rd) = (uint32_t)(res >> traits::XLEN);
                                     }
@@ -1851,11 +1851,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                                 *(X+rd) = MMIN;
                                             }
                                             else {
-                                                *(X+rd) = dividend / divisor;
+                                                *(X+rd) = (uint32_t)(dividend / divisor);
                                             }
                                         }
                                         else {
-                                            *(X+rd) = (int32_t)- 1;
+                                            *(X+rd) = (uint32_t)- 1;
                                         }
                                     }
                                 }
@@ -1884,12 +1884,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 else {
                                     if(*(X+rs2) !=  0) {
                                         if(rd != 0) {
-                                            *(X+rd) = *(X+rs1) / *(X+rs2);
+                                            *(X+rd) = (uint32_t)(*(X+rs1) / *(X+rs2));
                                         }
                                     }
                                     else {
                                         if(rd != 0) {
-                                            *(X+rd) = (int32_t)- 1;
+                                            *(X+rd) = (uint32_t)- 1;
                                         }
                                     }
                                 }
@@ -1925,7 +1925,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         }
                                         else {
                                             if(rd != 0) {
-                                                *(X+rd) = (int32_t)*(X+rs1) % (int32_t)*(X+rs2);
+                                                *(X+rd) = (uint32_t)((int32_t)*(X+rs1) % (int32_t)*(X+rs2));
                                             }
                                         }
                                     }
@@ -1979,7 +1979,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     /* generate console output when executing the command */
                     auto mnemonic = fmt::format(
                         "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "caddi4spn"),
-                        fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+                        fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
@@ -1988,7 +1988,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                                 if(imm) {
-                                    *(X+rd +  8) = *(X+2) + imm;
+                                    *(X+rd +  8) = (uint32_t)(*(X+2) + imm);
                                 }
                                 else {
                                     raise(0,  2);
@@ -2012,10 +2012,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    uint32_t load_address = *(X+rs1 +  8) + uimm;
-                    int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
+                    uint32_t offs = (uint32_t)(*(X+rs1 +  8) + uimm);
+                    int32_t read_res = super::template read_mem<int32_t>(traits::MEM, offs);
                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CLW;
-                    *(X+rd +  8) = (int32_t)read_res;
+                    *(X+rd +  8) = (uint32_t)(int32_t)read_res;
                 }
                 TRAP_CLW:break;
             }// @suppress("No break at end of case")
@@ -2035,8 +2035,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    uint32_t load_address = *(X+rs1 +  8) + uimm;
-                    super::template write_mem<uint32_t>(traits::MEM, load_address, (int32_t)*(X+rs2 +  8));
+                    uint32_t offs = (uint32_t)(*(X+rs1 +  8) + uimm);
+                    super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2 +  8));
                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CSW;
                 }
                 TRAP_CSW:break;
@@ -2061,7 +2061,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rs1 !=  0) {
-                                        *(X+rs1) = *(X+rs1) + (int8_t)sext<6>(imm);
+                                        *(X+rs1) = (uint32_t)(*(X+rs1) + (int8_t)sext<6>(imm));
                                     }
                                 }
                             }
@@ -2094,8 +2094,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    *(X+1) = *PC +  2;
-                    *NEXT_PC = *PC + (int16_t)sext<12>(imm);
+                    *(X+1) = (uint32_t)(*PC +  2);
+                    *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm));
                     this->core.reg.last_branch = 1;
                 }
                 TRAP_CJAL:break;
@@ -2120,7 +2120,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (int8_t)sext<6>(imm);
+                                        *(X+rd) = (uint32_t)((int8_t)sext<6>(imm));
                                     }
                                 }
                             }
@@ -2145,7 +2145,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         raise(0,  2);
                     }
                     if(rd !=  0) {
-                        *(X+rd) = (int32_t)sext<18>(imm);
+                        *(X+rd) = (uint32_t)((int32_t)sext<18>(imm));
                     }
                 }
                 TRAP_CLUI:break;
@@ -2165,7 +2165,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                                 if(nzimm) {
-                                    *(X+2) = *(X+2) + (int16_t)sext<10>(nzimm);
+                                    *(X+2) = (uint32_t)(*(X+2) + (int16_t)sext<10>(nzimm));
                                 }
                                 else {
                                     raise(0,  2);
@@ -2222,11 +2222,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                     if(shamt) {
-                        *(X+rs1 +  8) = ((int32_t)*(X+rs1 +  8)) >> shamt;
+                        *(X+rs1 +  8) = (uint32_t)(((int32_t)*(X+rs1 +  8)) >> shamt);
                     }
                     else {
                         if(traits::XLEN ==  128) {
-                            *(X+rs1 +  8) = ((int32_t)*(X+rs1 +  8)) >>  64;
+                            *(X+rs1 +  8) = (uint32_t)(((int32_t)*(X+rs1 +  8)) >>  64);
                         }
                     }
                 }
@@ -2247,7 +2247,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    *(X+rs1 +  8) = *(X+rs1 +  8) & (int8_t)sext<6>(imm);
+                    *(X+rs1 +  8) = (uint32_t)(*(X+rs1 +  8) & (int8_t)sext<6>(imm));
                 }
                 TRAP_CANDI:break;
             }// @suppress("No break at end of case")
@@ -2266,7 +2266,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    *(X+rd +  8) = *(X+rd +  8) - *(X+rs2 +  8);
+                    *(X+rd +  8) = (uint32_t)(*(X+rd +  8) - *(X+rs2 +  8));
                 }
                 TRAP_CSUB:break;
             }// @suppress("No break at end of case")
@@ -2340,7 +2340,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                                *NEXT_PC = *PC + (int16_t)sext<12>(imm);
+                                *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm));
                                 this->core.reg.last_branch = 1;
                             }
                 TRAP_CJ:break;
@@ -2361,7 +2361,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                                 if(*(X+rs1 +  8) ==  0) {
-                                    *NEXT_PC = *PC + (int16_t)sext<9>(imm);
+                                    *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm));
                                     this->core.reg.last_branch = 1;
                                 }
                             }
@@ -2383,7 +2383,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                                 if(*(X+rs1 +  8) !=  0) {
-                                    *NEXT_PC = *PC + (int16_t)sext<9>(imm);
+                                    *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm));
                                     this->core.reg.last_branch = 1;
                                 }
                             }
@@ -2434,10 +2434,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         raise(0,  2);
                     }
                     else {
-                        int32_t read_res = super::template read_mem<int32_t>(traits::MEM, *(X+2) + uimm);
+                        uint32_t offs = (uint32_t)(*(X+2) + uimm);
+                        int32_t read_res = super::template read_mem<int32_t>(traits::MEM, offs);
                         if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CLWSP;
-                        int32_t res = read_res;
-                        *(X+rd) = (int32_t)res;
+                        *(X+rd) = (uint32_t)(int32_t)read_res;
                     }
                 }
                 TRAP_CLWSP:break;
@@ -2525,7 +2525,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = *(X+rd) + *(X+rs2);
+                                        *(X+rd) = (uint32_t)(*(X+rd) + *(X+rs2));
                                     }
                                 }
                             }
@@ -2550,7 +2550,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     uint32_t new_pc = *(X+rs1);
-                                    *(X+1) = *PC +  2;
+                                    *(X+1) = (uint32_t)(*PC +  2);
                                     *NEXT_PC = new_pc & ~ 0x1;
                                     this->core.reg.last_branch = 1;
                                 }
@@ -2589,7 +2589,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t offs = *(X+2) + uimm;
+                                    uint32_t offs = (uint32_t)(*(X+2) + uimm);
                                     super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2));
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CSWSP;
                                 }
@@ -2635,7 +2635,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
     return pc;
 }
 
-}
+} // namespace tgc_c
 
 template <>
 std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
@@ -2652,13 +2652,17 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            arch::tgc_c* lcpu = new arch::riscv_hart_m_p<arch::tgc_c>();
-            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
+        core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc_c>();
+		    auto vm = new interp::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
         }),
-        core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            arch::tgc_c* lcpu = new arch::riscv_hart_mu_p<arch::tgc_c>();
-            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
+        core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc_c>();
+		    auto vm = new interp::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
         })
 };
 }