Compare commits
2 Commits
feature/co
...
hotfix/lat
Author | SHA1 | Date | |
---|---|---|---|
66dc28c239 | |||
40470445f4 |
3
.gitignore
vendored
3
.gitignore
vendored
@ -30,5 +30,4 @@ language.settings.xml
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/.gdbinit
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/*.out
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/dump.json
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/*.yaml
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/*.json
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/src-gen/
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|
3
.gitmodules
vendored
Normal file
3
.gitmodules
vendored
Normal file
@ -0,0 +1,3 @@
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[submodule "gen_input/CoreDSL-Instruction-Set-Description"]
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path = gen_input/CoreDSL-Instruction-Set-Description
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url = ../CoreDSL-Instruction-Set-Description.git
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270
CMakeLists.txt
270
CMakeLists.txt
@ -1,23 +1,20 @@
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cmake_minimum_required(VERSION 3.12)
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###############################################################################
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#
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###############################################################################
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project(dbt-rise-tgc VERSION 1.0.0)
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project("riscv" VERSION 1.0.0)
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include(GNUInstallDirs)
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find_package(elfio QUIET)
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find_package(Boost COMPONENTS coroutine)
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find_package(jsoncpp)
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conan_basic_setup()
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find_package(Boost COMPONENTS program_options system thread filesystem REQUIRED)
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if(WITH_LLVM)
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if(DEFINED ENV{LLVM_HOME})
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find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
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endif(DEFINED ENV{LLVM_HOME})
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find_package(LLVM REQUIRED CONFIG)
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message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
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message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
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llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
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if(DEFINED ENV{LLVM_HOME})
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find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm)
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endif(DEFINED ENV{LLVM_HOME})
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find_package(LLVM REQUIRED CONFIG)
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message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
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message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
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llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
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endif()
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#Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
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@ -29,195 +26,98 @@ endif()
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add_subdirectory(softfloat)
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set(LIB_SOURCES
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src/iss/plugin/instruction_count.cpp
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src/iss/arch/tgc_c.cpp
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src/vm/interp/vm_tgc_c.cpp
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src/vm/fp_functions.cpp
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)
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# library files
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if(TARGET ${CORE_NAME}_cpp)
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list(APPEND LIB_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
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else()
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FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
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FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
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list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
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foreach(FILEPATH ${GEN_ISS_SOURCES})
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get_filename_component(CORE ${FILEPATH} NAME_WE)
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string(TOUPPER ${CORE} CORE)
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list(APPEND LIB_DEFINES CORE_${CORE})
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endforeach()
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message("Defines are ${LIB_DEFINES}")
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endif()
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if(TARGET RapidJSON OR TARGET RapidJSON::RapidJSON)
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list(APPEND LIB_SOURCES src/iss/plugin/cycle_estimate.cpp src/iss/plugin/pctrace.cpp)
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endif()
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FILE(GLOB RiscVSCHeaders ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*.h ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*/*.h)
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set(LIB_HEADERS ${RiscVSCHeaders} )
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set(LIB_SOURCES
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src/iss/tgf_b.cpp
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src/iss/tgf_c.cpp
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src/vm/fp_functions.cpp
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src/vm/tcc/vm_tgf_b.cpp
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src/vm/tcc/vm_tgf_c.cpp
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src/vm/interp/vm_tgf_b.cpp
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src/vm/interp/vm_tgf_c.cpp
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src/plugin/instruction_count.cpp
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src/plugin/cycle_estimate.cpp
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)
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if(WITH_LLVM)
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FILE(GLOB LLVM_GEN_SOURCES
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${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp
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)
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list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
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endif()
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if(WITH_TCC)
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FILE(GLOB TCC_GEN_SOURCES
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${CMAKE_CURRENT_SOURCE_DIR}/src/vm/tcc/vm_*.cpp
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)
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list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
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set(LIB_SOURCES ${LIB_SOURCES}
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src/vm/llvm/fp_impl.cpp
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src/vm/llvm/vm_tgf_b.cpp
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src/vm/llvm/vm_tgf_c.cpp
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)
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endif()
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# Define the library
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add_library(${PROJECT_NAME} ${LIB_SOURCES})
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# list code gen dependencies
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if(TARGET ${CORE_NAME}_cpp)
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add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp)
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endif()
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if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
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target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
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elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
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target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
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endif()
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target_include_directories(${PROJECT_NAME} PUBLIC src)
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target_include_directories(${PROJECT_NAME} PUBLIC src-gen)
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target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util Boost::coroutine)
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if(TARGET jsoncpp::jsoncpp)
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target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp::jsoncpp)
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else()
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target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp)
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endif()
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if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU" AND BUILD_SHARED_LIBS)
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target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-rise-core -Wl,--no-whole-archive)
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else()
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target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-core)
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endif()
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if(TARGET elfio::elfio)
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target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
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else()
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message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
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endif()
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if(TARGET lz4::lz4)
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target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_LZ4)
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target_link_libraries(${PROJECT_NAME} PUBLIC lz4::lz4)
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endif()
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if(TARGET RapidJSON::RapidJSON)
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target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON::RapidJSON)
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elseif(TARGET RapidJSON)
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target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON)
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endif()
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set_target_properties(${PROJECT_NAME} PROPERTIES
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add_library(riscv SHARED ${LIB_SOURCES})
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target_compile_options(riscv PRIVATE -Wno-shift-count-overflow)
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target_include_directories(riscv PUBLIC incl ../external/elfio)
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target_link_libraries(riscv PUBLIC softfloat scc-util jsoncpp)
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target_link_libraries(riscv PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
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set_target_properties(riscv PROPERTIES
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VERSION ${PROJECT_VERSION}
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FRAMEWORK FALSE
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PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
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)
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install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
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EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
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ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
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RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
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LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib
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FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
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||||
PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
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INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
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)
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install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME}
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DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # target directory
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FILES_MATCHING # install only matched files
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PATTERN "*.h" # select header files
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)
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###############################################################################
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#
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###############################################################################
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project(tgc-sim)
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find_package(Boost COMPONENTS program_options thread REQUIRED)
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add_executable(${PROJECT_NAME} src/main.cpp)
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if(TARGET ${CORE_NAME}_cpp)
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list(APPEND TGC_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
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else()
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FILE(GLOB TGC_SOURCES
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${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
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${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
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)
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list(APPEND TGC_SOURCES ${GEN_SOURCES})
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if(SystemC_FOUND)
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add_library(riscv_sc src/sysc/core_complex.cpp)
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target_compile_definitions(riscv_sc PUBLIC WITH_SYSTEMC)
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target_include_directories(riscv_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
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||||
|
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if(SCV_FOUND)
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target_compile_definitions(riscv_sc PUBLIC WITH_SCV)
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target_include_directories(riscv_sc PUBLIC ${SCV_INCLUDE_DIRS})
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endif()
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target_link_libraries(riscv_sc PUBLIC riscv scc )
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||||
if(WITH_LLVM)
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||||
target_link_libraries(riscv_sc PUBLIC ${llvm_libs})
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||||
endif()
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||||
target_link_libraries(riscv_sc PUBLIC ${Boost_LIBRARIES} )
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||||
set_target_properties(riscv_sc PROPERTIES
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||||
VERSION ${PROJECT_VERSION}
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||||
FRAMEWORK FALSE
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||||
PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
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||||
)
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||||
endif()
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||||
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||||
foreach(F IN LISTS TGC_SOURCES)
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||||
if (${F} MATCHES ".*/arch/([^/]*)\.cpp")
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||||
string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
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||||
string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
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||||
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
|
||||
endif()
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||||
endforeach()
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||||
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||||
project("riscv-sim")
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||||
add_executable(riscv-sim src/main.cpp)
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||||
# This sets the include directory for the reference project. This is the -I flag in gcc.
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||||
target_include_directories(riscv-sim PRIVATE ../external/libGIS)
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||||
if(WITH_LLVM)
|
||||
target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
|
||||
target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
|
||||
endif()
|
||||
if(WITH_TCC)
|
||||
target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
|
||||
target_compile_definitions(riscv-sim PRIVATE WITH_LLVM)
|
||||
target_link_libraries(riscv-sim PUBLIC ${llvm_libs})
|
||||
endif()
|
||||
# Links the target exe against the libraries
|
||||
target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc)
|
||||
if(TARGET Boost::program_options)
|
||||
target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options)
|
||||
else()
|
||||
target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY})
|
||||
endif()
|
||||
target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS})
|
||||
target_link_libraries(riscv-sim riscv)
|
||||
target_link_libraries(riscv-sim jsoncpp)
|
||||
target_link_libraries(riscv-sim external)
|
||||
target_link_libraries(riscv-sim ${Boost_LIBRARIES} )
|
||||
if (Tcmalloc_FOUND)
|
||||
target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES})
|
||||
target_link_libraries(riscv-sim ${Tcmalloc_LIBRARIES})
|
||||
endif(Tcmalloc_FOUND)
|
||||
|
||||
install(TARGETS tgc-sim
|
||||
install(TARGETS riscv riscv-sim
|
||||
EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
|
||||
ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
|
||||
RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
|
||||
LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib
|
||||
FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
|
||||
PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
|
||||
ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # static lib
|
||||
RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} COMPONENT libs # binaries
|
||||
LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # shared lib
|
||||
FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac
|
||||
PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} COMPONENT devel # headers for mac (note the different component -> different package)
|
||||
INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
|
||||
)
|
||||
###############################################################################
|
||||
#
|
||||
###############################################################################
|
||||
if(TARGET scc-sysc)
|
||||
project(dbt-rise-tgc_sc VERSION 1.0.0)
|
||||
add_library(${PROJECT_NAME}
|
||||
src/sysc/core_complex.cpp
|
||||
src/sysc/register_tgc_c.cpp
|
||||
)
|
||||
target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
|
||||
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
|
||||
foreach(F IN LISTS TGC_SOURCES)
|
||||
if (${F} MATCHES ".*/arch/([^/]*)\.cpp")
|
||||
string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
|
||||
string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
|
||||
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
|
||||
endif()
|
||||
endforeach()
|
||||
target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
|
||||
if(WITH_LLVM)
|
||||
target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
|
||||
endif()
|
||||
|
||||
set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
|
||||
set_target_properties(${PROJECT_NAME} PROPERTIES
|
||||
VERSION ${PROJECT_VERSION}
|
||||
FRAMEWORK FALSE
|
||||
PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
|
||||
)
|
||||
install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
|
||||
EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
|
||||
ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
|
||||
RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
|
||||
LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib
|
||||
FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
|
||||
PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc # headers for mac (note the different component -> different package)
|
||||
INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
|
||||
)
|
||||
endif()
|
||||
|
||||
|
||||
|
||||
#
|
||||
# SYSTEM PACKAGING (RPM, TGZ, ...)
|
||||
# _____________________________________________________________________________
|
||||
|
||||
#include(CPackConfig)
|
||||
|
||||
#
|
||||
# CMAKE PACKAGING (for other CMake projects to use this one easily)
|
||||
# _____________________________________________________________________________
|
||||
|
||||
#include(PackageConfigurator)
|
||||
|
537
TGC_C_instr.yaml
537
TGC_C_instr.yaml
@ -1,537 +0,0 @@
|
||||
|
||||
RV32I:
|
||||
- LUI:
|
||||
encoding: 0b00000000000000000000000000110111
|
||||
mask: 0b00000000000000000000000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- AUIPC:
|
||||
encoding: 0b00000000000000000000000000010111
|
||||
mask: 0b00000000000000000000000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- JAL:
|
||||
encoding: 0b00000000000000000000000001101111
|
||||
mask: 0b00000000000000000000000001111111
|
||||
attributes: [[name:no_cont]]
|
||||
size: 32
|
||||
branch: true
|
||||
delay: 1
|
||||
- JALR:
|
||||
encoding: 0b00000000000000000000000001100111
|
||||
mask: 0b00000000000000000111000001111111
|
||||
attributes: [[name:no_cont]]
|
||||
size: 32
|
||||
branch: true
|
||||
delay: 1
|
||||
- BEQ:
|
||||
encoding: 0b00000000000000000000000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
attributes: [[name:no_cont], [name:cond]]
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
- BNE:
|
||||
encoding: 0b00000000000000000001000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
attributes: [[name:no_cont], [name:cond]]
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
- BLT:
|
||||
encoding: 0b00000000000000000100000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
attributes: [[name:no_cont], [name:cond]]
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
- BGE:
|
||||
encoding: 0b00000000000000000101000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
attributes: [[name:no_cont], [name:cond]]
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
- BLTU:
|
||||
encoding: 0b00000000000000000110000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
attributes: [[name:no_cont], [name:cond]]
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
- BGEU:
|
||||
encoding: 0b00000000000000000111000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
attributes: [[name:no_cont], [name:cond]]
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
- LB:
|
||||
encoding: 0b00000000000000000000000000000011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- LH:
|
||||
encoding: 0b00000000000000000001000000000011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- LW:
|
||||
encoding: 0b00000000000000000010000000000011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- LBU:
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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encoding: 0b00000000000000000010000000110011
|
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mask: 0b11111110000000000111000001111111
|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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mask: 0b11111110000000000111000001111111
|
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|
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|
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|
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|
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|
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|
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|
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mask: 0b11111110000000000111000001111111
|
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|
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branch: false
|
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delay: 1
|
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|
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encoding: 0b00000000000000000000000000001111
|
||||
mask: 0b00000000000000000111000001111111
|
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size: 32
|
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branch: false
|
||||
delay: 1
|
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|
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encoding: 0b00000000000000000000000001110011
|
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mask: 0b11111111111111111111111111111111
|
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attributes: [[name:no_cont]]
|
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size: 32
|
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branch: false
|
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delay: 1
|
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- EBREAK:
|
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encoding: 0b00000000000100000000000001110011
|
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mask: 0b11111111111111111111111111111111
|
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attributes: [[name:no_cont]]
|
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size: 32
|
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branch: false
|
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delay: 1
|
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- MRET:
|
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encoding: 0b00110000001000000000000001110011
|
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mask: 0b11111111111111111111111111111111
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attributes: [[name:no_cont]]
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size: 32
|
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branch: false
|
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delay: 1
|
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- WFI:
|
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encoding: 0b00010000010100000000000001110011
|
||||
mask: 0b11111111111111111111111111111111
|
||||
size: 32
|
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branch: false
|
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delay: 1
|
||||
Zicsr:
|
||||
- CSRRW:
|
||||
encoding: 0b00000000000000000001000001110011
|
||||
mask: 0b00000000000000000111000001111111
|
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size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- CSRRS:
|
||||
encoding: 0b00000000000000000010000001110011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- CSRRC:
|
||||
encoding: 0b00000000000000000011000001110011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- CSRRWI:
|
||||
encoding: 0b00000000000000000101000001110011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- CSRRSI:
|
||||
encoding: 0b00000000000000000110000001110011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- CSRRCI:
|
||||
encoding: 0b00000000000000000111000001110011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
Zifencei:
|
||||
- FENCE_I:
|
||||
encoding: 0b00000000000000000001000000001111
|
||||
mask: 0b00000000000000000111000001111111
|
||||
attributes: [[name:flush]]
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
RV32M:
|
||||
- MUL:
|
||||
encoding: 0b00000010000000000000000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- MULH:
|
||||
encoding: 0b00000010000000000001000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- MULHSU:
|
||||
encoding: 0b00000010000000000010000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- MULHU:
|
||||
encoding: 0b00000010000000000011000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- DIV:
|
||||
encoding: 0b00000010000000000100000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- DIVU:
|
||||
encoding: 0b00000010000000000101000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- REM:
|
||||
encoding: 0b00000010000000000110000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
- REMU:
|
||||
encoding: 0b00000010000000000111000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
RV32IC:
|
||||
- CADDI4SPN:
|
||||
encoding: 0b0000000000000000
|
||||
mask: 0b1110000000000011
|
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size: 16
|
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branch: false
|
||||
delay: 1
|
||||
- CLW:
|
||||
encoding: 0b0100000000000000
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
- CSW:
|
||||
encoding: 0b1100000000000000
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
- CADDI:
|
||||
encoding: 0b0000000000000001
|
||||
mask: 0b1110000000000011
|
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size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
- CNOP:
|
||||
encoding: 0b0000000000000001
|
||||
mask: 0b1110111110000011
|
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size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
- CJAL:
|
||||
encoding: 0b0010000000000001
|
||||
mask: 0b1110000000000011
|
||||
attributes: [[name:no_cont]]
|
||||
size: 16
|
||||
branch: true
|
||||
delay: 1
|
||||
- CLI:
|
||||
encoding: 0b0100000000000001
|
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mask: 0b1110000000000011
|
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size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
- CLUI:
|
||||
encoding: 0b0110000000000001
|
||||
mask: 0b1110000000000011
|
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size: 16
|
||||
branch: false
|
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delay: 1
|
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- CADDI16SP:
|
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encoding: 0b0110000100000001
|
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mask: 0b1110111110000011
|
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|
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branch: false
|
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delay: 1
|
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- CSRLI:
|
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encoding: 0b1000000000000001
|
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mask: 0b1111110000000011
|
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size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
- CSRAI:
|
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encoding: 0b1000010000000001
|
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mask: 0b1111110000000011
|
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|
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|
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delay: 1
|
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|
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encoding: 0b1000100000000001
|
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mask: 0b1110110000000011
|
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|
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|
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|
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|
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encoding: 0b1000110000000001
|
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mask: 0b1111110001100011
|
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|
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|
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|
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|
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encoding: 0b1000110000100001
|
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mask: 0b1111110001100011
|
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|
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|
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delay: 1
|
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- COR:
|
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encoding: 0b1000110001000001
|
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mask: 0b1111110001100011
|
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size: 16
|
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branch: false
|
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delay: 1
|
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- CAND:
|
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encoding: 0b1000110001100001
|
||||
mask: 0b1111110001100011
|
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|
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branch: false
|
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delay: 1
|
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- CJ:
|
||||
encoding: 0b1010000000000001
|
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mask: 0b1110000000000011
|
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attributes: [[name:no_cont]]
|
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size: 16
|
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branch: true
|
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delay: 1
|
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- CBEQZ:
|
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encoding: 0b1100000000000001
|
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mask: 0b1110000000000011
|
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attributes: [[name:no_cont], [name:cond]]
|
||||
size: 16
|
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branch: true
|
||||
delay: [1,1]
|
||||
- CBNEZ:
|
||||
encoding: 0b1110000000000001
|
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mask: 0b1110000000000011
|
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attributes: [[name:no_cont], [name:cond]]
|
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size: 16
|
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branch: true
|
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delay: [1,1]
|
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- CSLLI:
|
||||
encoding: 0b0000000000000010
|
||||
mask: 0b1111000000000011
|
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size: 16
|
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branch: false
|
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delay: 1
|
||||
- CLWSP:
|
||||
encoding: 0b0100000000000010
|
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mask: 0b1110000000000011
|
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size: 16
|
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branch: false
|
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delay: 1
|
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- CMV:
|
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encoding: 0b1000000000000010
|
||||
mask: 0b1111000000000011
|
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size: 16
|
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branch: false
|
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delay: 1
|
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- CJR:
|
||||
encoding: 0b1000000000000010
|
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mask: 0b1111000001111111
|
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attributes: [[name:no_cont]]
|
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size: 16
|
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branch: true
|
||||
delay: 1
|
||||
- CADD:
|
||||
encoding: 0b1001000000000010
|
||||
mask: 0b1111000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
- CJALR:
|
||||
encoding: 0b1001000000000010
|
||||
mask: 0b1111000001111111
|
||||
attributes: [[name:no_cont]]
|
||||
size: 16
|
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branch: true
|
||||
delay: 1
|
||||
- CEBREAK:
|
||||
encoding: 0b1001000000000010
|
||||
mask: 0b1111111111111111
|
||||
attributes: [[name:no_cont]]
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
- CSWSP:
|
||||
encoding: 0b1100000000000010
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
- DII:
|
||||
encoding: 0b0000000000000000
|
||||
mask: 0b1111111111111111
|
||||
attributes: [[name:no_cont]]
|
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size: 16
|
||||
branch: false
|
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delay: 1
|
||||
|
3
contrib/.gitignore
vendored
3
contrib/.gitignore
vendored
@ -1,3 +0,0 @@
|
||||
/results
|
||||
/cwr
|
||||
/*.xml
|
@ -1,43 +0,0 @@
|
||||
# Notes
|
||||
|
||||
* requires conan version 1.59
|
||||
* requires decent cmake version 3.23
|
||||
|
||||
Setup for tcsh:
|
||||
|
||||
```
|
||||
git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
|
||||
cd TGC-ISS/
|
||||
setenv TGFS_INSTALL_ROOT `pwd`/install
|
||||
setenv COWAREHOME <your SNPS PA installation>
|
||||
setenv SNPSLMD_LICENSE_FILE <your SNPS PA license file>
|
||||
source $COWAREHOME/SLS/linux/setup.csh pae
|
||||
setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
|
||||
setenv PATH $COWAREHOME/common/bin/:${PATH}
|
||||
setenv CC $COWAREHOME/SLS/linux/common/bin/gcc
|
||||
setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
|
||||
cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
|
||||
-DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
|
||||
cmake --build build/PA --target install -j16
|
||||
cd dbt-rise-tgc/contrib
|
||||
# import the TGC core itself
|
||||
pct tgc_import_tb.tcl
|
||||
```
|
||||
|
||||
Setup for bash:
|
||||
|
||||
```
|
||||
git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
|
||||
cd TGC-ISS/
|
||||
export TGFS_INSTALL_ROOT `pwd`/install
|
||||
module load tools/pa/T-2022.06
|
||||
export SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM=1
|
||||
export CC=$COWAREHOME/SLS/linux/common/bin/gcc
|
||||
export CXX=$COWAREHOME/SLS/linux/common/bin/g++
|
||||
cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
|
||||
-DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
|
||||
cmake --build build/PA --target install -j16
|
||||
cd dbt-rise-tgc/contrib
|
||||
# import the TGC core itself
|
||||
pct tgc_import_tb.tcl
|
||||
```
|
@ -1,30 +0,0 @@
|
||||
namespace eval Specification {
|
||||
proc buildproc { args } {
|
||||
global env
|
||||
variable installDir
|
||||
variable compiler
|
||||
variable compiler [::scsh::get_backend_compiler]
|
||||
# set target $machine
|
||||
set target [::scsh::machine]
|
||||
set linkerOptions ""
|
||||
set preprocessorOptions ""
|
||||
set libversion $compiler
|
||||
switch -exact -- $target {
|
||||
"linux" {
|
||||
set install_dir $::env(TGFS_INSTALL_ROOT)
|
||||
set incldir "${install_dir}/include"
|
||||
set libdir "${install_dir}/lib64"
|
||||
set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
|
||||
# Set the Linker paths.
|
||||
set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc -lscc-sysc"]
|
||||
}
|
||||
default {
|
||||
puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"
|
||||
return
|
||||
}
|
||||
}
|
||||
::scsh::cwr_append_ipsimbld_opts preprocessor "$preprocessorOptions"
|
||||
::scsh::cwr_append_ipsimbld_opts linker "$linkerOptions"
|
||||
}
|
||||
::scsh::add_build_callback [namespace current]::buildproc
|
||||
}
|
2092
contrib/hello.dis
2092
contrib/hello.dis
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
Before Width: | Height: | Size: 25 KiB |
@ -1,4 +0,0 @@
|
||||
|
||||
#include "sysc/core_complex.h"
|
||||
|
||||
void modules() { sysc::tgfs::core_complex i_core_complex("core_complex"); }
|
@ -1,50 +0,0 @@
|
||||
#############################################################################
|
||||
#
|
||||
#############################################################################
|
||||
proc getScriptDirectory {} {
|
||||
set dispScriptFile [file normalize [info script]]
|
||||
set scriptFolder [file dirname $dispScriptFile]
|
||||
return $scriptFolder
|
||||
}
|
||||
set hardware /HARDWARE/HW/HW
|
||||
|
||||
set scriptDir [getScriptDirectory]
|
||||
set top_design_name core_complex
|
||||
set encap_name sysc::tgfs::${top_design_name}
|
||||
set clocks clk_i
|
||||
set resets rst_i
|
||||
set model_prefix "i_"
|
||||
set model_postfix ""
|
||||
|
||||
::pct::new_project
|
||||
::pct::open_library TLM2_PL
|
||||
::pct::clear_systemc_defines
|
||||
::pct::clear_systemc_include_path
|
||||
::pct::add_to_systemc_include_path $::env(TGFS_INSTALL_ROOT)/include
|
||||
::pct::set_import_protocol_generation_flag false
|
||||
::pct::set_update_existing_encaps_flag true
|
||||
::pct::set_dynamic_port_arrays_flag true
|
||||
::pct::set_import_scml_properties_flag true
|
||||
::pct::set_import_encap_prop_as_extra_prop_flag true
|
||||
::pct::load_modules --set-category modules ${scriptDir}/tgc_import.cc
|
||||
|
||||
# Set Port Protocols correctly
|
||||
set block ${top_design_name}
|
||||
foreach clock ${clocks} {
|
||||
::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${clock} SYSTEM_LIBRARY:CLOCK
|
||||
}
|
||||
foreach reset ${resets} {
|
||||
::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
|
||||
}
|
||||
#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
|
||||
|
||||
# Set compile settings and look
|
||||
set block SYSTEM_LIBRARY:${top_design_name}
|
||||
::pct::set_encap_build_script $block/${encap_name} $scriptDir/build.tcl
|
||||
::pct::set_background_color_rgb $block 255 255 255 255
|
||||
::pct::create_instance SYSTEM_LIBRARY:${top_design_name} ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${encap_name} ${encap_name}()
|
||||
::pct::set_bounds i_${top_design_name} 200 300 100 400
|
||||
::pct::set_image i_${top_design_name} "$scriptDir/minres.png" center center false true
|
||||
|
||||
# export the result as component
|
||||
::pct::export_system_library ${top_design_name} ${top_design_name}.xml
|
@ -1,71 +0,0 @@
|
||||
source tgc_import.tcl
|
||||
set hardware /HARDWARE/HW/HW
|
||||
set FW_name ${scriptDir}/hello.elf
|
||||
|
||||
puts "instantiate testbench elements"
|
||||
::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
|
||||
::pct::set_param_value i_Memory_Generic/MEM:protocol {Protocol Common Parameters} address_width 30
|
||||
::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
|
||||
::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
|
||||
::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
|
||||
::pct::set_bounds i_Memory_Generic 1000 300 100 100
|
||||
|
||||
::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
|
||||
::BLWizard::generateFramework i_Bus SBLTLM2FT * {} \
|
||||
{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
|
||||
::pct::set_bounds i_Bus 700 300 100 400
|
||||
::pct::create_connection C_ibus i_core_complex/ibus i_Bus/i_core_complex_ibus
|
||||
::pct::set_location_on_owner i_Bus/i_core_complex_ibus 10
|
||||
::pct::create_connection C_dbus i_core_complex/dbus i_Bus/i_core_complex_dbus
|
||||
::pct::set_location_on_owner i_Bus/i_core_complex_dbus 10
|
||||
::pct::create_connection C_mem i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
|
||||
|
||||
puts "instantiating clock manager"
|
||||
set clock "Clk"
|
||||
::hw::create_hw_instance "" GenericIPlib:ClockGenerator ${clock}_clock
|
||||
::pct::set_bounds ${clock}_clock 100 100 100 100
|
||||
::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period 1000
|
||||
::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period_unit sc_core::SC_PS
|
||||
|
||||
puts "instantiating reset manager"
|
||||
set reset "Rst"
|
||||
::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
|
||||
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 0
|
||||
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
|
||||
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
|
||||
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
|
||||
::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
|
||||
::pct::set_bounds ${reset}_reset 300 100 100 100
|
||||
|
||||
puts "connecting reset/clock"
|
||||
::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
|
||||
::pct::add_ports_to_connection C_clk i_Bus/Clk
|
||||
::pct::add_ports_to_connection C_clk i_Memory_Generic/CLK
|
||||
::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
|
||||
::pct::add_ports_to_connection C_rst i_Bus/Rst
|
||||
|
||||
puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
|
||||
::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name}
|
||||
::pct::set_address $hardware/i_${top_design_name}/ibus:i_Memory_Generic/MEM 0x0
|
||||
::pct::set_address $hardware/i_${top_design_name}/dbus:i_Memory_Generic/MEM 0x0
|
||||
::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 }
|
||||
|
||||
::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
|
||||
::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
|
||||
::pct::create_simulation_build_config Debug
|
||||
::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
|
||||
# add build settings and save design for next steps
|
||||
#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
|
||||
#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
|
||||
|
||||
#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
|
||||
#::simulation::run_simulation Simulation
|
||||
|
||||
#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
|
||||
#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
|
||||
#::pct::export_system "export"
|
||||
#::cd "export"
|
||||
#::scsh::open-project
|
||||
#::scsh::build
|
||||
#::scsh::elab sim
|
||||
::pct::save_system testbench.xml
|
1
gen_input/.gitignore
vendored
1
gen_input/.gitignore
vendored
@ -1,2 +1 @@
|
||||
/src-gen/
|
||||
/CoreDSL-Instruction-Set-Description
|
||||
|
1
gen_input/CoreDSL-Instruction-Set-Description
Submodule
1
gen_input/CoreDSL-Instruction-Set-Description
Submodule
Submodule gen_input/CoreDSL-Instruction-Set-Description added at 3bb3763e92
@ -1,13 +0,0 @@
|
||||
import "ISA/RV32I.core_desc"
|
||||
import "ISA/RVM.core_desc"
|
||||
import "ISA/RVC.core_desc"
|
||||
|
||||
Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
|
||||
architectural_state {
|
||||
XLEN=32;
|
||||
// definitions for the architecture wrapper
|
||||
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
|
||||
unsigned int MISA_VAL = 0b01000000000000000001000100000100;
|
||||
unsigned int MARCHID_VAL = 0x80000003;
|
||||
}
|
||||
}
|
28
gen_input/TGFS.core_desc
Normal file
28
gen_input/TGFS.core_desc
Normal file
@ -0,0 +1,28 @@
|
||||
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
|
||||
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
|
||||
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
|
||||
|
||||
Core TGF_B provides RV32I {
|
||||
constants {
|
||||
XLEN:=32;
|
||||
PCLEN:=32;
|
||||
// definitions for the architecture wrapper
|
||||
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
|
||||
MISA_VAL:=0b01000000000000000000000100000000;
|
||||
PGSIZE := 0x1000; //1 << 12;
|
||||
PGMASK := 0xfff; //PGSIZE-1
|
||||
}
|
||||
}
|
||||
|
||||
Core TGF_C provides RV32I, RV32M, RV32IC {
|
||||
constants {
|
||||
XLEN:=32;
|
||||
PCLEN:=32;
|
||||
MUL_LEN:=64;
|
||||
// definitions for the architecture wrapper
|
||||
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
|
||||
MISA_VAL:=0b01000000000000000001000100000100;
|
||||
PGSIZE := 0x1000; //1 << 12;
|
||||
PGMASK := 0xfff; //PGSIZE-1
|
||||
}
|
||||
}
|
74
gen_input/minres_rv.core_desc
Normal file
74
gen_input/minres_rv.core_desc
Normal file
@ -0,0 +1,74 @@
|
||||
import "RV32I.core_desc"
|
||||
import "RV64I.core_desc"
|
||||
import "RVM.core_desc"
|
||||
import "RVA.core_desc"
|
||||
import "RVC.core_desc"
|
||||
import "RVF.core_desc"
|
||||
import "RVD.core_desc"
|
||||
|
||||
|
||||
Core MNRV32 provides RV32I, RV32IC {
|
||||
constants {
|
||||
XLEN:=32;
|
||||
PCLEN:=32;
|
||||
// definitions for the architecture wrapper
|
||||
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
|
||||
MISA_VAL:=0b01000000000101000001000100000101;
|
||||
PGSIZE := 0x1000; //1 << 12;
|
||||
PGMASK := 0xfff; //PGSIZE-1
|
||||
}
|
||||
}
|
||||
|
||||
Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
|
||||
constants {
|
||||
XLEN:=32;
|
||||
PCLEN:=32;
|
||||
MUL_LEN:=64;
|
||||
// definitions for the architecture wrapper
|
||||
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
|
||||
MISA_VAL:=0b01000000000101000001000100000101;
|
||||
PGSIZE := 0x1000; //1 << 12;
|
||||
PGMASK := 0xfff; //PGSIZE-1
|
||||
}
|
||||
}
|
||||
|
||||
Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
|
||||
constants {
|
||||
XLEN:=32;
|
||||
FLEN:=64;
|
||||
PCLEN:=32;
|
||||
MUL_LEN:=64;
|
||||
// definitions for the architecture wrapper
|
||||
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
|
||||
MISA_VAL:=0b01000000000101000001000100101101;
|
||||
PGSIZE := 0x1000; //1 << 12;
|
||||
PGMASK := 0xfff; //PGSIZE-1
|
||||
}
|
||||
}
|
||||
|
||||
Core RV64I provides RV64I {
|
||||
constants {
|
||||
XLEN:=64;
|
||||
PCLEN:=64;
|
||||
// definitions for the architecture wrapper
|
||||
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
|
||||
MISA_VAL:=0b10000000000001000000000100000000;
|
||||
PGSIZE := 0x1000; //1 << 12;
|
||||
PGMASK := 0xfff; //PGSIZE-1
|
||||
}
|
||||
}
|
||||
|
||||
Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC {
|
||||
constants {
|
||||
XLEN:=64;
|
||||
FLEN:=64;
|
||||
PCLEN:=64;
|
||||
MUL_LEN:=128;
|
||||
// definitions for the architecture wrapper
|
||||
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
|
||||
MISA_VAL:=0b01000000000101000001000100101101;
|
||||
PGSIZE := 0x1000; //1 << 12;
|
||||
PGMASK := 0xfff; //PGSIZE-1
|
||||
}
|
||||
}
|
||||
|
@ -1,12 +0,0 @@
|
||||
{
|
||||
"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
|
||||
{
|
||||
"name" : "${instr.name}",
|
||||
"size" : ${instr.length},
|
||||
"encoding": "${instr.encoding}",
|
||||
"mask": "${instr.mask}",
|
||||
"branch": ${instr.modifiesPC},
|
||||
"delay" : ${instr.isConditional?"[1,1]":"1"}
|
||||
}<%}%>
|
||||
]
|
||||
}
|
@ -1,86 +0,0 @@
|
||||
#include "${coreDef.name.toLowerCase()}.h"
|
||||
#include <vector>
|
||||
#include <array>
|
||||
#include <cstdlib>
|
||||
#include <algorithm>
|
||||
|
||||
namespace iss {
|
||||
namespace arch {
|
||||
namespace {
|
||||
// according to
|
||||
// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
|
||||
#ifdef __GCC__
|
||||
constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
|
||||
#elif __cplusplus < 201402L
|
||||
constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
|
||||
constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
|
||||
#else
|
||||
constexpr size_t bit_count(uint32_t u) {
|
||||
size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
|
||||
return ((uCount + (uCount >> 3)) & 030707070707) % 63;
|
||||
}
|
||||
#endif
|
||||
|
||||
using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
|
||||
|
||||
/****************************************************************************
|
||||
* start opcode definitions
|
||||
****************************************************************************/
|
||||
struct instruction_desriptor {
|
||||
size_t length;
|
||||
uint32_t value;
|
||||
uint32_t mask;
|
||||
opcode_e op;
|
||||
};
|
||||
|
||||
const std::array<instruction_desriptor, ${instructions.size}> instr_descr = {{
|
||||
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
|
||||
{${instr.length}, ${instr.encoding}, ${instr.mask}, opcode_e::${instr.instruction.name}},<%}%>
|
||||
}};
|
||||
|
||||
}
|
||||
|
||||
template<>
|
||||
struct instruction_decoder<${coreDef.name.toLowerCase()}> {
|
||||
using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
|
||||
using code_word_t=traits<${coreDef.name.toLowerCase()}>::code_word_t;
|
||||
|
||||
struct instruction_pattern {
|
||||
uint32_t value;
|
||||
uint32_t mask;
|
||||
opcode_e id;
|
||||
};
|
||||
|
||||
std::array<std::vector<instruction_pattern>, 4> qlut;
|
||||
|
||||
template<typename T>
|
||||
unsigned decode_instruction(T);
|
||||
|
||||
instruction_decoder() {
|
||||
for (auto instr : instr_descr) {
|
||||
auto quadrant = instr.value & 0x3;
|
||||
qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
|
||||
}
|
||||
for(auto& lut: qlut){
|
||||
std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
|
||||
return bit_count(a.mask) < bit_count(b.mask);
|
||||
});
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
template<>
|
||||
unsigned instruction_decoder<${coreDef.name.toLowerCase()}>::decode_instruction<traits<${coreDef.name.toLowerCase()}>::code_word_t>(traits<${coreDef.name.toLowerCase()}>::code_word_t instr){
|
||||
auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
|
||||
return !((instr&e.mask) ^ e.value );
|
||||
});
|
||||
return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
|
||||
}
|
||||
|
||||
|
||||
std::unique_ptr<instruction_decoder<${coreDef.name.toLowerCase()}>> traits<${coreDef.name.toLowerCase()}>::get_decoder(){
|
||||
return std::make_unique<instruction_decoder<${coreDef.name.toLowerCase()}>>();
|
||||
}
|
||||
|
||||
}
|
||||
}
|
@ -1,20 +0,0 @@
|
||||
<% def getInstructionGroups() {
|
||||
def instrGroups = [:]
|
||||
instructions.each {
|
||||
def groupName = it['instruction'].eContainer().name
|
||||
if(!instrGroups.containsKey(groupName)) {
|
||||
instrGroups[groupName]=[]
|
||||
}
|
||||
instrGroups[groupName]+=it;
|
||||
}
|
||||
instrGroups
|
||||
}%><%getInstructionGroups().each{name, instrList -> %>
|
||||
${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %>
|
||||
- ${it.instruction.name}:
|
||||
encoding: ${it.encoding}
|
||||
mask: ${it.mask}<%if(it.attributes.size) {%>
|
||||
attributes: ${it.attributes}<%}%>
|
||||
size: ${it.length}
|
||||
branch: ${it.modifiesPC}
|
||||
delay: ${it.isConditional?"[1,1]":"1"}<%}}%>
|
||||
|
@ -1,334 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2021 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
<%
|
||||
def nativeTypeSize(int size){
|
||||
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
|
||||
}
|
||||
%>
|
||||
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
#include <iss/interp/vm_base.h>
|
||||
#include <util/logging.h>
|
||||
#include <sstream>
|
||||
#include <boost/coroutine2/all.hpp>
|
||||
#include <functional>
|
||||
|
||||
#ifndef FMT_HEADER_ONLY
|
||||
#define FMT_HEADER_ONLY
|
||||
#endif
|
||||
#include <fmt/format.h>
|
||||
|
||||
#include <array>
|
||||
#include <iss/debugger/riscv_target_adapter.h>
|
||||
|
||||
namespace iss {
|
||||
namespace interp {
|
||||
namespace ${coreDef.name.toLowerCase()} {
|
||||
using namespace iss::arch;
|
||||
using namespace iss::debugger;
|
||||
using namespace std::placeholders;
|
||||
|
||||
template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
|
||||
public:
|
||||
using traits = arch::traits<ARCH>;
|
||||
using super = typename iss::interp::vm_base<ARCH>;
|
||||
using virt_addr_t = typename super::virt_addr_t;
|
||||
using phys_addr_t = typename super::phys_addr_t;
|
||||
using code_word_t = typename super::code_word_t;
|
||||
using addr_t = typename super::addr_t;
|
||||
using reg_t = typename traits::reg_t;
|
||||
using mem_type_e = typename traits::mem_type_e;
|
||||
using opcode_e = typename traits::opcode_e;
|
||||
|
||||
vm_impl();
|
||||
|
||||
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
|
||||
|
||||
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
|
||||
|
||||
target_adapter_if *accquire_target_adapter(server_if *srv) override {
|
||||
debugger_if::dbg_enabled = true;
|
||||
if (super::tgt_adapter == nullptr)
|
||||
super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
|
||||
return super::tgt_adapter;
|
||||
}
|
||||
|
||||
protected:
|
||||
using this_class = vm_impl<ARCH>;
|
||||
using compile_ret_t = virt_addr_t;
|
||||
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
|
||||
|
||||
inline const char *name(size_t index){return index<traits::reg_aliases.size()?traits::reg_aliases[index]:"illegal";}
|
||||
|
||||
typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
|
||||
virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
|
||||
|
||||
// some compile time constants
|
||||
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
|
||||
enum {
|
||||
LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)),
|
||||
LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16))
|
||||
};
|
||||
|
||||
std::array<compile_func, LUT_SIZE> lut;
|
||||
|
||||
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
|
||||
std::array<compile_func, LUT_SIZE> lut_11;
|
||||
|
||||
struct instruction_pattern {
|
||||
uint32_t value;
|
||||
uint32_t mask;
|
||||
typename arch::traits<ARCH>::opcode_e id;
|
||||
};
|
||||
|
||||
std::array<std::vector<instruction_pattern>, 4> qlut;
|
||||
|
||||
inline void raise(uint16_t trap_id, uint16_t cause){
|
||||
auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
|
||||
this->core.reg.trap_state = trap_val;
|
||||
this->template get_reg<uint${addrDataWidth}_t>(traits::NEXT_PC) = std::numeric_limits<uint${addrDataWidth}_t>::max();
|
||||
}
|
||||
|
||||
inline void leave(unsigned lvl){
|
||||
this->core.leave_trap(lvl);
|
||||
}
|
||||
|
||||
inline void wait(unsigned type){
|
||||
this->core.wait_until(type);
|
||||
}
|
||||
|
||||
using yield_t = boost::coroutines2::coroutine<void>::push_type;
|
||||
using coro_t = boost::coroutines2::coroutine<void>::pull_type;
|
||||
std::vector<coro_t> spawn_blocks;
|
||||
|
||||
template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
|
||||
inline S sext(U from) {
|
||||
auto mask = (1ULL<<W) - 1;
|
||||
auto sign_mask = 1ULL<<(W-1);
|
||||
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
|
||||
}
|
||||
|
||||
inline void process_spawn_blocks() {
|
||||
if(spawn_blocks.size()==0) return;
|
||||
for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
|
||||
if(*it){
|
||||
(*it)();
|
||||
++it;
|
||||
} else
|
||||
spawn_blocks.erase(it);
|
||||
}
|
||||
<%functions.each{ it.eachLine { %>
|
||||
${it}<%}%>
|
||||
<%}%>
|
||||
|
||||
private:
|
||||
/****************************************************************************
|
||||
* start opcode definitions
|
||||
****************************************************************************/
|
||||
struct InstructionDesriptor {
|
||||
size_t length;
|
||||
uint32_t value;
|
||||
uint32_t mask;
|
||||
typename arch::traits<ARCH>::opcode_e op;
|
||||
};
|
||||
|
||||
const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
|
||||
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
|
||||
{${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
|
||||
}};
|
||||
|
||||
//static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
|
||||
iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
|
||||
auto phys_pc = this->core.v2p(pc);
|
||||
//if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
||||
// if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
|
||||
// if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
|
||||
// if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
|
||||
//} else {
|
||||
if (this->core.read(phys_pc, 4, data) != iss::Ok) return iss::Err;
|
||||
//}
|
||||
return iss::Ok;
|
||||
}
|
||||
};
|
||||
|
||||
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
|
||||
volatile CODE_WORD x = insn;
|
||||
insn = 2 * x;
|
||||
}
|
||||
|
||||
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
|
||||
|
||||
// according to
|
||||
// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
|
||||
#ifdef __GCC__
|
||||
constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
|
||||
#elif __cplusplus < 201402L
|
||||
constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
|
||||
constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
|
||||
#else
|
||||
constexpr size_t bit_count(uint32_t u) {
|
||||
size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
|
||||
return ((uCount + (uCount >> 3)) & 030707070707) % 63;
|
||||
}
|
||||
#endif
|
||||
|
||||
template <typename ARCH>
|
||||
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
|
||||
: vm_base<ARCH>(core, core_id, cluster_id) {
|
||||
unsigned id=0;
|
||||
for (auto instr : instr_descr) {
|
||||
auto quadrant = instr.value & 0x3;
|
||||
qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
|
||||
}
|
||||
for(auto& lut: qlut){
|
||||
std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
|
||||
return bit_count(a.mask) > bit_count(b.mask);
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
inline bool is_count_limit_enabled(finish_cond_e cond){
|
||||
return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
|
||||
}
|
||||
|
||||
inline bool is_jump_to_self_enabled(finish_cond_e cond){
|
||||
return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
|
||||
}
|
||||
|
||||
template <typename ARCH>
|
||||
typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
|
||||
for(auto& e: qlut[instr&0x3]){
|
||||
if(!((instr&e.mask) ^ e.value )) return e.id;
|
||||
}
|
||||
return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
|
||||
}
|
||||
|
||||
template <typename ARCH>
|
||||
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
|
||||
auto pc=start;
|
||||
auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
||||
auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
||||
auto& trap_state = this->core.reg.trap_state;
|
||||
auto& icount = this->core.reg.icount;
|
||||
auto& cycle = this->core.reg.cycle;
|
||||
auto& instret = this->core.reg.instret;
|
||||
auto& instr = this->core.reg.instruction;
|
||||
// we fetch at max 4 byte, alignment is 2
|
||||
auto *const data = reinterpret_cast<uint8_t*>(&instr);
|
||||
|
||||
while(!this->core.should_stop() &&
|
||||
!(is_count_limit_enabled(cond) && icount >= icount_limit)){
|
||||
if(fetch_ins(pc, data)!=iss::Ok){
|
||||
this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
|
||||
pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
|
||||
} else {
|
||||
if (is_jump_to_self_enabled(cond) &&
|
||||
(instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||
auto inst_id = decode_inst_id(instr);
|
||||
// pre execution stuff
|
||||
this->core.reg.last_branch = 0;
|
||||
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
|
||||
switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
|
||||
case arch::traits<ARCH>::opcode_e::${instr.name}: {
|
||||
<%instr.fields.eachLine{%>${it}
|
||||
<%}%>if(this->disass_enabled){
|
||||
/* generate console output when executing the command */<%instr.disass.eachLine{%>
|
||||
${it}<%}%>
|
||||
}
|
||||
// used registers<%instr.usedVariables.each{ k,v->
|
||||
if(v.isArray) {%>
|
||||
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
|
||||
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
|
||||
<%}}%>// calculate next pc value
|
||||
*NEXT_PC = *PC + ${instr.length/8};
|
||||
// execute instruction<%instr.behavior.eachLine{%>
|
||||
${it}<%}%>
|
||||
TRAP_${instr.name}:break;
|
||||
}// @suppress("No break at end of case")<%}%>
|
||||
default: {
|
||||
*NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
|
||||
raise(0, 2);
|
||||
}
|
||||
}
|
||||
// post execution stuff
|
||||
process_spawn_blocks();
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
|
||||
// if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt
|
||||
// this->core.reg.trap_state = this->core.reg.pending_trap;
|
||||
// trap check
|
||||
if(trap_state!=0){
|
||||
super::core.enter_trap(trap_state, pc.val, instr);
|
||||
} else {
|
||||
icount++;
|
||||
instret++;
|
||||
}
|
||||
cycle++;
|
||||
pc.val=*NEXT_PC;
|
||||
this->core.reg.PC = this->core.reg.NEXT_PC;
|
||||
this->core.reg.trap_state = this->core.reg.pending_trap;
|
||||
}
|
||||
}
|
||||
return pc;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
template <>
|
||||
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
|
||||
auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||
return std::unique_ptr<vm_if>(ret);
|
||||
}
|
||||
} // namespace interp
|
||||
} // namespace iss
|
||||
|
||||
#include <iss/factory.h>
|
||||
#include <iss/arch/riscv_hart_m_p.h>
|
||||
#include <iss/arch/riscv_hart_mu_p.h>
|
||||
namespace iss {
|
||||
namespace {
|
||||
volatile std::array<bool, 2> dummy = {
|
||||
core_factory::instance().register_creator("${coreDef.name.toLowerCase()|m_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto* lcpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()>();
|
||||
return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
|
||||
}),
|
||||
core_factory::instance().register_creator("${coreDef.name.toLowerCase()|mu_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto* lcpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()>();
|
||||
return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
|
||||
})
|
||||
};
|
||||
}
|
||||
}
|
9
gen_input/templates/interp/CORENAME_cyles.txt.gtl
Normal file
9
gen_input/templates/interp/CORENAME_cyles.txt.gtl
Normal file
@ -0,0 +1,9 @@
|
||||
{
|
||||
"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
|
||||
{
|
||||
"name" : "${instr.name}",
|
||||
"size" : ${instr.length},
|
||||
"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
|
||||
}<%}%>
|
||||
]
|
||||
}
|
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -29,33 +29,47 @@
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
<%
|
||||
def nativeTypeSize(int size){
|
||||
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
|
||||
|
||||
<%
|
||||
import com.minres.coredsl.coreDsl.Register
|
||||
import com.minres.coredsl.coreDsl.RegisterFile
|
||||
import com.minres.coredsl.coreDsl.RegisterAlias
|
||||
def getTypeSize(size){
|
||||
if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
|
||||
}
|
||||
def getRegisterSizes(){
|
||||
def regs = registers.collect{nativeTypeSize(it.size)}
|
||||
regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
|
||||
return regs
|
||||
}
|
||||
def getRegisterOffsets(){
|
||||
def offset = 0
|
||||
def offsets = []
|
||||
getRegisterSizes().each { size ->
|
||||
offsets<<offset
|
||||
offset+=size/8
|
||||
def getOriginalName(reg){
|
||||
if( reg.original instanceof RegisterFile) {
|
||||
if( reg.index != null ) {
|
||||
return reg.original.name+generator.generateHostCode(reg.index)
|
||||
} else {
|
||||
return reg.original.name
|
||||
}
|
||||
} else if(reg.original instanceof Register){
|
||||
return reg.original.name
|
||||
}
|
||||
return offsets
|
||||
}
|
||||
def byteSize(int size){
|
||||
if(size<=8) return 8;
|
||||
if(size<=16) return 16;
|
||||
if(size<=32) return 32;
|
||||
if(size<=64) return 64;
|
||||
return 128;
|
||||
def getRegisterNames(){
|
||||
def regNames = []
|
||||
allRegs.each { reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
(reg.range.right..reg.range.left).each{
|
||||
regNames+=reg.name.toLowerCase()+it
|
||||
}
|
||||
} else if(reg instanceof Register){
|
||||
regNames+=reg.name.toLowerCase()
|
||||
}
|
||||
}
|
||||
return regNames
|
||||
}
|
||||
def getCString(def val){
|
||||
return val.toString()
|
||||
def getRegisterAliasNames(){
|
||||
def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
|
||||
return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
|
||||
} else if(reg instanceof Register){
|
||||
regMap[reg.name]?:reg.name.toLowerCase()
|
||||
}
|
||||
}.flatten()
|
||||
}
|
||||
%>
|
||||
#ifndef _${coreDef.name.toUpperCase()}_H_
|
||||
@ -73,23 +87,43 @@ struct ${coreDef.name.toLowerCase()};
|
||||
|
||||
template <> struct traits<${coreDef.name.toLowerCase()}> {
|
||||
|
||||
constexpr static char const* const core_type = "${coreDef.name}";
|
||||
constexpr static char const* const core_type = "${coreDef.name}";
|
||||
|
||||
static constexpr std::array<const char*, ${registers.size}> reg_names{
|
||||
{"${registers.collect{it.name}.join('", "')}"}};
|
||||
static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
|
||||
{"${getRegisterNames().join("\", \"")}"}};
|
||||
|
||||
static constexpr std::array<const char*, ${registers.size}> reg_aliases{
|
||||
{"${registers.collect{it.alias}.join('", "')}"}};
|
||||
static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
|
||||
{"${getRegisterAliasNames().join("\", \"")}"}};
|
||||
|
||||
enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
|
||||
enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
|
||||
|
||||
constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
|
||||
constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
|
||||
|
||||
enum reg_e {
|
||||
${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
|
||||
enum reg_e {<%
|
||||
allRegs.each { reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
(reg.range.right..reg.range.left).each{%>
|
||||
${reg.name}${it},<%
|
||||
}
|
||||
} else if(reg instanceof Register){ %>
|
||||
${reg.name},<%
|
||||
}
|
||||
}%>
|
||||
NUM_REGS,
|
||||
NEXT_${pc.name}=NUM_REGS,
|
||||
TRAP_STATE,
|
||||
PENDING_TRAP,
|
||||
MACHINE_STATE,
|
||||
LAST_BRANCH,
|
||||
ICOUNT<%
|
||||
allRegs.each { reg ->
|
||||
if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
|
||||
${reg.name} = ${aliasname}<%
|
||||
}
|
||||
}%>
|
||||
};
|
||||
|
||||
using reg_t = uint${addrDataWidth}_t;
|
||||
using reg_t = uint${regDataWidth}_t;
|
||||
|
||||
using addr_t = uint${addrDataWidth}_t;
|
||||
|
||||
@ -99,22 +133,17 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
|
||||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||
|
||||
static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
|
||||
{${getRegisterSizes().join(',')}}};
|
||||
static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
|
||||
{${regSizes.join(",")}}};
|
||||
|
||||
static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
|
||||
{${getRegisterOffsets().join(',')}}};
|
||||
static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
|
||||
{${regOffsets.join(",")}}};
|
||||
|
||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||
|
||||
enum sreg_flag_e { FLAGS };
|
||||
|
||||
enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
|
||||
|
||||
enum class opcode_e : unsigned short {<%instructions.eachWithIndex{instr, index -> %>
|
||||
${instr.instruction.name} = ${index},<%}%>
|
||||
MAX_OPCODE
|
||||
};
|
||||
enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
|
||||
};
|
||||
|
||||
struct ${coreDef.name.toLowerCase()}: public arch_if {
|
||||
@ -130,6 +159,14 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
|
||||
void reset(uint64_t address=0) override;
|
||||
|
||||
uint8_t* get_regs_base_ptr() override;
|
||||
/// deprecated
|
||||
void get_reg(short idx, std::vector<uint8_t>& value) override {}
|
||||
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
|
||||
/// deprecated
|
||||
bool get_flag(int flag) override {return false;}
|
||||
void set_flag(int, bool value) override {};
|
||||
/// deprecated
|
||||
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
|
||||
|
||||
inline uint64_t get_icount() { return reg.icount; }
|
||||
|
||||
@ -151,31 +188,33 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
|
||||
|
||||
inline uint32_t get_last_branch() { return reg.last_branch; }
|
||||
|
||||
|
||||
#pragma pack(push, 1)
|
||||
protected:
|
||||
struct ${coreDef.name}_regs {<%
|
||||
registers.each { reg -> if(reg.size>0) {%>
|
||||
uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
|
||||
}}%>
|
||||
uint32_t trap_state = 0, pending_trap = 0;
|
||||
allRegs.each { reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
(reg.range.right..reg.range.left).each{%>
|
||||
uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
|
||||
}
|
||||
} else if(reg instanceof Register){ %>
|
||||
uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
|
||||
}
|
||||
}%>
|
||||
uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
|
||||
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
|
||||
uint64_t icount = 0;
|
||||
uint64_t cycle = 0;
|
||||
uint64_t instret = 0;
|
||||
uint32_t instruction = 0;
|
||||
uint32_t last_branch = 0;
|
||||
} reg;
|
||||
#pragma pack(pop)
|
||||
|
||||
std::array<address_type, 4> addr_mode;
|
||||
|
||||
uint64_t interrupt_sim=0;
|
||||
<%
|
||||
def fcsr = registers.find {it.name=='FCSR'}
|
||||
def fcsr = allRegs.find {it.name=='FCSR'}
|
||||
if(fcsr != null) {%>
|
||||
uint${fcsr.size}_t get_fcsr(){return reg.FCSR;}
|
||||
void set_fcsr(uint${fcsr.size}_t val){reg.FCSR = val;}
|
||||
uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
|
||||
void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}
|
||||
<%} else { %>
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
<%}%>
|
||||
};
|
||||
|
107
gen_input/templates/interp/src-CORENAME.cpp.gtl
Normal file
107
gen_input/templates/interp/src-CORENAME.cpp.gtl
Normal file
@ -0,0 +1,107 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
<%
|
||||
import com.minres.coredsl.coreDsl.Register
|
||||
import com.minres.coredsl.coreDsl.RegisterFile
|
||||
import com.minres.coredsl.coreDsl.RegisterAlias
|
||||
def getOriginalName(reg){
|
||||
if( reg.original instanceof RegisterFile) {
|
||||
if( reg.index != null ) {
|
||||
return reg.original.name+generator.generateHostCode(reg.index)
|
||||
} else {
|
||||
return reg.original.name
|
||||
}
|
||||
} else if(reg.original instanceof Register){
|
||||
return reg.original.name
|
||||
}
|
||||
}
|
||||
def getRegisterNames(){
|
||||
def regNames = []
|
||||
allRegs.each { reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
(reg.range.right..reg.range.left).each{
|
||||
regNames+=reg.name.toLowerCase()+it
|
||||
}
|
||||
} else if(reg instanceof Register){
|
||||
regNames+=reg.name.toLowerCase()
|
||||
}
|
||||
}
|
||||
return regNames
|
||||
}
|
||||
def getRegisterAliasNames(){
|
||||
def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
|
||||
return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
|
||||
} else if(reg instanceof Register){
|
||||
regMap[reg.name]?:reg.name.toLowerCase()
|
||||
}
|
||||
}.flatten()
|
||||
}
|
||||
%>
|
||||
#include "util/ities.h"
|
||||
#include <util/logging.h>
|
||||
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
|
||||
#include <cstdio>
|
||||
#include <cstring>
|
||||
#include <fstream>
|
||||
|
||||
using namespace iss::arch;
|
||||
|
||||
constexpr std::array<const char*, ${getRegisterNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
|
||||
constexpr std::array<const char*, ${getRegisterAliasNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
|
||||
|
||||
${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
|
||||
reg.icount = 0;
|
||||
}
|
||||
|
||||
${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
|
||||
|
||||
void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
|
||||
for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
|
||||
reg.PC=address;
|
||||
reg.NEXT_PC=reg.PC;
|
||||
reg.trap_state=0;
|
||||
reg.machine_state=0x3;
|
||||
reg.icount=0;
|
||||
}
|
||||
|
||||
uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
|
||||
return reinterpret_cast<uint8_t*>(®);
|
||||
}
|
||||
|
||||
${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
|
||||
return phys_addr_t(pc); // change logical address to physical address
|
||||
}
|
||||
|
247
gen_input/templates/interp/vm-vm_CORENAME.cpp.gtl
Normal file
247
gen_input/templates/interp/vm-vm_CORENAME.cpp.gtl
Normal file
@ -0,0 +1,247 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2020 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include "../fp_functions.h"
|
||||
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
|
||||
#include <iss/arch/riscv_hart_m_p.h>
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
#include <iss/interp/vm_base.h>
|
||||
#include <util/logging.h>
|
||||
#include <sstream>
|
||||
|
||||
#ifndef FMT_HEADER_ONLY
|
||||
#define FMT_HEADER_ONLY
|
||||
#endif
|
||||
#include <fmt/format.h>
|
||||
|
||||
#include <array>
|
||||
#include <iss/debugger/riscv_target_adapter.h>
|
||||
|
||||
namespace iss {
|
||||
namespace interp {
|
||||
namespace ${coreDef.name.toLowerCase()} {
|
||||
using namespace iss::arch;
|
||||
using namespace iss::debugger;
|
||||
|
||||
template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
|
||||
public:
|
||||
using super = typename iss::interp::vm_base<ARCH>;
|
||||
using virt_addr_t = typename super::virt_addr_t;
|
||||
using phys_addr_t = typename super::phys_addr_t;
|
||||
using code_word_t = typename super::code_word_t;
|
||||
using addr_t = typename super::addr_t;
|
||||
using reg_t = typename traits<ARCH>::reg_t;
|
||||
using iss::interp::vm_base<ARCH>::get_reg;
|
||||
|
||||
vm_impl();
|
||||
|
||||
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
|
||||
|
||||
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
|
||||
|
||||
target_adapter_if *accquire_target_adapter(server_if *srv) override {
|
||||
debugger_if::dbg_enabled = true;
|
||||
if (super::tgt_adapter == nullptr)
|
||||
super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
|
||||
return super::tgt_adapter;
|
||||
}
|
||||
|
||||
protected:
|
||||
using this_class = vm_impl<ARCH>;
|
||||
using compile_ret_t = virt_addr_t;
|
||||
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
|
||||
|
||||
inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
|
||||
|
||||
virt_addr_t execute_inst(virt_addr_t start, std::function<bool(void)> pred) override;
|
||||
|
||||
// some compile time constants
|
||||
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
|
||||
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
|
||||
|
||||
std::array<compile_func, LUT_SIZE> lut;
|
||||
|
||||
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
|
||||
std::array<compile_func, LUT_SIZE> lut_11;
|
||||
|
||||
std::array<compile_func *, 4> qlut;
|
||||
|
||||
std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
|
||||
|
||||
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
|
||||
compile_func f) {
|
||||
if (pos < 0) {
|
||||
lut[idx] = f;
|
||||
} else {
|
||||
auto bitmask = 1UL << pos;
|
||||
if ((mask & bitmask) == 0) {
|
||||
expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
|
||||
} else {
|
||||
if ((valid & bitmask) == 0) {
|
||||
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
|
||||
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
|
||||
} else {
|
||||
auto new_val = idx << 1;
|
||||
if ((value & bitmask) != 0) new_val++;
|
||||
expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
|
||||
|
||||
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
|
||||
if (pos >= 0) {
|
||||
auto bitmask = 1UL << pos;
|
||||
if ((mask & bitmask) == 0) {
|
||||
lut_val = extract_fields(pos - 1, val, mask, lut_val);
|
||||
} else {
|
||||
auto new_val = lut_val << 1;
|
||||
if ((val & bitmask) != 0) new_val++;
|
||||
lut_val = extract_fields(pos - 1, val, mask, new_val);
|
||||
}
|
||||
}
|
||||
return lut_val;
|
||||
}
|
||||
|
||||
void raise_trap(uint16_t trap_id, uint16_t cause){
|
||||
auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
|
||||
this->template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE) = trap_val;
|
||||
this->template get_reg<uint32_t>(arch::traits<ARCH>::NEXT_PC) = std::numeric_limits<uint32_t>::max();
|
||||
}
|
||||
|
||||
void leave_trap(unsigned lvl){
|
||||
this->core.leave_trap(lvl);
|
||||
auto pc_val = super::template read_mem<reg_t>(traits<ARCH>::CSR, (lvl << 8) + 0x41);
|
||||
this->template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc_val;
|
||||
this->template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
|
||||
}
|
||||
|
||||
void wait(unsigned type){
|
||||
this->core.wait_until(type);
|
||||
}
|
||||
|
||||
|
||||
private:
|
||||
/****************************************************************************
|
||||
* start opcode definitions
|
||||
****************************************************************************/
|
||||
struct InstructionDesriptor {
|
||||
size_t length;
|
||||
uint32_t value;
|
||||
uint32_t mask;
|
||||
compile_func op;
|
||||
};
|
||||
|
||||
const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
|
||||
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
|
||||
/* instruction ${instr.instruction.name} */
|
||||
{${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
|
||||
}};
|
||||
|
||||
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
|
||||
/* instruction ${idx}: ${instr.name} */
|
||||
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){<%instr.code.eachLine{%>
|
||||
${it}<%}%>
|
||||
}
|
||||
<%}%>
|
||||
/****************************************************************************
|
||||
* end opcode definitions
|
||||
****************************************************************************/
|
||||
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
|
||||
pc = pc + ((instr & 3) == 3 ? 4 : 2);
|
||||
return pc;
|
||||
}
|
||||
};
|
||||
|
||||
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
|
||||
volatile CODE_WORD x = insn;
|
||||
insn = 2 * x;
|
||||
}
|
||||
|
||||
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
|
||||
|
||||
template <typename ARCH>
|
||||
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
|
||||
: vm_base<ARCH>(core, core_id, cluster_id) {
|
||||
qlut[0] = lut_00.data();
|
||||
qlut[1] = lut_01.data();
|
||||
qlut[2] = lut_10.data();
|
||||
qlut[3] = lut_11.data();
|
||||
for (auto instr : instr_descr) {
|
||||
auto quantrant = instr.value & 0x3;
|
||||
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
|
||||
}
|
||||
}
|
||||
|
||||
template <typename ARCH>
|
||||
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(void)> pred) {
|
||||
// we fetch at max 4 byte, alignment is 2
|
||||
enum {TRAP_ID=1<<16};
|
||||
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
|
||||
code_word_t insn = 0;
|
||||
auto *const data = (uint8_t *)&insn;
|
||||
auto pc=start;
|
||||
while(pred){
|
||||
auto paddr = this->core.v2p(pc);
|
||||
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
||||
if (this->core.read(paddr, 2, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
if ((insn & 0x3) == 0x3) // this is a 32bit instruction
|
||||
if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
} else {
|
||||
if (this->core.read(paddr, 4, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
}
|
||||
if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||
auto lut_val = extract_fields(insn);
|
||||
auto f = qlut[insn & 0x3][lut_val];
|
||||
if (!f)
|
||||
f = &this_class::illegal_intruction;
|
||||
pc = (this->*f)(pc, insn);
|
||||
}
|
||||
return pc;
|
||||
}
|
||||
|
||||
} // namespace mnrv32
|
||||
|
||||
template <>
|
||||
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
|
||||
auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||
return std::unique_ptr<vm_if>(ret);
|
||||
}
|
||||
} // namespace interp
|
||||
} // namespace iss
|
@ -30,10 +30,10 @@
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
|
||||
#include <iss/arch/riscv_hart_m_p.h>
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
#include <iss/llvm/vm_base.h>
|
||||
#include <util/logging.h>
|
||||
|
9
gen_input/templates/tcc/CORENAME_cyles.txt.gtl
Normal file
9
gen_input/templates/tcc/CORENAME_cyles.txt.gtl
Normal file
@ -0,0 +1,9 @@
|
||||
{
|
||||
"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
|
||||
{
|
||||
"name" : "${instr.name}",
|
||||
"size" : ${instr.length},
|
||||
"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
|
||||
}<%}%>
|
||||
]
|
||||
}
|
223
gen_input/templates/tcc/incl-CORENAME.h.gtl
Normal file
223
gen_input/templates/tcc/incl-CORENAME.h.gtl
Normal file
@ -0,0 +1,223 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
<%
|
||||
import com.minres.coredsl.coreDsl.Register
|
||||
import com.minres.coredsl.coreDsl.RegisterFile
|
||||
import com.minres.coredsl.coreDsl.RegisterAlias
|
||||
def getTypeSize(size){
|
||||
if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
|
||||
}
|
||||
def getOriginalName(reg){
|
||||
if( reg.original instanceof RegisterFile) {
|
||||
if( reg.index != null ) {
|
||||
return reg.original.name+generator.generateHostCode(reg.index)
|
||||
} else {
|
||||
return reg.original.name
|
||||
}
|
||||
} else if(reg.original instanceof Register){
|
||||
return reg.original.name
|
||||
}
|
||||
}
|
||||
def getRegisterNames(){
|
||||
def regNames = []
|
||||
allRegs.each { reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
(reg.range.right..reg.range.left).each{
|
||||
regNames+=reg.name.toLowerCase()+it
|
||||
}
|
||||
} else if(reg instanceof Register){
|
||||
regNames+=reg.name.toLowerCase()
|
||||
}
|
||||
}
|
||||
return regNames
|
||||
}
|
||||
def getRegisterAliasNames(){
|
||||
def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
|
||||
return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
|
||||
} else if(reg instanceof Register){
|
||||
regMap[reg.name]?:reg.name.toLowerCase()
|
||||
}
|
||||
}.flatten()
|
||||
}
|
||||
%>
|
||||
#ifndef _${coreDef.name.toUpperCase()}_H_
|
||||
#define _${coreDef.name.toUpperCase()}_H_
|
||||
|
||||
#include <array>
|
||||
#include <iss/arch/traits.h>
|
||||
#include <iss/arch_if.h>
|
||||
#include <iss/vm_if.h>
|
||||
|
||||
namespace iss {
|
||||
namespace arch {
|
||||
|
||||
struct ${coreDef.name.toLowerCase()};
|
||||
|
||||
template <> struct traits<${coreDef.name.toLowerCase()}> {
|
||||
|
||||
constexpr static char const* const core_type = "${coreDef.name}";
|
||||
|
||||
static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
|
||||
{"${getRegisterNames().join("\", \"")}"}};
|
||||
|
||||
static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
|
||||
{"${getRegisterAliasNames().join("\", \"")}"}};
|
||||
|
||||
enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
|
||||
|
||||
constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
|
||||
|
||||
enum reg_e {<%
|
||||
allRegs.each { reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
(reg.range.right..reg.range.left).each{%>
|
||||
${reg.name}${it},<%
|
||||
}
|
||||
} else if(reg instanceof Register){ %>
|
||||
${reg.name},<%
|
||||
}
|
||||
}%>
|
||||
NUM_REGS,
|
||||
NEXT_${pc.name}=NUM_REGS,
|
||||
TRAP_STATE,
|
||||
PENDING_TRAP,
|
||||
MACHINE_STATE,
|
||||
LAST_BRANCH,
|
||||
ICOUNT<%
|
||||
allRegs.each { reg ->
|
||||
if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
|
||||
${reg.name} = ${aliasname}<%
|
||||
}
|
||||
}%>
|
||||
};
|
||||
|
||||
using reg_t = uint${regDataWidth}_t;
|
||||
|
||||
using addr_t = uint${addrDataWidth}_t;
|
||||
|
||||
using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
|
||||
|
||||
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
|
||||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||
|
||||
static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
|
||||
{${regSizes.join(",")}}};
|
||||
|
||||
static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
|
||||
{${regOffsets.join(",")}}};
|
||||
|
||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||
|
||||
enum sreg_flag_e { FLAGS };
|
||||
|
||||
enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
|
||||
};
|
||||
|
||||
struct ${coreDef.name.toLowerCase()}: public arch_if {
|
||||
|
||||
using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
|
||||
using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
|
||||
using reg_t = typename traits<${coreDef.name.toLowerCase()}>::reg_t;
|
||||
using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
|
||||
|
||||
${coreDef.name.toLowerCase()}();
|
||||
~${coreDef.name.toLowerCase()}();
|
||||
|
||||
void reset(uint64_t address=0) override;
|
||||
|
||||
uint8_t* get_regs_base_ptr() override;
|
||||
/// deprecated
|
||||
void get_reg(short idx, std::vector<uint8_t>& value) override {}
|
||||
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
|
||||
/// deprecated
|
||||
bool get_flag(int flag) override {return false;}
|
||||
void set_flag(int, bool value) override {};
|
||||
/// deprecated
|
||||
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
|
||||
|
||||
inline uint64_t get_icount() { return reg.icount; }
|
||||
|
||||
inline bool should_stop() { return interrupt_sim; }
|
||||
|
||||
inline uint64_t stop_code() { return interrupt_sim; }
|
||||
|
||||
inline phys_addr_t v2p(const iss::addr_t& addr){
|
||||
if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
|
||||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
|
||||
return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
|
||||
} else
|
||||
return virt2phys(addr);
|
||||
}
|
||||
|
||||
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
|
||||
|
||||
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
|
||||
|
||||
inline uint32_t get_last_branch() { return reg.last_branch; }
|
||||
|
||||
protected:
|
||||
struct ${coreDef.name}_regs {<%
|
||||
allRegs.each { reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
(reg.range.right..reg.range.left).each{%>
|
||||
uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
|
||||
}
|
||||
} else if(reg instanceof Register){ %>
|
||||
uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
|
||||
}
|
||||
}%>
|
||||
uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
|
||||
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
|
||||
uint64_t icount = 0;
|
||||
} reg;
|
||||
|
||||
std::array<address_type, 4> addr_mode;
|
||||
|
||||
uint64_t interrupt_sim=0;
|
||||
<%
|
||||
def fcsr = allRegs.find {it.name=='FCSR'}
|
||||
if(fcsr != null) {%>
|
||||
uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
|
||||
void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}
|
||||
<%} else { %>
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
<%}%>
|
||||
};
|
||||
|
||||
}
|
||||
}
|
||||
#endif /* _${coreDef.name.toUpperCase()}_H_ */
|
107
gen_input/templates/tcc/src-CORENAME.cpp.gtl
Normal file
107
gen_input/templates/tcc/src-CORENAME.cpp.gtl
Normal file
@ -0,0 +1,107 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
<%
|
||||
import com.minres.coredsl.coreDsl.Register
|
||||
import com.minres.coredsl.coreDsl.RegisterFile
|
||||
import com.minres.coredsl.coreDsl.RegisterAlias
|
||||
def getOriginalName(reg){
|
||||
if( reg.original instanceof RegisterFile) {
|
||||
if( reg.index != null ) {
|
||||
return reg.original.name+generator.generateHostCode(reg.index)
|
||||
} else {
|
||||
return reg.original.name
|
||||
}
|
||||
} else if(reg.original instanceof Register){
|
||||
return reg.original.name
|
||||
}
|
||||
}
|
||||
def getRegisterNames(){
|
||||
def regNames = []
|
||||
allRegs.each { reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
(reg.range.right..reg.range.left).each{
|
||||
regNames+=reg.name.toLowerCase()+it
|
||||
}
|
||||
} else if(reg instanceof Register){
|
||||
regNames+=reg.name.toLowerCase()
|
||||
}
|
||||
}
|
||||
return regNames
|
||||
}
|
||||
def getRegisterAliasNames(){
|
||||
def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
|
||||
return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
|
||||
} else if(reg instanceof Register){
|
||||
regMap[reg.name]?:reg.name.toLowerCase()
|
||||
}
|
||||
}.flatten()
|
||||
}
|
||||
%>
|
||||
#include "util/ities.h"
|
||||
#include <util/logging.h>
|
||||
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
|
||||
#include <cstdio>
|
||||
#include <cstring>
|
||||
#include <fstream>
|
||||
|
||||
using namespace iss::arch;
|
||||
|
||||
constexpr std::array<const char*, ${getRegisterNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
|
||||
constexpr std::array<const char*, ${getRegisterAliasNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
|
||||
|
||||
${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
|
||||
reg.icount = 0;
|
||||
}
|
||||
|
||||
${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
|
||||
|
||||
void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
|
||||
for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
|
||||
reg.PC=address;
|
||||
reg.NEXT_PC=reg.PC;
|
||||
reg.trap_state=0;
|
||||
reg.machine_state=0x3;
|
||||
reg.icount=0;
|
||||
}
|
||||
|
||||
uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
|
||||
return reinterpret_cast<uint8_t*>(®);
|
||||
}
|
||||
|
||||
${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
|
||||
return phys_addr_t(pc); // change logical address to physical address
|
||||
}
|
||||
|
@ -31,6 +31,7 @@
|
||||
*******************************************************************************/
|
||||
|
||||
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
|
||||
#include <iss/arch/riscv_hart_m_p.h>
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
@ -54,12 +55,10 @@ using namespace iss::debugger;
|
||||
|
||||
template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
|
||||
public:
|
||||
using traits = arch::traits<ARCH>;
|
||||
using super = typename iss::tcc::vm_base<ARCH>;
|
||||
using virt_addr_t = typename super::virt_addr_t;
|
||||
using phys_addr_t = typename super::phys_addr_t;
|
||||
using code_word_t = typename super::code_word_t;
|
||||
using mem_type_e = typename traits::mem_type_e;
|
||||
using addr_t = typename super::addr_t;
|
||||
using tu_builder = typename super::tu_builder;
|
||||
|
||||
@ -83,7 +82,7 @@ protected:
|
||||
using compile_ret_t = std::tuple<continuation_e>;
|
||||
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
|
||||
|
||||
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
|
||||
inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
|
||||
|
||||
void setup_module(std::string m) override {
|
||||
super::setup_module(m);
|
||||
@ -105,10 +104,10 @@ protected:
|
||||
|
||||
inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
|
||||
switch(reg_num){
|
||||
case traits::NEXT_PC:
|
||||
case traits<ARCH>::NEXT_PC:
|
||||
tu("*next_pc = {:#x};", pc.val);
|
||||
break;
|
||||
case traits::PC:
|
||||
case traits<ARCH>::PC:
|
||||
tu("*pc = {:#x};", pc.val);
|
||||
break;
|
||||
default:
|
||||
@ -124,7 +123,7 @@ protected:
|
||||
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
|
||||
enum { LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)), LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16)) };
|
||||
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
|
||||
|
||||
std::array<compile_func, LUT_SIZE> lut;
|
||||
|
||||
@ -171,12 +170,6 @@ protected:
|
||||
}
|
||||
return lut_val;
|
||||
}
|
||||
template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
|
||||
inline S sext(U from) {
|
||||
auto mask = (1ULL<<W) - 1;
|
||||
auto sign_mask = 1ULL<<(W-1);
|
||||
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
|
||||
}
|
||||
|
||||
private:
|
||||
/****************************************************************************
|
||||
@ -192,28 +185,13 @@ private:
|
||||
const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
|
||||
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
|
||||
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
|
||||
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
|
||||
{${instr.length}, 0b${instr.value}, 0b${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
|
||||
}};
|
||||
|
||||
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
|
||||
/* instruction ${idx}: ${instr.name} */
|
||||
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
|
||||
tu("${instr.name}_{:#010x}:", pc.val);
|
||||
vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
|
||||
<%instr.fields.eachLine{%>${it}
|
||||
<%}%>if(this->disass_enabled){
|
||||
/* generate console output when executing the command */<%instr.disass.eachLine{%>
|
||||
${it}<%}%>
|
||||
}
|
||||
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
|
||||
pc=pc+4;
|
||||
gen_set_pc(tu, pc, traits::NEXT_PC);
|
||||
tu.open_scope();<%instr.behavior.eachLine{%>
|
||||
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){<%instr.code.eachLine{%>
|
||||
${it}<%}%>
|
||||
tu.close_scope();
|
||||
vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
|
||||
gen_trap_check(tu);
|
||||
return returnValue;
|
||||
}
|
||||
<%}%>
|
||||
/****************************************************************************
|
||||
@ -255,20 +233,20 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
|
||||
// we fetch at max 4 byte, alignment is 2
|
||||
enum {TRAP_ID=1<<16};
|
||||
code_word_t insn = 0;
|
||||
// const typename traits::addr_t upper_bits = ~traits::PGMASK;
|
||||
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
|
||||
phys_addr_t paddr(pc);
|
||||
auto *const data = (uint8_t *)&insn;
|
||||
paddr = this->core.v2p(pc);
|
||||
// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
||||
// auto res = this->core.read(paddr, 2, data);
|
||||
// if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
// if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
|
||||
// res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
|
||||
// }
|
||||
// } else {
|
||||
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
||||
auto res = this->core.read(paddr, 2, data);
|
||||
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
|
||||
res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
|
||||
}
|
||||
} else {
|
||||
auto res = this->core.read(paddr, 4, data);
|
||||
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
// }
|
||||
}
|
||||
if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||
// curr pc on stack
|
||||
++inst_cnt;
|
||||
@ -282,13 +260,13 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
|
||||
tu(" *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
|
||||
tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
|
||||
tu("leave_trap(core_ptr, {});", lvl);
|
||||
tu.store(traits::NEXT_PC, tu.read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN));
|
||||
tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
|
||||
tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
|
||||
@ -296,8 +274,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
|
||||
tu("trap_entry:");
|
||||
tu("enter_trap(core_ptr, *trap_state, *pc, 0);");
|
||||
tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(),32));
|
||||
tu("enter_trap(core_ptr, *trap_state, *pc);");
|
||||
tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
|
||||
tu("return *next_pc;");
|
||||
}
|
||||
|
||||
@ -309,23 +287,5 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||
return std::unique_ptr<vm_if>(ret);
|
||||
}
|
||||
} // namesapce tcc
|
||||
}
|
||||
} // namespace iss
|
||||
|
||||
#include <iss/factory.h>
|
||||
#include <iss/arch/riscv_hart_m_p.h>
|
||||
#include <iss/arch/riscv_hart_mu_p.h>
|
||||
namespace iss {
|
||||
namespace {
|
||||
volatile std::array<bool, 2> dummy = {
|
||||
core_factory::instance().register_creator("${coreDef.name.toLowerCase()|m_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto* lcpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()>();
|
||||
return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
|
||||
}),
|
||||
core_factory::instance().register_creator("${coreDef.name.toLowerCase()|mu_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto* lcpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()>();
|
||||
return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
|
||||
})
|
||||
};
|
||||
}
|
||||
}
|
944
incl/iss/arch/riscv_hart_m_p.h
Normal file
944
incl/iss/arch/riscv_hart_m_p.h
Normal file
@ -0,0 +1,944 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, 2018, MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contributors:
|
||||
* eyck@minres.com - initial implementation
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _RISCV_CORE_H_
|
||||
#define _RISCV_CORE_H_
|
||||
|
||||
#include "iss/arch/traits.h"
|
||||
#include "iss/arch_if.h"
|
||||
#include "iss/instrumentation_if.h"
|
||||
#include "iss/log_categories.h"
|
||||
#include "iss/vm_if.h"
|
||||
#ifndef FMT_HEADER_ONLY
|
||||
#define FMT_HEADER_ONLY
|
||||
#endif
|
||||
#include <array>
|
||||
#include <elfio/elfio.hpp>
|
||||
#include <fmt/format.h>
|
||||
#include <iomanip>
|
||||
#include <sstream>
|
||||
#include <type_traits>
|
||||
#include <unordered_map>
|
||||
#include <util/bit_field.h>
|
||||
#include <util/ities.h>
|
||||
#include <util/sparse_array.h>
|
||||
|
||||
#if defined(__GNUC__)
|
||||
#define likely(x) __builtin_expect(!!(x), 1)
|
||||
#define unlikely(x) __builtin_expect(!!(x), 0)
|
||||
#else
|
||||
#define likely(x) x
|
||||
#define unlikely(x) x
|
||||
#endif
|
||||
|
||||
namespace iss {
|
||||
namespace arch {
|
||||
|
||||
enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
|
||||
|
||||
enum riscv_csr {
|
||||
/* user-level CSR */
|
||||
// User Trap Setup
|
||||
ustatus = 0x000,
|
||||
uie = 0x004,
|
||||
utvec = 0x005,
|
||||
// User Trap Handling
|
||||
uscratch = 0x040,
|
||||
uepc = 0x041,
|
||||
ucause = 0x042,
|
||||
utval = 0x043,
|
||||
uip = 0x044,
|
||||
// User Floating-Point CSRs
|
||||
fflags = 0x001,
|
||||
frm = 0x002,
|
||||
fcsr = 0x003,
|
||||
// User Counter/Timers
|
||||
cycle = 0xC00,
|
||||
time = 0xC01,
|
||||
instret = 0xC02,
|
||||
hpmcounter3 = 0xC03,
|
||||
hpmcounter4 = 0xC04,
|
||||
/*...*/
|
||||
hpmcounter31 = 0xC1F,
|
||||
cycleh = 0xC80,
|
||||
timeh = 0xC81,
|
||||
instreth = 0xC82,
|
||||
hpmcounter3h = 0xC83,
|
||||
hpmcounter4h = 0xC84,
|
||||
/*...*/
|
||||
hpmcounter31h = 0xC9F,
|
||||
/* supervisor-level CSR */
|
||||
// Supervisor Trap Setup
|
||||
sstatus = 0x100,
|
||||
sedeleg = 0x102,
|
||||
sideleg = 0x103,
|
||||
sie = 0x104,
|
||||
stvec = 0x105,
|
||||
scounteren = 0x106,
|
||||
// Supervisor Trap Handling
|
||||
sscratch = 0x140,
|
||||
sepc = 0x141,
|
||||
scause = 0x142,
|
||||
stval = 0x143,
|
||||
sip = 0x144,
|
||||
// Supervisor Protection and Translation
|
||||
satp = 0x180,
|
||||
/* machine-level CSR */
|
||||
// Machine Information Registers
|
||||
mvendorid = 0xF11,
|
||||
marchid = 0xF12,
|
||||
mimpid = 0xF13,
|
||||
mhartid = 0xF14,
|
||||
// Machine Trap Setup
|
||||
mstatus = 0x300,
|
||||
misa = 0x301,
|
||||
medeleg = 0x302,
|
||||
mideleg = 0x303,
|
||||
mie = 0x304,
|
||||
mtvec = 0x305,
|
||||
mcounteren = 0x306,
|
||||
// Machine Trap Handling
|
||||
mscratch = 0x340,
|
||||
mepc = 0x341,
|
||||
mcause = 0x342,
|
||||
mtval = 0x343,
|
||||
mip = 0x344,
|
||||
// Machine Protection and Translation
|
||||
pmpcfg0 = 0x3A0,
|
||||
pmpcfg1 = 0x3A1,
|
||||
pmpcfg2 = 0x3A2,
|
||||
pmpcfg3 = 0x3A3,
|
||||
pmpaddr0 = 0x3B0,
|
||||
pmpaddr1 = 0x3B1,
|
||||
/*...*/
|
||||
pmpaddr15 = 0x3BF,
|
||||
// Machine Counter/Timers
|
||||
mcycle = 0xB00,
|
||||
minstret = 0xB02,
|
||||
mhpmcounter3 = 0xB03,
|
||||
mhpmcounter4 = 0xB04,
|
||||
/*...*/
|
||||
mhpmcounter31 = 0xB1F,
|
||||
mcycleh = 0xB80,
|
||||
minstreth = 0xB82,
|
||||
mhpmcounter3h = 0xB83,
|
||||
mhpmcounter4h = 0xB84,
|
||||
/*...*/
|
||||
mhpmcounter31h = 0xB9F,
|
||||
// Machine Counter Setup
|
||||
mhpmevent3 = 0x323,
|
||||
mhpmevent4 = 0x324,
|
||||
/*...*/
|
||||
mhpmevent31 = 0x33F,
|
||||
// Debug/Trace Registers (shared with Debug Mode)
|
||||
tselect = 0x7A0,
|
||||
tdata1 = 0x7A1,
|
||||
tdata2 = 0x7A2,
|
||||
tdata3 = 0x7A3,
|
||||
// Debug Mode Registers
|
||||
dcsr = 0x7B0,
|
||||
dpc = 0x7B1,
|
||||
dscratch = 0x7B2
|
||||
};
|
||||
|
||||
namespace {
|
||||
|
||||
std::array<const char *, 16> trap_str = {{""
|
||||
"Instruction address misaligned", // 0
|
||||
"Instruction access fault", // 1
|
||||
"Illegal instruction", // 2
|
||||
"Breakpoint", // 3
|
||||
"Load address misaligned", // 4
|
||||
"Load access fault", // 5
|
||||
"Store/AMO address misaligned", // 6
|
||||
"Store/AMO access fault", // 7
|
||||
"Environment call from U-mode", // 8
|
||||
"Environment call from S-mode", // 9
|
||||
"Reserved", // a
|
||||
"Environment call from M-mode", // b
|
||||
"Instruction page fault", // c
|
||||
"Load page fault", // d
|
||||
"Reserved", // e
|
||||
"Store/AMO page fault"}};
|
||||
std::array<const char *, 12> irq_str = {
|
||||
{"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
|
||||
"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
|
||||
"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
|
||||
|
||||
enum {
|
||||
PGSHIFT = 12,
|
||||
PTE_PPN_SHIFT = 10,
|
||||
// page table entry (PTE) fields
|
||||
PTE_V = 0x001, // Valid
|
||||
PTE_R = 0x002, // Read
|
||||
PTE_W = 0x004, // Write
|
||||
PTE_X = 0x008, // Execute
|
||||
PTE_U = 0x010, // User
|
||||
PTE_G = 0x020, // Global
|
||||
PTE_A = 0x040, // Accessed
|
||||
PTE_D = 0x080, // Dirty
|
||||
PTE_SOFT = 0x300 // Reserved for Software
|
||||
};
|
||||
|
||||
template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
|
||||
|
||||
enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3 };
|
||||
|
||||
enum {
|
||||
ISA_A = 1,
|
||||
ISA_B = 1 << 1,
|
||||
ISA_C = 1 << 2,
|
||||
ISA_D = 1 << 3,
|
||||
ISA_E = 1 << 4,
|
||||
ISA_F = 1 << 5,
|
||||
ISA_G = 1 << 6,
|
||||
ISA_I = 1 << 8,
|
||||
ISA_M = 1 << 12,
|
||||
ISA_N = 1 << 13,
|
||||
ISA_Q = 1 << 16,
|
||||
ISA_S = 1 << 18,
|
||||
ISA_U = 1 << 20
|
||||
};
|
||||
|
||||
class trap_load_access_fault : public trap_access {
|
||||
public:
|
||||
trap_load_access_fault(uint64_t badaddr)
|
||||
: trap_access(5 << 16, badaddr) {}
|
||||
};
|
||||
class illegal_instruction_fault : public trap_access {
|
||||
public:
|
||||
illegal_instruction_fault(uint64_t badaddr)
|
||||
: trap_access(2 << 16, badaddr) {}
|
||||
};
|
||||
} // namespace
|
||||
|
||||
template <typename BASE> class riscv_hart_m_p : public BASE {
|
||||
public:
|
||||
using super = BASE;
|
||||
using this_class = riscv_hart_m_p<BASE>;
|
||||
using phys_addr_t = typename super::phys_addr_t;
|
||||
using reg_t = typename super::reg_t;
|
||||
using addr_t = typename super::addr_t;
|
||||
|
||||
using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
|
||||
using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
|
||||
|
||||
// primary template
|
||||
template <class T, class Enable = void> struct hart_state {};
|
||||
// specialization 32bit
|
||||
template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
|
||||
public:
|
||||
BEGIN_BF_DECL(mstatus_t, T);
|
||||
// SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
|
||||
BF_FIELD(SD, 31, 1);
|
||||
// Trap SRET
|
||||
BF_FIELD(TSR, 22, 1);
|
||||
// Timeout Wait
|
||||
BF_FIELD(TW, 21, 1);
|
||||
// Trap Virtual Memory
|
||||
BF_FIELD(TVM, 20, 1);
|
||||
// Make eXecutable Readable
|
||||
BF_FIELD(MXR, 19, 1);
|
||||
// permit Supervisor User Memory access
|
||||
BF_FIELD(SUM, 18, 1);
|
||||
// Modify PRiVilege
|
||||
BF_FIELD(MPRV, 17, 1);
|
||||
// status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
|
||||
BF_FIELD(XS, 15, 2);
|
||||
// floating-point unit status Off/Initial/Clean/Dirty
|
||||
BF_FIELD(FS, 13, 2);
|
||||
// machine previous privilege
|
||||
BF_FIELD(MPP, 11, 2);
|
||||
// supervisor previous privilege
|
||||
BF_FIELD(SPP, 8, 1);
|
||||
// previous machine interrupt-enable
|
||||
BF_FIELD(MPIE, 7, 1);
|
||||
// previous supervisor interrupt-enable
|
||||
BF_FIELD(SPIE, 5, 1);
|
||||
// previous user interrupt-enable
|
||||
BF_FIELD(UPIE, 4, 1);
|
||||
// machine interrupt-enable
|
||||
BF_FIELD(MIE, 3, 1);
|
||||
// supervisor interrupt-enable
|
||||
BF_FIELD(SIE, 1, 1);
|
||||
// user interrupt-enable
|
||||
BF_FIELD(UIE, 0, 1);
|
||||
END_BF_DECL();
|
||||
|
||||
mstatus_t mstatus;
|
||||
|
||||
static const reg_t mstatus_reset_val = 0;
|
||||
|
||||
void write_mstatus(T val) {
|
||||
auto mask = get_mask();
|
||||
auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
|
||||
mstatus = new_val;
|
||||
}
|
||||
|
||||
T satp;
|
||||
|
||||
static constexpr T get_misa() { return (1UL << 30) | ISA_I | ISA_M | ISA_A | ISA_U | ISA_S | ISA_M; }
|
||||
|
||||
static constexpr uint32_t get_mask() {
|
||||
return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011 // only machine mode is supported
|
||||
}
|
||||
};
|
||||
|
||||
constexpr reg_t get_irq_mask() {
|
||||
return 0b101110111011; // only machine mode is supported
|
||||
}
|
||||
|
||||
riscv_hart_m_p();
|
||||
virtual ~riscv_hart_m_p() = default;
|
||||
|
||||
void reset(uint64_t address) override;
|
||||
|
||||
std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
|
||||
|
||||
iss::status read(const address_type type, const access_type access, const uint32_t space,
|
||||
const uint64_t addr, const unsigned length, uint8_t *const data) override;
|
||||
iss::status write(const address_type type, const access_type access, const uint32_t space,
|
||||
const uint64_t addr, const unsigned length, const uint8_t *const data) override;
|
||||
|
||||
virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data); }
|
||||
virtual uint64_t enter_trap(uint64_t flags, uint64_t addr) override;
|
||||
virtual uint64_t leave_trap(uint64_t flags) override;
|
||||
|
||||
const reg_t& get_mhartid() const { return mhartid_reg; }
|
||||
void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
|
||||
|
||||
void disass_output(uint64_t pc, const std::string instr) override {
|
||||
CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [s:0x{:x};c:{}]",
|
||||
pc, instr, (reg_t)state.mstatus, this->reg.icount);
|
||||
};
|
||||
|
||||
iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
|
||||
|
||||
protected:
|
||||
struct riscv_instrumentation_if : public iss::instrumentation_if {
|
||||
|
||||
riscv_instrumentation_if(riscv_hart_m_p<BASE> &arch)
|
||||
: arch(arch) {}
|
||||
/**
|
||||
* get the name of this architecture
|
||||
*
|
||||
* @return the name of this architecture
|
||||
*/
|
||||
const std::string core_type_name() const override { return traits<BASE>::core_type; }
|
||||
|
||||
virtual uint64_t get_pc() { return arch.get_pc(); };
|
||||
|
||||
virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
|
||||
|
||||
virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
|
||||
|
||||
riscv_hart_m_p<BASE> &arch;
|
||||
};
|
||||
|
||||
friend struct riscv_instrumentation_if;
|
||||
addr_t get_pc() { return this->reg.PC; }
|
||||
addr_t get_next_pc() { return this->reg.NEXT_PC; }
|
||||
|
||||
virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
|
||||
virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
|
||||
|
||||
virtual iss::status read_csr(unsigned addr, reg_t &val);
|
||||
virtual iss::status write_csr(unsigned addr, reg_t val);
|
||||
|
||||
hart_state<reg_t> state;
|
||||
uint64_t cycle_offset;
|
||||
reg_t fault_data;
|
||||
uint64_t tohost = tohost_dflt;
|
||||
uint64_t fromhost = fromhost_dflt;
|
||||
unsigned to_host_wr_cnt = 0;
|
||||
riscv_instrumentation_if instr_if;
|
||||
|
||||
using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
|
||||
using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
|
||||
using csr_page_type = typename csr_type::page_type;
|
||||
mem_type mem;
|
||||
csr_type csr;
|
||||
std::stringstream uart_buf;
|
||||
std::unordered_map<reg_t, uint64_t> ptw;
|
||||
std::unordered_map<uint64_t, uint8_t> atomic_reservation;
|
||||
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
|
||||
std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
|
||||
|
||||
private:
|
||||
iss::status read_cycle(unsigned addr, reg_t &val);
|
||||
iss::status read_time(unsigned addr, reg_t &val);
|
||||
iss::status read_status(unsigned addr, reg_t &val);
|
||||
iss::status write_status(unsigned addr, reg_t val);
|
||||
iss::status read_ie(unsigned addr, reg_t &val);
|
||||
iss::status write_ie(unsigned addr, reg_t val);
|
||||
iss::status read_ip(unsigned addr, reg_t &val);
|
||||
iss::status write_ip(unsigned addr, reg_t val);
|
||||
iss::status read_hartid(unsigned addr, reg_t &val);
|
||||
|
||||
reg_t mhartid_reg{0xF};
|
||||
|
||||
protected:
|
||||
void check_interrupt();
|
||||
};
|
||||
|
||||
template <typename BASE>
|
||||
riscv_hart_m_p<BASE>::riscv_hart_m_p()
|
||||
: state()
|
||||
, cycle_offset(0)
|
||||
, instr_if(*this) {
|
||||
csr[misa] = hart_state<reg_t>::get_misa();
|
||||
uart_buf.str("");
|
||||
// read-only registers
|
||||
csr_wr_cb[misa] = nullptr;
|
||||
for (unsigned addr = mcycle; addr <= hpmcounter31; ++addr) csr_wr_cb[addr] = nullptr;
|
||||
for (unsigned addr = mcycleh; addr <= hpmcounter31h; ++addr) csr_wr_cb[addr] = nullptr;
|
||||
// special handling
|
||||
csr_rd_cb[time] = &riscv_hart_m_p<BASE>::read_time;
|
||||
csr_wr_cb[time] = nullptr;
|
||||
csr_rd_cb[timeh] = &riscv_hart_m_p<BASE>::read_time;
|
||||
csr_wr_cb[timeh] = nullptr;
|
||||
csr_rd_cb[mcycle] = &riscv_hart_m_p<BASE>::read_cycle;
|
||||
csr_rd_cb[mcycleh] = &riscv_hart_m_p<BASE>::read_cycle;
|
||||
csr_rd_cb[minstret] = &riscv_hart_m_p<BASE>::read_cycle;
|
||||
csr_rd_cb[minstreth] = &riscv_hart_m_p<BASE>::read_cycle;
|
||||
csr_rd_cb[mstatus] = &riscv_hart_m_p<BASE>::read_status;
|
||||
csr_wr_cb[mstatus] = &riscv_hart_m_p<BASE>::write_status;
|
||||
csr_rd_cb[mip] = &riscv_hart_m_p<BASE>::read_ip;
|
||||
csr_wr_cb[mip] = &riscv_hart_m_p<BASE>::write_ip;
|
||||
csr_rd_cb[mie] = &riscv_hart_m_p<BASE>::read_ie;
|
||||
csr_wr_cb[mie] = &riscv_hart_m_p<BASE>::write_ie;
|
||||
csr_rd_cb[mhartid] = &riscv_hart_m_p<BASE>::read_hartid;
|
||||
}
|
||||
|
||||
template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
|
||||
FILE *fp = fopen(name.c_str(), "r");
|
||||
if (fp) {
|
||||
std::array<char, 5> buf;
|
||||
auto n = fread(buf.data(), 1, 4, fp);
|
||||
if (n != 4) throw std::runtime_error("input file has insufficient size");
|
||||
buf[4] = 0;
|
||||
if (strcmp(buf.data() + 1, "ELF") == 0) {
|
||||
fclose(fp);
|
||||
// Create elfio reader
|
||||
ELFIO::elfio reader;
|
||||
// Load ELF data
|
||||
if (!reader.load(name)) throw std::runtime_error("could not process elf file");
|
||||
// check elf properties
|
||||
if (reader.get_class() != ELFCLASS32)
|
||||
if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
|
||||
if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
|
||||
if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
|
||||
for (const auto pseg : reader.segments) {
|
||||
const auto fsize = pseg->get_file_size(); // 0x42c/0x0
|
||||
const auto seg_data = pseg->get_data();
|
||||
if (fsize > 0) {
|
||||
auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE,
|
||||
traits<BASE>::MEM, pseg->get_physical_address(),
|
||||
fsize, reinterpret_cast<const uint8_t *const>(seg_data));
|
||||
if (res != iss::Ok)
|
||||
LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex
|
||||
<< pseg->get_physical_address();
|
||||
}
|
||||
}
|
||||
for (const auto sec : reader.sections) {
|
||||
if (sec->get_name() == ".tohost") {
|
||||
tohost = sec->get_address();
|
||||
fromhost = tohost + 0x40;
|
||||
}
|
||||
}
|
||||
|
||||
return std::make_pair(reader.get_entry(), true);
|
||||
}
|
||||
throw std::runtime_error("memory load file is not a valid elf file");
|
||||
}
|
||||
throw std::runtime_error("memory load file not found");
|
||||
}
|
||||
|
||||
template <typename BASE>
|
||||
iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_type access, const uint32_t space,
|
||||
const uint64_t addr, const unsigned length, uint8_t *const data) {
|
||||
#ifndef NDEBUG
|
||||
if (access && iss::access_type::DEBUG) {
|
||||
LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
|
||||
} else if(access && iss::access_type::FETCH){
|
||||
LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr;
|
||||
} else {
|
||||
LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr;
|
||||
}
|
||||
#endif
|
||||
try {
|
||||
switch (space) {
|
||||
case traits<BASE>::MEM: {
|
||||
if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
|
||||
fault_data = addr;
|
||||
if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
|
||||
this->reg.trap_state = (1 << 31); // issue trap 0
|
||||
return iss::Err;
|
||||
}
|
||||
try {
|
||||
auto res = type==iss::address_type::PHYSICAL?
|
||||
read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
|
||||
read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
|
||||
if (unlikely(res != iss::Ok)) this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
|
||||
return res;
|
||||
} catch (trap_access &ta) {
|
||||
this->reg.trap_state = (1 << 31) | ta.id;
|
||||
return iss::Err;
|
||||
}
|
||||
} break;
|
||||
case traits<BASE>::CSR: {
|
||||
if (length != sizeof(reg_t)) return iss::Err;
|
||||
return read_csr(addr, *reinterpret_cast<reg_t *const>(data));
|
||||
} break;
|
||||
case traits<BASE>::FENCE: {
|
||||
if ((addr + length) > mem.size()) return iss::Err;
|
||||
return iss::Ok;
|
||||
} break;
|
||||
case traits<BASE>::RES: {
|
||||
auto it = atomic_reservation.find(addr);
|
||||
if (it != atomic_reservation.end() && it->second != 0) {
|
||||
memset(data, 0xff, length);
|
||||
atomic_reservation.erase(addr);
|
||||
} else
|
||||
memset(data, 0, length);
|
||||
} break;
|
||||
default:
|
||||
return iss::Err; // assert("Not supported");
|
||||
}
|
||||
return iss::Ok;
|
||||
} catch (trap_access &ta) {
|
||||
this->reg.trap_state = (1 << 31) | ta.id;
|
||||
return iss::Err;
|
||||
}
|
||||
}
|
||||
|
||||
template <typename BASE>
|
||||
iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_type access, const uint32_t space,
|
||||
const uint64_t addr, const unsigned length, const uint8_t *const data) {
|
||||
#ifndef NDEBUG
|
||||
const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
|
||||
switch (length) {
|
||||
case 8:
|
||||
LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec
|
||||
<< ") @addr 0x" << std::hex << addr;
|
||||
break;
|
||||
case 4:
|
||||
LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec
|
||||
<< ") @addr 0x" << std::hex << addr;
|
||||
break;
|
||||
case 2:
|
||||
LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec
|
||||
<< ") @addr 0x" << std::hex << addr;
|
||||
break;
|
||||
case 1:
|
||||
LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec
|
||||
<< ") @addr 0x" << std::hex << addr;
|
||||
break;
|
||||
default:
|
||||
LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
|
||||
}
|
||||
#endif
|
||||
try {
|
||||
switch (space) {
|
||||
case traits<BASE>::MEM: {
|
||||
if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
|
||||
fault_data = addr;
|
||||
if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
|
||||
this->reg.trap_state = (1 << 31); // issue trap 0
|
||||
return iss::Err;
|
||||
}
|
||||
try {
|
||||
auto res = type==iss::address_type::PHYSICAL?
|
||||
write_mem(phys_addr_t{access, space, addr}, length, data):
|
||||
write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
|
||||
if (unlikely(res != iss::Ok))
|
||||
this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 7 (Store/AMO access fault)
|
||||
return res;
|
||||
} catch (trap_access &ta) {
|
||||
this->reg.trap_state = (1 << 31) | ta.id;
|
||||
return iss::Err;
|
||||
}
|
||||
|
||||
phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
|
||||
if ((paddr.val + length) > mem.size()) return iss::Err;
|
||||
switch (paddr.val) {
|
||||
case 0x10013000: // UART0 base, TXFIFO reg
|
||||
case 0x10023000: // UART1 base, TXFIFO reg
|
||||
uart_buf << (char)data[0];
|
||||
if (((char)data[0]) == '\n' || data[0] == 0) {
|
||||
// LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
|
||||
// '"<<uart_buf.str()<<"'";
|
||||
std::cout << uart_buf.str();
|
||||
uart_buf.str("");
|
||||
}
|
||||
return iss::Ok;
|
||||
case 0x10008000: { // HFROSC base, hfrosccfg reg
|
||||
auto &p = mem(paddr.val / mem.page_size);
|
||||
auto offs = paddr.val & mem.page_addr_mask;
|
||||
std::copy(data, data + length, p.data() + offs);
|
||||
auto &x = *(p.data() + offs + 3);
|
||||
if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
|
||||
return iss::Ok;
|
||||
}
|
||||
case 0x10008008: { // HFROSC base, pllcfg reg
|
||||
auto &p = mem(paddr.val / mem.page_size);
|
||||
auto offs = paddr.val & mem.page_addr_mask;
|
||||
std::copy(data, data + length, p.data() + offs);
|
||||
auto &x = *(p.data() + offs + 3);
|
||||
x |= 0x80; // set pll lock upon writing
|
||||
return iss::Ok;
|
||||
} break;
|
||||
default: {}
|
||||
}
|
||||
} break;
|
||||
case traits<BASE>::CSR: {
|
||||
if (length != sizeof(reg_t)) return iss::Err;
|
||||
return write_csr(addr, *reinterpret_cast<const reg_t *>(data));
|
||||
} break;
|
||||
case traits<BASE>::FENCE: {
|
||||
if ((addr + length) > mem.size()) return iss::Err;
|
||||
switch (addr) {
|
||||
case 2:
|
||||
case 3: {
|
||||
ptw.clear();
|
||||
auto tvm = state.mstatus.TVM;
|
||||
return iss::Ok;
|
||||
}
|
||||
}
|
||||
} break;
|
||||
case traits<BASE>::RES: {
|
||||
atomic_reservation[addr] = data[0];
|
||||
} break;
|
||||
default:
|
||||
return iss::Err;
|
||||
}
|
||||
return iss::Ok;
|
||||
} catch (trap_access &ta) {
|
||||
this->reg.trap_state = (1 << 31) | ta.id;
|
||||
return iss::Err;
|
||||
}
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) {
|
||||
if (addr >= csr.size()) return iss::Err;
|
||||
auto req_priv_lvl = (addr >> 8) & 0x3;
|
||||
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
|
||||
auto it = csr_rd_cb.find(addr);
|
||||
if (it == csr_rd_cb.end()) {
|
||||
val = csr[addr & csr.page_addr_mask];
|
||||
return iss::Ok;
|
||||
}
|
||||
rd_csr_f f = it->second;
|
||||
if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
|
||||
return (this->*f)(addr, val);
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) {
|
||||
if (addr >= csr.size()) return iss::Err;
|
||||
auto req_priv_lvl = (addr >> 8) & 0x3;
|
||||
if (this->reg.machine_state < req_priv_lvl)
|
||||
throw illegal_instruction_fault(this->fault_data);
|
||||
if((addr&0xc00)==0xc00)
|
||||
throw illegal_instruction_fault(this->fault_data);
|
||||
auto it = csr_wr_cb.find(addr);
|
||||
if (it == csr_wr_cb.end()) {
|
||||
csr[addr & csr.page_addr_mask] = val;
|
||||
return iss::Ok;
|
||||
}
|
||||
wr_csr_f f = it->second;
|
||||
if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
|
||||
return (this->*f)(addr, val);
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
|
||||
auto cycle_val = this->reg.icount + cycle_offset;
|
||||
if (addr == mcycle) {
|
||||
val = static_cast<reg_t>(cycle_val);
|
||||
} else if (addr == mcycleh) {
|
||||
if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
|
||||
val = static_cast<reg_t>(cycle_val >> 32);
|
||||
}
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
|
||||
uint64_t time_val = (this->reg.icount + cycle_offset) / (100000000 / 32768 - 1); //-> ~3052;
|
||||
if (addr == time) {
|
||||
val = static_cast<reg_t>(time_val);
|
||||
} else if (addr == timeh) {
|
||||
if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
|
||||
val = static_cast<reg_t>(time_val >> 32);
|
||||
}
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_status(unsigned addr, reg_t &val) {
|
||||
val = state.mstatus & hart_state<reg_t>::get_mask();
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned addr, reg_t val) {
|
||||
state.write_mstatus(val);
|
||||
check_interrupt();
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) {
|
||||
val = csr[mie];
|
||||
val &= csr[mideleg];
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_hartid(unsigned addr, reg_t &val) {
|
||||
val = mhartid_reg;
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned addr, reg_t val) {
|
||||
auto mask = get_irq_mask();
|
||||
csr[mie] = (csr[mie] & ~mask) | (val & mask);
|
||||
check_interrupt();
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ip(unsigned addr, reg_t &val) {
|
||||
val = csr[mip];
|
||||
val &= csr[mideleg];
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned addr, reg_t val) {
|
||||
auto mask = get_irq_mask();
|
||||
mask &= ~(1 << 7); // MTIP is read only
|
||||
csr[mip] = (csr[mip] & ~mask) | (val & mask);
|
||||
check_interrupt();
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE>
|
||||
iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
|
||||
if ((paddr.val + length) > mem.size()) return iss::Err;
|
||||
switch (paddr.val) {
|
||||
case 0x0200BFF8: { // CLINT base, mtime reg
|
||||
if (sizeof(reg_t) < length) return iss::Err;
|
||||
reg_t time_val;
|
||||
this->read_csr(time, time_val);
|
||||
std::copy((uint8_t *)&time_val, ((uint8_t *)&time_val) + length, data);
|
||||
} break;
|
||||
case 0x10008000: {
|
||||
const mem_type::page_type &p = mem(paddr.val / mem.page_size);
|
||||
uint64_t offs = paddr.val & mem.page_addr_mask;
|
||||
std::copy(p.data() + offs, p.data() + offs + length, data);
|
||||
if (this->reg.icount > 30000) data[3] |= 0x80;
|
||||
} break;
|
||||
default: {
|
||||
const auto &p = mem(paddr.val / mem.page_size);
|
||||
auto offs = paddr.val & mem.page_addr_mask;
|
||||
std::copy(p.data() + offs, p.data() + offs + length, data);
|
||||
}
|
||||
}
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE>
|
||||
iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
|
||||
if ((paddr.val + length) > mem.size()) return iss::Err;
|
||||
switch (paddr.val) {
|
||||
case 0x10013000: // UART0 base, TXFIFO reg
|
||||
case 0x10023000: // UART1 base, TXFIFO reg
|
||||
uart_buf << (char)data[0];
|
||||
if (((char)data[0]) == '\n' || data[0] == 0) {
|
||||
// LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
|
||||
// '"<<uart_buf.str()<<"'";
|
||||
std::cout << uart_buf.str();
|
||||
uart_buf.str("");
|
||||
}
|
||||
break;
|
||||
case 0x10008000: { // HFROSC base, hfrosccfg reg
|
||||
mem_type::page_type &p = mem(paddr.val / mem.page_size);
|
||||
size_t offs = paddr.val & mem.page_addr_mask;
|
||||
std::copy(data, data + length, p.data() + offs);
|
||||
uint8_t &x = *(p.data() + offs + 3);
|
||||
if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
|
||||
} break;
|
||||
case 0x10008008: { // HFROSC base, pllcfg reg
|
||||
mem_type::page_type &p = mem(paddr.val / mem.page_size);
|
||||
size_t offs = paddr.val & mem.page_addr_mask;
|
||||
std::copy(data, data + length, p.data() + offs);
|
||||
uint8_t &x = *(p.data() + offs + 3);
|
||||
x |= 0x80; // set pll lock upon writing
|
||||
} break;
|
||||
default: {
|
||||
mem_type::page_type &p = mem(paddr.val / mem.page_size);
|
||||
std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
|
||||
// tohost handling in case of riscv-test
|
||||
if (paddr.access && iss::access_type::FUNC) {
|
||||
auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4));
|
||||
auto tohost_lower =
|
||||
(traits<BASE>::XLEN == 32 && paddr.val == tohost);
|
||||
if (tohost_lower || tohost_upper) {
|
||||
uint64_t hostvar = *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask));
|
||||
if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
|
||||
switch (hostvar >> 48) {
|
||||
case 0:
|
||||
if (hostvar != 0x1) {
|
||||
LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
|
||||
<< "), stopping simulation";
|
||||
} else {
|
||||
LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
|
||||
<< "), stopping simulation";
|
||||
}
|
||||
this->reg.trap_state=std::numeric_limits<uint32_t>::max();
|
||||
this->interrupt_sim=hostvar;
|
||||
break;
|
||||
//throw(iss::simulation_stopped(hostvar));
|
||||
case 0x0101: {
|
||||
char c = static_cast<char>(hostvar & 0xff);
|
||||
if (c == '\n' || c == 0) {
|
||||
LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
|
||||
uart_buf.str("");
|
||||
} else
|
||||
uart_buf << c;
|
||||
to_host_wr_cnt = 0;
|
||||
} break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else if (tohost_lower)
|
||||
to_host_wr_cnt++;
|
||||
} else if (traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) {
|
||||
uint64_t fhostvar = *reinterpret_cast<uint64_t *>(p.data() + (fromhost & mem.page_addr_mask));
|
||||
*reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template <typename BASE> inline void riscv_hart_m_p<BASE>::reset(uint64_t address) {
|
||||
BASE::reset(address);
|
||||
state.mstatus = hart_state<reg_t>::mstatus_reset_val;
|
||||
}
|
||||
|
||||
template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
|
||||
auto ideleg = csr[mideleg];
|
||||
// Multiple simultaneous interrupts and traps at the same privilege level are
|
||||
// handled in the following decreasing priority order:
|
||||
// external interrupts, software interrupts, timer interrupts, then finally
|
||||
// any synchronous traps.
|
||||
auto ena_irq = csr[mip] & csr[mie];
|
||||
|
||||
bool mie = state.mstatus.MIE;
|
||||
auto m_enabled = this->reg.machine_state < PRIV_M || (this->reg.machine_state == PRIV_M && mie);
|
||||
auto enabled_interrupts = m_enabled ? ena_irq & ~ideleg : 0;
|
||||
|
||||
if (enabled_interrupts != 0) {
|
||||
int res = 0;
|
||||
while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++;
|
||||
this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
|
||||
}
|
||||
}
|
||||
|
||||
template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flags, uint64_t addr) {
|
||||
// flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
|
||||
// calculate and write mcause val
|
||||
auto trap_id = bit_sub<0, 16>(flags);
|
||||
auto cause = bit_sub<16, 15>(flags);
|
||||
if (trap_id == 0 && cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
|
||||
// calculate effective privilege level
|
||||
if (trap_id == 0) { // exception
|
||||
// store ret addr in xepc register
|
||||
csr[mepc] = static_cast<reg_t>(addr); // store actual address instruction of exception
|
||||
csr[mtval] = fault_data;
|
||||
fault_data = 0;
|
||||
} else {
|
||||
csr[mepc] = this->reg.NEXT_PC; // store next address if interrupt
|
||||
this->reg.pending_trap = 0;
|
||||
}
|
||||
csr[mcause] = (trap_id << 31) + cause;
|
||||
// update mstatus
|
||||
// xPP field of mstatus is written with the active privilege mode at the time
|
||||
// of the trap; the x PIE field of mstatus
|
||||
// is written with the value of the active interrupt-enable bit at the time of
|
||||
// the trap; and the x IE field of mstatus
|
||||
// is cleared
|
||||
// store the actual privilege level in yPP and store interrupt enable flags
|
||||
state.mstatus.MPP = PRIV_M;
|
||||
state.mstatus.MPIE = state.mstatus.MIE;
|
||||
state.mstatus.MIE = false;
|
||||
|
||||
// get trap vector
|
||||
auto ivec = csr[mtvec];
|
||||
// calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
|
||||
// bits in mtvec
|
||||
this->reg.NEXT_PC = ivec & ~0x1UL;
|
||||
if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
|
||||
// reset trap state
|
||||
this->reg.machine_state = PRIV_M;
|
||||
this->reg.trap_state = 0;
|
||||
std::array<char, 32> buffer;
|
||||
sprintf(buffer.data(), "0x%016lx", addr);
|
||||
if((flags&0xffffffff) != 0xffffffff)
|
||||
CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
|
||||
<< (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
|
||||
<< " at address " << buffer.data() << " occurred";
|
||||
return this->reg.NEXT_PC;
|
||||
}
|
||||
|
||||
template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
|
||||
auto cur_priv = this->reg.machine_state;
|
||||
auto inst_priv = flags & 0x3;
|
||||
auto status = state.mstatus;
|
||||
|
||||
// pop the relevant lower-privilege interrupt enable and privilege mode stack
|
||||
// clear respective yIE
|
||||
if (inst_priv == PRIV_M) {
|
||||
this->reg.machine_state = state.mstatus.MPP;
|
||||
state.mstatus.MPP = 0; // clear mpp to U mode
|
||||
state.mstatus.MIE = state.mstatus.MPIE;
|
||||
} else {
|
||||
CLOG(ERROR, disass) << "Unsupported mode:" << inst_priv;
|
||||
}
|
||||
|
||||
// sets the pc to the value stored in the x epc register.
|
||||
this->reg.NEXT_PC = csr[mepc];
|
||||
CLOG(INFO, disass) << "Executing xRET";
|
||||
return this->reg.NEXT_PC;
|
||||
}
|
||||
|
||||
} // namespace arch
|
||||
} // namespace iss
|
||||
|
||||
#endif /* _RISCV_CORE_H_ */
|
252
incl/iss/arch/tgf_b.h
Normal file
252
incl/iss/arch/tgf_b.h
Normal file
@ -0,0 +1,252 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifndef _TGF_B_H_
|
||||
#define _TGF_B_H_
|
||||
|
||||
#include <array>
|
||||
#include <iss/arch/traits.h>
|
||||
#include <iss/arch_if.h>
|
||||
#include <iss/vm_if.h>
|
||||
|
||||
namespace iss {
|
||||
namespace arch {
|
||||
|
||||
struct tgf_b;
|
||||
|
||||
template <> struct traits<tgf_b> {
|
||||
|
||||
constexpr static char const* const core_type = "TGF_B";
|
||||
|
||||
static constexpr std::array<const char*, 33> reg_names{
|
||||
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
|
||||
|
||||
static constexpr std::array<const char*, 33> reg_aliases{
|
||||
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
|
||||
|
||||
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0xfff};
|
||||
|
||||
constexpr static unsigned FP_REGS_SIZE = 0;
|
||||
|
||||
enum reg_e {
|
||||
X0,
|
||||
X1,
|
||||
X2,
|
||||
X3,
|
||||
X4,
|
||||
X5,
|
||||
X6,
|
||||
X7,
|
||||
X8,
|
||||
X9,
|
||||
X10,
|
||||
X11,
|
||||
X12,
|
||||
X13,
|
||||
X14,
|
||||
X15,
|
||||
X16,
|
||||
X17,
|
||||
X18,
|
||||
X19,
|
||||
X20,
|
||||
X21,
|
||||
X22,
|
||||
X23,
|
||||
X24,
|
||||
X25,
|
||||
X26,
|
||||
X27,
|
||||
X28,
|
||||
X29,
|
||||
X30,
|
||||
X31,
|
||||
PC,
|
||||
NUM_REGS,
|
||||
NEXT_PC=NUM_REGS,
|
||||
TRAP_STATE,
|
||||
PENDING_TRAP,
|
||||
MACHINE_STATE,
|
||||
LAST_BRANCH,
|
||||
ICOUNT,
|
||||
ZERO = X0,
|
||||
RA = X1,
|
||||
SP = X2,
|
||||
GP = X3,
|
||||
TP = X4,
|
||||
T0 = X5,
|
||||
T1 = X6,
|
||||
T2 = X7,
|
||||
S0 = X8,
|
||||
S1 = X9,
|
||||
A0 = X10,
|
||||
A1 = X11,
|
||||
A2 = X12,
|
||||
A3 = X13,
|
||||
A4 = X14,
|
||||
A5 = X15,
|
||||
A6 = X16,
|
||||
A7 = X17,
|
||||
S2 = X18,
|
||||
S3 = X19,
|
||||
S4 = X20,
|
||||
S5 = X21,
|
||||
S6 = X22,
|
||||
S7 = X23,
|
||||
S8 = X24,
|
||||
S9 = X25,
|
||||
S10 = X26,
|
||||
S11 = X27,
|
||||
T3 = X28,
|
||||
T4 = X29,
|
||||
T5 = X30,
|
||||
T6 = X31
|
||||
};
|
||||
|
||||
using reg_t = uint32_t;
|
||||
|
||||
using addr_t = uint32_t;
|
||||
|
||||
using code_word_t = uint32_t; //TODO: check removal
|
||||
|
||||
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
|
||||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||
|
||||
static constexpr std::array<const uint32_t, 39> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
|
||||
|
||||
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
|
||||
|
||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||
|
||||
enum sreg_flag_e { FLAGS };
|
||||
|
||||
enum mem_type_e { MEM, CSR, FENCE, RES };
|
||||
};
|
||||
|
||||
struct tgf_b: public arch_if {
|
||||
|
||||
using virt_addr_t = typename traits<tgf_b>::virt_addr_t;
|
||||
using phys_addr_t = typename traits<tgf_b>::phys_addr_t;
|
||||
using reg_t = typename traits<tgf_b>::reg_t;
|
||||
using addr_t = typename traits<tgf_b>::addr_t;
|
||||
|
||||
tgf_b();
|
||||
~tgf_b();
|
||||
|
||||
void reset(uint64_t address=0) override;
|
||||
|
||||
uint8_t* get_regs_base_ptr() override;
|
||||
/// deprecated
|
||||
void get_reg(short idx, std::vector<uint8_t>& value) override {}
|
||||
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
|
||||
/// deprecated
|
||||
bool get_flag(int flag) override {return false;}
|
||||
void set_flag(int, bool value) override {};
|
||||
/// deprecated
|
||||
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
|
||||
|
||||
inline uint64_t get_icount() { return reg.icount; }
|
||||
|
||||
inline bool should_stop() { return interrupt_sim; }
|
||||
|
||||
inline uint64_t stop_code() { return interrupt_sim; }
|
||||
|
||||
inline phys_addr_t v2p(const iss::addr_t& addr){
|
||||
if (addr.space != traits<tgf_b>::MEM || addr.type == iss::address_type::PHYSICAL ||
|
||||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
|
||||
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf_b>::addr_mask);
|
||||
} else
|
||||
return virt2phys(addr);
|
||||
}
|
||||
|
||||
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
|
||||
|
||||
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
|
||||
|
||||
inline uint32_t get_last_branch() { return reg.last_branch; }
|
||||
|
||||
protected:
|
||||
struct TGF_B_regs {
|
||||
uint32_t X0 = 0;
|
||||
uint32_t X1 = 0;
|
||||
uint32_t X2 = 0;
|
||||
uint32_t X3 = 0;
|
||||
uint32_t X4 = 0;
|
||||
uint32_t X5 = 0;
|
||||
uint32_t X6 = 0;
|
||||
uint32_t X7 = 0;
|
||||
uint32_t X8 = 0;
|
||||
uint32_t X9 = 0;
|
||||
uint32_t X10 = 0;
|
||||
uint32_t X11 = 0;
|
||||
uint32_t X12 = 0;
|
||||
uint32_t X13 = 0;
|
||||
uint32_t X14 = 0;
|
||||
uint32_t X15 = 0;
|
||||
uint32_t X16 = 0;
|
||||
uint32_t X17 = 0;
|
||||
uint32_t X18 = 0;
|
||||
uint32_t X19 = 0;
|
||||
uint32_t X20 = 0;
|
||||
uint32_t X21 = 0;
|
||||
uint32_t X22 = 0;
|
||||
uint32_t X23 = 0;
|
||||
uint32_t X24 = 0;
|
||||
uint32_t X25 = 0;
|
||||
uint32_t X26 = 0;
|
||||
uint32_t X27 = 0;
|
||||
uint32_t X28 = 0;
|
||||
uint32_t X29 = 0;
|
||||
uint32_t X30 = 0;
|
||||
uint32_t X31 = 0;
|
||||
uint32_t PC = 0;
|
||||
uint32_t NEXT_PC = 0;
|
||||
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
|
||||
uint64_t icount = 0;
|
||||
} reg;
|
||||
|
||||
std::array<address_type, 4> addr_mode;
|
||||
|
||||
uint64_t interrupt_sim=0;
|
||||
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
|
||||
};
|
||||
|
||||
}
|
||||
}
|
||||
#endif /* _TGF_B_H_ */
|
252
incl/iss/arch/tgf_c.h
Normal file
252
incl/iss/arch/tgf_c.h
Normal file
@ -0,0 +1,252 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifndef _TGF_C_H_
|
||||
#define _TGF_C_H_
|
||||
|
||||
#include <array>
|
||||
#include <iss/arch/traits.h>
|
||||
#include <iss/arch_if.h>
|
||||
#include <iss/vm_if.h>
|
||||
|
||||
namespace iss {
|
||||
namespace arch {
|
||||
|
||||
struct tgf_c;
|
||||
|
||||
template <> struct traits<tgf_c> {
|
||||
|
||||
constexpr static char const* const core_type = "TGF_C";
|
||||
|
||||
static constexpr std::array<const char*, 33> reg_names{
|
||||
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
|
||||
|
||||
static constexpr std::array<const char*, 33> reg_aliases{
|
||||
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
|
||||
|
||||
enum constants {XLEN=32, PCLEN=32, MUL_LEN=64, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff};
|
||||
|
||||
constexpr static unsigned FP_REGS_SIZE = 0;
|
||||
|
||||
enum reg_e {
|
||||
X0,
|
||||
X1,
|
||||
X2,
|
||||
X3,
|
||||
X4,
|
||||
X5,
|
||||
X6,
|
||||
X7,
|
||||
X8,
|
||||
X9,
|
||||
X10,
|
||||
X11,
|
||||
X12,
|
||||
X13,
|
||||
X14,
|
||||
X15,
|
||||
X16,
|
||||
X17,
|
||||
X18,
|
||||
X19,
|
||||
X20,
|
||||
X21,
|
||||
X22,
|
||||
X23,
|
||||
X24,
|
||||
X25,
|
||||
X26,
|
||||
X27,
|
||||
X28,
|
||||
X29,
|
||||
X30,
|
||||
X31,
|
||||
PC,
|
||||
NUM_REGS,
|
||||
NEXT_PC=NUM_REGS,
|
||||
TRAP_STATE,
|
||||
PENDING_TRAP,
|
||||
MACHINE_STATE,
|
||||
LAST_BRANCH,
|
||||
ICOUNT,
|
||||
ZERO = X0,
|
||||
RA = X1,
|
||||
SP = X2,
|
||||
GP = X3,
|
||||
TP = X4,
|
||||
T0 = X5,
|
||||
T1 = X6,
|
||||
T2 = X7,
|
||||
S0 = X8,
|
||||
S1 = X9,
|
||||
A0 = X10,
|
||||
A1 = X11,
|
||||
A2 = X12,
|
||||
A3 = X13,
|
||||
A4 = X14,
|
||||
A5 = X15,
|
||||
A6 = X16,
|
||||
A7 = X17,
|
||||
S2 = X18,
|
||||
S3 = X19,
|
||||
S4 = X20,
|
||||
S5 = X21,
|
||||
S6 = X22,
|
||||
S7 = X23,
|
||||
S8 = X24,
|
||||
S9 = X25,
|
||||
S10 = X26,
|
||||
S11 = X27,
|
||||
T3 = X28,
|
||||
T4 = X29,
|
||||
T5 = X30,
|
||||
T6 = X31
|
||||
};
|
||||
|
||||
using reg_t = uint32_t;
|
||||
|
||||
using addr_t = uint32_t;
|
||||
|
||||
using code_word_t = uint32_t; //TODO: check removal
|
||||
|
||||
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
|
||||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||
|
||||
static constexpr std::array<const uint32_t, 39> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
|
||||
|
||||
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
|
||||
|
||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||
|
||||
enum sreg_flag_e { FLAGS };
|
||||
|
||||
enum mem_type_e { MEM, CSR, FENCE, RES };
|
||||
};
|
||||
|
||||
struct tgf_c: public arch_if {
|
||||
|
||||
using virt_addr_t = typename traits<tgf_c>::virt_addr_t;
|
||||
using phys_addr_t = typename traits<tgf_c>::phys_addr_t;
|
||||
using reg_t = typename traits<tgf_c>::reg_t;
|
||||
using addr_t = typename traits<tgf_c>::addr_t;
|
||||
|
||||
tgf_c();
|
||||
~tgf_c();
|
||||
|
||||
void reset(uint64_t address=0) override;
|
||||
|
||||
uint8_t* get_regs_base_ptr() override;
|
||||
/// deprecated
|
||||
void get_reg(short idx, std::vector<uint8_t>& value) override {}
|
||||
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
|
||||
/// deprecated
|
||||
bool get_flag(int flag) override {return false;}
|
||||
void set_flag(int, bool value) override {};
|
||||
/// deprecated
|
||||
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
|
||||
|
||||
inline uint64_t get_icount() { return reg.icount; }
|
||||
|
||||
inline bool should_stop() { return interrupt_sim; }
|
||||
|
||||
inline uint64_t stop_code() { return interrupt_sim; }
|
||||
|
||||
inline phys_addr_t v2p(const iss::addr_t& addr){
|
||||
if (addr.space != traits<tgf_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
|
||||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
|
||||
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgf_c>::addr_mask);
|
||||
} else
|
||||
return virt2phys(addr);
|
||||
}
|
||||
|
||||
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
|
||||
|
||||
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
|
||||
|
||||
inline uint32_t get_last_branch() { return reg.last_branch; }
|
||||
|
||||
protected:
|
||||
struct TGF_C_regs {
|
||||
uint32_t X0 = 0;
|
||||
uint32_t X1 = 0;
|
||||
uint32_t X2 = 0;
|
||||
uint32_t X3 = 0;
|
||||
uint32_t X4 = 0;
|
||||
uint32_t X5 = 0;
|
||||
uint32_t X6 = 0;
|
||||
uint32_t X7 = 0;
|
||||
uint32_t X8 = 0;
|
||||
uint32_t X9 = 0;
|
||||
uint32_t X10 = 0;
|
||||
uint32_t X11 = 0;
|
||||
uint32_t X12 = 0;
|
||||
uint32_t X13 = 0;
|
||||
uint32_t X14 = 0;
|
||||
uint32_t X15 = 0;
|
||||
uint32_t X16 = 0;
|
||||
uint32_t X17 = 0;
|
||||
uint32_t X18 = 0;
|
||||
uint32_t X19 = 0;
|
||||
uint32_t X20 = 0;
|
||||
uint32_t X21 = 0;
|
||||
uint32_t X22 = 0;
|
||||
uint32_t X23 = 0;
|
||||
uint32_t X24 = 0;
|
||||
uint32_t X25 = 0;
|
||||
uint32_t X26 = 0;
|
||||
uint32_t X27 = 0;
|
||||
uint32_t X28 = 0;
|
||||
uint32_t X29 = 0;
|
||||
uint32_t X30 = 0;
|
||||
uint32_t X31 = 0;
|
||||
uint32_t PC = 0;
|
||||
uint32_t NEXT_PC = 0;
|
||||
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
|
||||
uint64_t icount = 0;
|
||||
} reg;
|
||||
|
||||
std::array<address_type, 4> addr_mode;
|
||||
|
||||
uint64_t interrupt_sim=0;
|
||||
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
|
||||
};
|
||||
|
||||
}
|
||||
}
|
||||
#endif /* _TGF_C_H_ */
|
@ -85,7 +85,7 @@ public:
|
||||
corresponding bytes in avail_buf are 0, otherwise
|
||||
avail buf is 1 */
|
||||
status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
|
||||
std::vector<uint8_t> &avail_buf) override;
|
||||
std::vector<uint8_t> &avail_buf) override;
|
||||
|
||||
/* Write one register. buf is 4-byte aligned and it is in target byte
|
||||
order */
|
||||
@ -104,7 +104,7 @@ public:
|
||||
status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
|
||||
|
||||
status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
|
||||
size_t &num, bool &done) override;
|
||||
size_t &num, bool &done) override;
|
||||
|
||||
status current_thread_query(rp_thread_ref &thread) override;
|
||||
|
||||
@ -120,12 +120,12 @@ public:
|
||||
|
||||
status packetsize_query(std::string &out_buf) override;
|
||||
|
||||
status add_break(break_type type, uint64_t addr, unsigned int length) override;
|
||||
status add_break(int type, uint64_t addr, unsigned int length) override;
|
||||
|
||||
status remove_break(break_type type, uint64_t addr, unsigned int length) override;
|
||||
status remove_break(int type, uint64_t addr, unsigned int length) override;
|
||||
|
||||
status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
|
||||
std::function<void(unsigned)> stop_callback) override;
|
||||
std::function<void(unsigned)> stop_callback) override;
|
||||
|
||||
status target_xml_query(std::string &out_buf) override;
|
||||
|
||||
@ -159,8 +159,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_t
|
||||
*/
|
||||
template <typename ARCH>
|
||||
status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
|
||||
std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
|
||||
bool &done) {
|
||||
std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
|
||||
bool &done) {
|
||||
if (first == 0) {
|
||||
result.clear();
|
||||
result.push_back(thread_idx);
|
||||
@ -183,8 +183,7 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
|
||||
data.clear();
|
||||
avail.clear();
|
||||
const uint8_t *reg_base = core->get_regs_base_ptr();
|
||||
auto start_reg=arch::traits<ARCH>::X0;
|
||||
for (size_t reg_no = start_reg; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
|
||||
for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
|
||||
auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
|
||||
unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
|
||||
for (size_t j = 0; j < reg_width; ++j) {
|
||||
@ -193,54 +192,40 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
|
||||
}
|
||||
}
|
||||
// work around fill with F type registers
|
||||
// if (arch::traits<ARCH>::NUM_REGS < 65) {
|
||||
// auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
|
||||
// for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
|
||||
// for (size_t j = 0; j < reg_width; ++j) {
|
||||
// data.push_back(0x0);
|
||||
// avail.push_back(0x00);
|
||||
// }
|
||||
// // if(arch::traits<ARCH>::XLEN < 64)
|
||||
// // for(unsigned j=0; j<4; ++j){
|
||||
// // data.push_back(0x0);
|
||||
// // avail.push_back(0x00);
|
||||
// // }
|
||||
// }
|
||||
// }
|
||||
// if (arch::traits<ARCH>::NUM_REGS < 65) {
|
||||
// auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
|
||||
// for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
|
||||
// for (size_t j = 0; j < reg_width; ++j) {
|
||||
// data.push_back(0x0);
|
||||
// avail.push_back(0x00);
|
||||
// }
|
||||
// // if(arch::traits<ARCH>::XLEN < 64)
|
||||
// // for(unsigned j=0; j<4; ++j){
|
||||
// // data.push_back(0x0);
|
||||
// // avail.push_back(0x00);
|
||||
// // }
|
||||
// }
|
||||
// }
|
||||
return Ok;
|
||||
}
|
||||
|
||||
template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(const std::vector<uint8_t> &data) {
|
||||
auto start_reg=arch::traits<ARCH>::X0;
|
||||
auto reg_count = arch::traits<ARCH>::NUM_REGS;
|
||||
auto *reg_base = core->get_regs_base_ptr();
|
||||
auto iter = data.data();
|
||||
bool e_ext = arch::traits<ARCH>::PC<32;
|
||||
for (size_t reg_no = 0; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
|
||||
if(e_ext && reg_no>15){
|
||||
if(reg_no==32){
|
||||
auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
|
||||
auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
|
||||
std::copy(iter, iter + reg_width, reg_base);
|
||||
} else {
|
||||
const uint64_t zero_val=0;
|
||||
auto reg_width = arch::traits<ARCH>::reg_bit_widths[15] / 8;
|
||||
auto iter = (uint8_t*)&zero_val;
|
||||
std::copy(iter, iter + reg_width, reg_base);
|
||||
}
|
||||
} else {
|
||||
auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
|
||||
auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
|
||||
std::copy(iter, iter + reg_width, reg_base);
|
||||
iter += 4;
|
||||
reg_base += offset;
|
||||
}
|
||||
for (size_t reg_no = 0; reg_no < reg_count; ++reg_no) {
|
||||
auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
|
||||
auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
|
||||
std::copy(iter, iter + reg_width, reg_base);
|
||||
iter += 4;
|
||||
reg_base += offset;
|
||||
}
|
||||
return Ok;
|
||||
}
|
||||
|
||||
template <typename ARCH>
|
||||
status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
|
||||
std::vector<uint8_t> &avail) {
|
||||
std::vector<uint8_t> &avail) {
|
||||
if (reg_no < 65) {
|
||||
// auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
|
||||
// arch::traits<ARCH>::reg_e>(reg_no))/8;
|
||||
@ -331,48 +316,34 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std
|
||||
return Ok;
|
||||
}
|
||||
|
||||
template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type type, uint64_t addr, unsigned int length) {
|
||||
switch(type) {
|
||||
default:
|
||||
return Err;
|
||||
case SW_EXEC:
|
||||
case HW_EXEC: {
|
||||
auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
|
||||
auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
|
||||
target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
|
||||
LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
|
||||
<< saddr.val << std::dec;
|
||||
template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
|
||||
auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
|
||||
auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
|
||||
target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
|
||||
LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
|
||||
<< saddr.val << std::dec;
|
||||
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
|
||||
return Ok;
|
||||
}
|
||||
|
||||
template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
|
||||
auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
|
||||
unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
|
||||
if (handle) {
|
||||
LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
|
||||
<< std::dec;
|
||||
// TODO: check length of addr range
|
||||
target_adapter_base::bp_lut.removeEntry(handle);
|
||||
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
|
||||
return Ok;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_type type, uint64_t addr, unsigned int length) {
|
||||
switch(type) {
|
||||
default:
|
||||
return Err;
|
||||
case SW_EXEC:
|
||||
case HW_EXEC: {
|
||||
auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
|
||||
unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
|
||||
if (handle) {
|
||||
LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
|
||||
<< std::dec;
|
||||
// TODO: check length of addr range
|
||||
target_adapter_base::bp_lut.removeEntry(handle);
|
||||
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
|
||||
return Ok;
|
||||
}
|
||||
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
|
||||
return Err;
|
||||
}
|
||||
}
|
||||
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
|
||||
return Err;
|
||||
}
|
||||
|
||||
template <typename ARCH>
|
||||
status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
|
||||
std::function<void(unsigned)> stop_callback) {
|
||||
std::function<void(unsigned)> stop_callback) {
|
||||
auto *reg_base = core->get_regs_base_ptr();
|
||||
auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
|
||||
auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
|
||||
@ -383,42 +354,42 @@ status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t
|
||||
|
||||
template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string &out_buf) {
|
||||
const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
|
||||
"<target><architecture>riscv:rv32</architecture>"
|
||||
//" <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
|
||||
//" <reg name=\"x0\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x1\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x2\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x3\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x4\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x5\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x6\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x7\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x8\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x9\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" </feature>\n"
|
||||
"</target>"};
|
||||
"<target><architecture>riscv:rv32</architecture>"
|
||||
//" <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
|
||||
//" <reg name=\"x0\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x1\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x2\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x3\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x4\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x5\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x6\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x7\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x8\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x9\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
|
||||
//" </feature>\n"
|
||||
"</target>"};
|
||||
out_buf = res;
|
||||
return Ok;
|
||||
}
|
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2023, MINRES Technologies GmbH
|
||||
* Copyright (C) 2017, 2018, MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -37,25 +37,23 @@
|
||||
|
||||
#include "iss/instrumentation_if.h"
|
||||
#include "iss/vm_plugin.h"
|
||||
#include <json/json.h>
|
||||
#include <string>
|
||||
#include <unordered_map>
|
||||
#include <vector>
|
||||
|
||||
namespace iss {
|
||||
|
||||
namespace plugin {
|
||||
|
||||
class cycle_estimate: public vm_plugin {
|
||||
class cycle_estimate: public iss::vm_plugin {
|
||||
BEGIN_BF_DECL(instr_desc, uint32_t)
|
||||
BF_FIELD(taken, 24, 8)
|
||||
BF_FIELD(not_taken, 16, 8)
|
||||
BF_FIELD(is_branch, 8, 8)
|
||||
BF_FIELD(size, 0, 8)
|
||||
instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
|
||||
BF_FIELD(size, 0, 16)
|
||||
instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken): instr_desc() {
|
||||
this->size=size;
|
||||
this->taken=taken;
|
||||
this->not_taken=not_taken;
|
||||
this->is_branch=branch;
|
||||
}
|
||||
END_BF_DECL();
|
||||
|
||||
@ -66,7 +64,7 @@ public:
|
||||
|
||||
cycle_estimate(const cycle_estimate &&) = delete;
|
||||
|
||||
cycle_estimate(std::string const& config_file_name);
|
||||
cycle_estimate(std::string config_file_name);
|
||||
|
||||
virtual ~cycle_estimate();
|
||||
|
||||
@ -81,7 +79,7 @@ public:
|
||||
void callback(instr_info_t instr_info) override;
|
||||
|
||||
private:
|
||||
iss::instrumentation_if *instr_if;
|
||||
iss::instrumentation_if *arch_instr;
|
||||
std::vector<instr_desc> delays;
|
||||
struct pair_hash {
|
||||
size_t operator()(const std::pair<uint64_t, uint64_t> &p) const {
|
||||
@ -90,7 +88,7 @@ private:
|
||||
}
|
||||
};
|
||||
std::unordered_map<std::pair<uint64_t, uint64_t>, uint64_t, pair_hash> blocks;
|
||||
std::string config_file_name;
|
||||
Json::Value root;
|
||||
};
|
||||
}
|
||||
}
|
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2023, MINRES Technologies GmbH
|
||||
* Copyright (C) 2017, 2018, MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -69,7 +69,7 @@ public:
|
||||
|
||||
sync_type get_sync() override { return POST_SYNC; };
|
||||
|
||||
void callback(instr_info_t) override;
|
||||
void callback(instr_info_t instr_info) override;
|
||||
|
||||
private:
|
||||
Json::Value root;
|
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017-2021 MINRES Technologies GmbH
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -30,29 +30,34 @@
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _SYSC_CORE_COMPLEX_H_
|
||||
#define _SYSC_CORE_COMPLEX_H_
|
||||
#ifndef _SYSC_SIFIVE_FE310_H_
|
||||
#define _SYSC_SIFIVE_FE310_H_
|
||||
|
||||
#include <tlm/scc/initiator_mixin.h>
|
||||
#include <scc/traceable.h>
|
||||
#include <scc/tick2time.h>
|
||||
#include <scc/utilities.h>
|
||||
#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
|
||||
#ifdef CWR_SYSTEMC
|
||||
#include <scmlinc/scml_property.h>
|
||||
#define SOCKET_WIDTH 32
|
||||
#else
|
||||
#include "tlm/scc/initiator_mixin.h"
|
||||
#include "scc/traceable.h"
|
||||
#include "scc/utilities.h"
|
||||
#include <cci_configuration>
|
||||
#define SOCKET_WIDTH scc::LT
|
||||
#endif
|
||||
#include <tlm>
|
||||
#include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
|
||||
#include <tlm_utils/tlm_quantumkeeper.h>
|
||||
#include <util/range_lut.h>
|
||||
#include <memory>
|
||||
|
||||
class scv_tr_db;
|
||||
class scv_tr_stream;
|
||||
struct _scv_tr_generator_default_data;
|
||||
template <class T_begin, class T_end> class scv_tr_generator;
|
||||
|
||||
namespace iss {
|
||||
class vm_plugin;
|
||||
class vm_if;
|
||||
namespace arch {
|
||||
template <typename BASE> class riscv_hart_m_p;
|
||||
}
|
||||
namespace debugger {
|
||||
class target_adapter_if;
|
||||
}
|
||||
} // namespace iss
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class tlm_dmi_ext : public tlm::tlm_dmi {
|
||||
@ -65,19 +70,18 @@ public:
|
||||
bool operator!=(const tlm_dmi_ext &o) const { return !operator==(o); }
|
||||
};
|
||||
|
||||
namespace tgfs {
|
||||
namespace SiFive {
|
||||
class core_wrapper;
|
||||
struct core_trace;
|
||||
|
||||
class core_complex : public sc_core::sc_module, public scc::traceable {
|
||||
public:
|
||||
tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> ibus{"ibus"};
|
||||
tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
|
||||
|
||||
tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> dbus{"dbus"};
|
||||
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
|
||||
|
||||
sc_core::sc_in<bool> rst_i{"rst_i"};
|
||||
|
||||
sc_core::sc_in<bool> ext_irq_i{"ext_irq_i"};
|
||||
sc_core::sc_in<bool> global_irq_i{"global_irq_i"};
|
||||
|
||||
sc_core::sc_in<bool> timer_irq_i{"timer_irq_i"};
|
||||
|
||||
@ -85,10 +89,7 @@ public:
|
||||
|
||||
sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i{"local_irq_i", 16};
|
||||
|
||||
#ifndef CWR_SYSTEMC
|
||||
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
|
||||
|
||||
sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o{"mtime_o"};
|
||||
sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
|
||||
|
||||
cci::cci_param<std::string> elf_file{"elf_file", ""};
|
||||
|
||||
@ -96,9 +97,7 @@ public:
|
||||
|
||||
cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
|
||||
|
||||
cci::cci_param<std::string> core_type{"core_type", "tgc_c"};
|
||||
|
||||
cci::cci_param<std::string> backend{"backend", "interp"};
|
||||
cci::cci_param<std::string> backend{"backend", "tcc"};
|
||||
|
||||
cci::cci_param<unsigned short> gdb_server_port{"gdb_server_port", 0};
|
||||
|
||||
@ -106,67 +105,18 @@ public:
|
||||
|
||||
cci::cci_param<uint32_t> mhartid{"mhartid", 0};
|
||||
|
||||
cci::cci_param<std::string> plugins{"plugins", ""};
|
||||
|
||||
core_complex(sc_core::sc_module_name const& name);
|
||||
|
||||
#else
|
||||
sc_core::sc_in<bool> clk_i{"clk_i"};
|
||||
|
||||
sc_core::sc_in<uint64_t> mtime_i{"mtime_i"};
|
||||
|
||||
scml_property<std::string> elf_file{"elf_file", ""};
|
||||
|
||||
scml_property<bool> enable_disass{"enable_disass", false};
|
||||
|
||||
scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
|
||||
|
||||
scml_property<std::string> core_type{"core_type", "tgc_c"};
|
||||
|
||||
scml_property<std::string> backend{"backend", "interp"};
|
||||
|
||||
scml_property<unsigned> gdb_server_port{"gdb_server_port", 0};
|
||||
|
||||
scml_property<bool> dump_ir{"dump_ir", false};
|
||||
|
||||
scml_property<uint32_t> mhartid{"mhartid", 0};
|
||||
|
||||
scml_property<std::string> plugins{"plugins", ""};
|
||||
|
||||
core_complex(sc_core::sc_module_name const& name)
|
||||
: sc_module(name)
|
||||
, local_irq_i{"local_irq_i", 16}
|
||||
, elf_file{"elf_file", ""}
|
||||
, enable_disass{"enable_disass", false}
|
||||
, reset_address{"reset_address", 0ULL}
|
||||
, core_type{"core_type", "tgc_c"}
|
||||
, backend{"backend", "interp"}
|
||||
, gdb_server_port{"gdb_server_port", 0}
|
||||
, dump_ir{"dump_ir", false}
|
||||
, mhartid{"mhartid", 0}
|
||||
, plugins{"plugins", ""}
|
||||
, fetch_lut(tlm_dmi_ext())
|
||||
, read_lut(tlm_dmi_ext())
|
||||
, write_lut(tlm_dmi_ext())
|
||||
{
|
||||
init();
|
||||
}
|
||||
|
||||
#endif
|
||||
core_complex(sc_core::sc_module_name name);
|
||||
|
||||
~core_complex();
|
||||
|
||||
inline void sync(uint64_t cycle) {
|
||||
auto core_inc = curr_clk * (cycle - last_sync_cycle);
|
||||
auto incr = std::max(core_inc, std::max(ibus_inc, dbus_inc));
|
||||
quantum_keeper.inc(incr);
|
||||
auto time = curr_clk * (cycle - last_sync_cycle);
|
||||
quantum_keeper.inc(time);
|
||||
if (quantum_keeper.need_sync()) {
|
||||
wait(quantum_keeper.get_local_time());
|
||||
quantum_keeper.reset();
|
||||
}
|
||||
last_sync_cycle = cycle;
|
||||
ibus_inc = sc_core::SC_ZERO_TIME;
|
||||
dbus_inc = sc_core::SC_ZERO_TIME;
|
||||
}
|
||||
|
||||
bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
|
||||
@ -179,34 +129,38 @@ public:
|
||||
|
||||
void trace(sc_core::sc_trace_file *trf) const override;
|
||||
|
||||
bool disass_output(uint64_t pc, const std::string instr);
|
||||
void disass_output(uint64_t pc, const std::string instr);
|
||||
|
||||
void set_clock_period(sc_core::sc_time period);
|
||||
protected:
|
||||
void before_end_of_elaboration() override;
|
||||
void start_of_simulation() override;
|
||||
void forward();
|
||||
void run();
|
||||
void clk_cb();
|
||||
void rst_cb();
|
||||
void sw_irq_cb();
|
||||
void timer_irq_cb();
|
||||
void ext_irq_cb();
|
||||
void local_irq_cb();
|
||||
void global_irq_cb();
|
||||
uint64_t last_sync_cycle = 0;
|
||||
util::range_lut<tlm_dmi_ext> fetch_lut, read_lut, write_lut;
|
||||
util::range_lut<tlm_dmi_ext> read_lut, write_lut;
|
||||
tlm_utils::tlm_quantumkeeper quantum_keeper;
|
||||
std::vector<uint8_t> write_buf;
|
||||
core_wrapper* cpu{nullptr};
|
||||
sc_core::sc_signal<sc_core::sc_time> curr_clk;
|
||||
sc_core::sc_time ibus_inc, dbus_inc;
|
||||
core_trace* trc{nullptr};
|
||||
std::unique_ptr<scc::tick2time> t2t;
|
||||
private:
|
||||
void init();
|
||||
std::vector<iss::vm_plugin *> plugin_list;
|
||||
|
||||
std::unique_ptr<core_wrapper> cpu;
|
||||
std::unique_ptr<iss::vm_if> vm;
|
||||
sc_core::sc_time curr_clk;
|
||||
iss::debugger::target_adapter_if *tgt_adapter;
|
||||
#ifdef WITH_SCV
|
||||
//! transaction recording database
|
||||
scv_tr_db *m_db;
|
||||
//! blocking transaction recording stream handle
|
||||
scv_tr_stream *stream_handle;
|
||||
//! transaction generator handle for blocking transactions
|
||||
scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data> *instr_tr_handle;
|
||||
scv_tr_generator<uint64_t, _scv_tr_generator_default_data> *fetch_tr_handle;
|
||||
scv_tr_handle tr_handle;
|
||||
#endif
|
||||
};
|
||||
} /* namespace tgfs */
|
||||
|
||||
} /* namespace SiFive */
|
||||
} /* namespace sysc */
|
||||
|
||||
#endif /* _SYSC_CORE_COMPLEX_H_ */
|
||||
#endif /* _SYSC_SIFIVE_FE310_H_ */
|
@ -8,7 +8,7 @@ project("sotfloat" VERSION 3.0.0)
|
||||
# Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0)
|
||||
set(VERSION "3e")
|
||||
|
||||
#include(Common)
|
||||
include(Common)
|
||||
include(GNUInstallDirs)
|
||||
|
||||
set(SPECIALIZATION RISCV)
|
||||
|
@ -49,9 +49,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
*----------------------------------------------------------------------------*/
|
||||
#ifdef __GNUC__
|
||||
#define SOFTFLOAT_BUILTIN_CLZ 1
|
||||
#define SOFTFLOAT_INTRINSIC_INT128 1
|
||||
#endif
|
||||
#include "opts-GCC.h"
|
||||
|
||||
|
2
src-gen/.gitignore
vendored
2
src-gen/.gitignore
vendored
@ -1,2 +0,0 @@
|
||||
/iss
|
||||
/vm
|
1
src/iss/.gitignore
vendored
1
src/iss/.gitignore
vendored
@ -1 +0,0 @@
|
||||
/tgc_*.cpp
|
@ -1,100 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2022 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contributors:
|
||||
* eyck@minres.com - initial implementation
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _RISCV_HART_M_P_HWL_H
|
||||
#define _RISCV_HART_M_P_HWL_H
|
||||
|
||||
#include <iss/vm_types.h>
|
||||
|
||||
namespace iss {
|
||||
namespace arch {
|
||||
|
||||
template <typename BASE> class hwl : public BASE {
|
||||
public:
|
||||
using base_class = BASE;
|
||||
using this_class = hwl<BASE>;
|
||||
using reg_t = typename BASE::reg_t;
|
||||
|
||||
hwl();
|
||||
virtual ~hwl() = default;
|
||||
|
||||
protected:
|
||||
iss::status read_custom_csr_reg(unsigned addr, reg_t &val) override;
|
||||
iss::status write_custom_csr_reg(unsigned addr, reg_t val) override;
|
||||
};
|
||||
|
||||
|
||||
template<typename BASE>
|
||||
inline hwl<BASE>::hwl() {
|
||||
for (unsigned addr = 0x800; addr < 0x803; ++addr){
|
||||
this->register_custom_csr_rd(addr);
|
||||
this->register_custom_csr_wr(addr);
|
||||
}
|
||||
for (unsigned addr = 0x804; addr < 0x807; ++addr){
|
||||
this->register_custom_csr_rd(addr);
|
||||
this->register_custom_csr_wr(addr);
|
||||
}
|
||||
}
|
||||
|
||||
template<typename BASE>
|
||||
inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t &val) {
|
||||
switch(addr){
|
||||
case 0x800: val = this->reg.lpstart0; break;
|
||||
case 0x801: val = this->reg.lpend0; break;
|
||||
case 0x802: val = this->reg.lpcount0; break;
|
||||
case 0x804: val = this->reg.lpstart1; break;
|
||||
case 0x805: val = this->reg.lpend1; break;
|
||||
case 0x806: val = this->reg.lpcount1; break;
|
||||
}
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
template<typename BASE>
|
||||
inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
|
||||
switch(addr){
|
||||
case 0x800: this->reg.lpstart0 = val; break;
|
||||
case 0x801: this->reg.lpend0 = val; break;
|
||||
case 0x802: this->reg.lpcount0 = val; break;
|
||||
case 0x804: this->reg.lpstart1 = val; break;
|
||||
case 0x805: this->reg.lpend1 = val; break;
|
||||
case 0x806: this->reg.lpcount1 = val; break;
|
||||
}
|
||||
return iss::Ok;
|
||||
}
|
||||
|
||||
} // namespace arch
|
||||
} // namespace iss
|
||||
|
||||
|
||||
#endif /* _RISCV_HART_M_P_H */
|
@ -1,302 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, 2018, 2021 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contributors:
|
||||
* eyck@minres.com - initial implementation
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _RISCV_HART_COMMON
|
||||
#define _RISCV_HART_COMMON
|
||||
|
||||
#include "iss/arch_if.h"
|
||||
#include <cstdint>
|
||||
|
||||
namespace iss {
|
||||
namespace arch {
|
||||
|
||||
enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
|
||||
|
||||
enum features_e{FEAT_NONE, FEAT_PMP=1, FEAT_EXT_N=2, FEAT_CLIC=4, FEAT_DEBUG=8, FEAT_TCM=16};
|
||||
|
||||
enum riscv_csr {
|
||||
/* user-level CSR */
|
||||
// User Trap Setup
|
||||
ustatus = 0x000,
|
||||
uie = 0x004,
|
||||
utvec = 0x005,
|
||||
utvt = 0x007, //CLIC
|
||||
// User Trap Handling
|
||||
uscratch = 0x040,
|
||||
uepc = 0x041,
|
||||
ucause = 0x042,
|
||||
utval = 0x043,
|
||||
uip = 0x044,
|
||||
uxnti = 0x045, //CLIC
|
||||
uintstatus = 0xCB1, // MRW Current interrupt levels (CLIC) - addr subject to change
|
||||
uintthresh = 0x047, // MRW Interrupt-level threshold (CLIC) - addr subject to change
|
||||
uscratchcsw = 0x048, // MRW Conditional scratch swap on priv mode change (CLIC)
|
||||
uscratchcswl = 0x049, // MRW Conditional scratch swap on level change (CLIC)
|
||||
// User Floating-Point CSRs
|
||||
fflags = 0x001,
|
||||
frm = 0x002,
|
||||
fcsr = 0x003,
|
||||
// User Counter/Timers
|
||||
cycle = 0xC00,
|
||||
time = 0xC01,
|
||||
instret = 0xC02,
|
||||
hpmcounter3 = 0xC03,
|
||||
hpmcounter4 = 0xC04,
|
||||
/*...*/
|
||||
hpmcounter31 = 0xC1F,
|
||||
cycleh = 0xC80,
|
||||
timeh = 0xC81,
|
||||
instreth = 0xC82,
|
||||
hpmcounter3h = 0xC83,
|
||||
hpmcounter4h = 0xC84,
|
||||
/*...*/
|
||||
hpmcounter31h = 0xC9F,
|
||||
/* supervisor-level CSR */
|
||||
// Supervisor Trap Setup
|
||||
sstatus = 0x100,
|
||||
sedeleg = 0x102,
|
||||
sideleg = 0x103,
|
||||
sie = 0x104,
|
||||
stvec = 0x105,
|
||||
scounteren = 0x106,
|
||||
// Supervisor Trap Handling
|
||||
sscratch = 0x140,
|
||||
sepc = 0x141,
|
||||
scause = 0x142,
|
||||
stval = 0x143,
|
||||
sip = 0x144,
|
||||
// Supervisor Protection and Translation
|
||||
satp = 0x180,
|
||||
/* machine-level CSR */
|
||||
// Machine Information Registers
|
||||
mvendorid = 0xF11,
|
||||
marchid = 0xF12,
|
||||
mimpid = 0xF13,
|
||||
mhartid = 0xF14,
|
||||
// Machine Trap Setup
|
||||
mstatus = 0x300,
|
||||
misa = 0x301,
|
||||
medeleg = 0x302,
|
||||
mideleg = 0x303,
|
||||
mie = 0x304,
|
||||
mtvec = 0x305,
|
||||
mcounteren = 0x306,
|
||||
mtvt = 0x307, //CLIC
|
||||
// Machine Trap Handling
|
||||
mscratch = 0x340,
|
||||
mepc = 0x341,
|
||||
mcause = 0x342,
|
||||
mtval = 0x343,
|
||||
mip = 0x344,
|
||||
mxnti = 0x345, //CLIC
|
||||
mintstatus = 0xFB1, // MRW Current interrupt levels (CLIC) - addr subject to change
|
||||
mintthresh = 0x347, // MRW Interrupt-level threshold (CLIC) - addr subject to change
|
||||
mscratchcsw = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
|
||||
mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
|
||||
// Physical Memory Protection
|
||||
pmpcfg0 = 0x3A0,
|
||||
pmpcfg1 = 0x3A1,
|
||||
pmpcfg2 = 0x3A2,
|
||||
pmpcfg3 = 0x3A3,
|
||||
pmpaddr0 = 0x3B0,
|
||||
pmpaddr1 = 0x3B1,
|
||||
pmpaddr2 = 0x3B2,
|
||||
pmpaddr3 = 0x3B3,
|
||||
pmpaddr4 = 0x3B4,
|
||||
pmpaddr5 = 0x3B5,
|
||||
pmpaddr6 = 0x3B6,
|
||||
pmpaddr7 = 0x3B7,
|
||||
pmpaddr8 = 0x3B8,
|
||||
pmpaddr9 = 0x3B9,
|
||||
pmpaddr10 = 0x3BA,
|
||||
pmpaddr11 = 0x3BB,
|
||||
pmpaddr12 = 0x3BC,
|
||||
pmpaddr13 = 0x3BD,
|
||||
pmpaddr14 = 0x3BE,
|
||||
pmpaddr15 = 0x3BF,
|
||||
// Machine Counter/Timers
|
||||
mcycle = 0xB00,
|
||||
minstret = 0xB02,
|
||||
mhpmcounter3 = 0xB03,
|
||||
mhpmcounter4 = 0xB04,
|
||||
/*...*/
|
||||
mhpmcounter31 = 0xB1F,
|
||||
mcycleh = 0xB80,
|
||||
minstreth = 0xB82,
|
||||
mhpmcounter3h = 0xB83,
|
||||
mhpmcounter4h = 0xB84,
|
||||
/*...*/
|
||||
mhpmcounter31h = 0xB9F,
|
||||
// Machine Counter Setup
|
||||
mhpmevent3 = 0x323,
|
||||
mhpmevent4 = 0x324,
|
||||
/*...*/
|
||||
mhpmevent31 = 0x33F,
|
||||
// Debug/Trace Registers (shared with Debug Mode)
|
||||
tselect = 0x7A0,
|
||||
tdata1 = 0x7A1,
|
||||
tdata2 = 0x7A2,
|
||||
tdata3 = 0x7A3,
|
||||
// Debug Mode Registers
|
||||
dcsr = 0x7B0,
|
||||
dpc = 0x7B1,
|
||||
dscratch0 = 0x7B2,
|
||||
dscratch1 = 0x7B3
|
||||
};
|
||||
|
||||
|
||||
enum {
|
||||
PGSHIFT = 12,
|
||||
PTE_PPN_SHIFT = 10,
|
||||
// page table entry (PTE) fields
|
||||
PTE_V = 0x001, // Valid
|
||||
PTE_R = 0x002, // Read
|
||||
PTE_W = 0x004, // Write
|
||||
PTE_X = 0x008, // Execute
|
||||
PTE_U = 0x010, // User
|
||||
PTE_G = 0x020, // Global
|
||||
PTE_A = 0x040, // Accessed
|
||||
PTE_D = 0x080, // Dirty
|
||||
PTE_SOFT = 0x300 // Reserved for Software
|
||||
};
|
||||
|
||||
template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
|
||||
|
||||
enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3, PRIV_D = 4};
|
||||
|
||||
enum {
|
||||
ISA_A = 1,
|
||||
ISA_B = 1 << 1,
|
||||
ISA_C = 1 << 2,
|
||||
ISA_D = 1 << 3,
|
||||
ISA_E = 1 << 4,
|
||||
ISA_F = 1 << 5,
|
||||
ISA_G = 1 << 6,
|
||||
ISA_I = 1 << 8,
|
||||
ISA_M = 1 << 12,
|
||||
ISA_N = 1 << 13,
|
||||
ISA_Q = 1 << 16,
|
||||
ISA_S = 1 << 18,
|
||||
ISA_U = 1 << 20
|
||||
};
|
||||
|
||||
struct vm_info {
|
||||
int levels;
|
||||
int idxbits;
|
||||
int ptesize;
|
||||
uint64_t ptbase;
|
||||
bool is_active() { return levels; }
|
||||
};
|
||||
|
||||
struct feature_config {
|
||||
uint64_t clic_base{0xc0000000};
|
||||
unsigned clic_int_ctl_bits{4};
|
||||
unsigned clic_num_irq{16};
|
||||
unsigned clic_num_trigger{0};
|
||||
uint64_t tcm_base{0x10000000};
|
||||
uint64_t tcm_size{0x8000};
|
||||
};
|
||||
|
||||
class trap_load_access_fault : public trap_access {
|
||||
public:
|
||||
trap_load_access_fault(uint64_t badaddr)
|
||||
: trap_access(5 << 16, badaddr) {}
|
||||
};
|
||||
class illegal_instruction_fault : public trap_access {
|
||||
public:
|
||||
illegal_instruction_fault(uint64_t badaddr)
|
||||
: trap_access(2 << 16, badaddr) {}
|
||||
};
|
||||
class trap_instruction_page_fault : public trap_access {
|
||||
public:
|
||||
trap_instruction_page_fault(uint64_t badaddr)
|
||||
: trap_access(12 << 16, badaddr) {}
|
||||
};
|
||||
class trap_load_page_fault : public trap_access {
|
||||
public:
|
||||
trap_load_page_fault(uint64_t badaddr)
|
||||
: trap_access(13 << 16, badaddr) {}
|
||||
};
|
||||
class trap_store_page_fault : public trap_access {
|
||||
public:
|
||||
trap_store_page_fault(uint64_t badaddr)
|
||||
: trap_access(15 << 16, badaddr) {}
|
||||
};
|
||||
|
||||
inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t *const data, unsigned length) {
|
||||
auto reg_ptr = reinterpret_cast<uint8_t*>(®);
|
||||
switch (offs & 0x3) {
|
||||
case 0:
|
||||
for (auto i = 0U; i < length; ++i)
|
||||
*(data + i) = *(reg_ptr + i);
|
||||
break;
|
||||
case 1:
|
||||
for (auto i = 0U; i < length; ++i)
|
||||
*(data + i) = *(reg_ptr + 1 + i);
|
||||
break;
|
||||
case 2:
|
||||
for (auto i = 0U; i < length; ++i)
|
||||
*(data + i) = *(reg_ptr + 2 + i);
|
||||
break;
|
||||
case 3:
|
||||
*data = *(reg_ptr + 3);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t *const data, unsigned length) {
|
||||
auto reg_ptr = reinterpret_cast<uint8_t*>(®);
|
||||
switch (offs & 0x3) {
|
||||
case 0:
|
||||
for (auto i = 0U; i < length; ++i)
|
||||
*(reg_ptr + i) = *(data + i);
|
||||
break;
|
||||
case 1:
|
||||
for (auto i = 0U; i < length; ++i)
|
||||
*(reg_ptr + 1 + i) = *(data + i);
|
||||
break;
|
||||
case 2:
|
||||
for (auto i = 0U; i < length; ++i)
|
||||
*(reg_ptr + 2 + i) = *(data + i);
|
||||
break;
|
||||
case 3:
|
||||
*(reg_ptr + 3) = *data ;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,270 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _TGC_C_H_
|
||||
#define _TGC_C_H_
|
||||
|
||||
#include <array>
|
||||
#include <iss/arch/traits.h>
|
||||
#include <iss/arch_if.h>
|
||||
#include <iss/vm_if.h>
|
||||
|
||||
namespace iss {
|
||||
namespace arch {
|
||||
|
||||
struct tgc_c;
|
||||
|
||||
template <> struct traits<tgc_c> {
|
||||
|
||||
constexpr static char const* const core_type = "TGC_C";
|
||||
|
||||
static constexpr std::array<const char*, 36> reg_names{
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
|
||||
|
||||
static constexpr std::array<const char*, 36> reg_aliases{
|
||||
{"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
|
||||
|
||||
enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};
|
||||
|
||||
constexpr static unsigned FP_REGS_SIZE = 0;
|
||||
|
||||
enum reg_e {
|
||||
X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
|
||||
};
|
||||
|
||||
using reg_t = uint32_t;
|
||||
|
||||
using addr_t = uint32_t;
|
||||
|
||||
using code_word_t = uint32_t; //TODO: check removal
|
||||
|
||||
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
|
||||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||
|
||||
static constexpr std::array<const uint32_t, 43> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};
|
||||
|
||||
static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}};
|
||||
|
||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||
|
||||
enum sreg_flag_e { FLAGS };
|
||||
|
||||
enum mem_type_e { MEM, FENCE, RES, CSR };
|
||||
|
||||
enum class opcode_e : unsigned short {
|
||||
LUI = 0,
|
||||
AUIPC = 1,
|
||||
JAL = 2,
|
||||
JALR = 3,
|
||||
BEQ = 4,
|
||||
BNE = 5,
|
||||
BLT = 6,
|
||||
BGE = 7,
|
||||
BLTU = 8,
|
||||
BGEU = 9,
|
||||
LB = 10,
|
||||
LH = 11,
|
||||
LW = 12,
|
||||
LBU = 13,
|
||||
LHU = 14,
|
||||
SB = 15,
|
||||
SH = 16,
|
||||
SW = 17,
|
||||
ADDI = 18,
|
||||
SLTI = 19,
|
||||
SLTIU = 20,
|
||||
XORI = 21,
|
||||
ORI = 22,
|
||||
ANDI = 23,
|
||||
SLLI = 24,
|
||||
SRLI = 25,
|
||||
SRAI = 26,
|
||||
ADD = 27,
|
||||
SUB = 28,
|
||||
SLL = 29,
|
||||
SLT = 30,
|
||||
SLTU = 31,
|
||||
XOR = 32,
|
||||
SRL = 33,
|
||||
SRA = 34,
|
||||
OR = 35,
|
||||
AND = 36,
|
||||
FENCE = 37,
|
||||
ECALL = 38,
|
||||
EBREAK = 39,
|
||||
MRET = 40,
|
||||
WFI = 41,
|
||||
CSRRW = 42,
|
||||
CSRRS = 43,
|
||||
CSRRC = 44,
|
||||
CSRRWI = 45,
|
||||
CSRRSI = 46,
|
||||
CSRRCI = 47,
|
||||
FENCE_I = 48,
|
||||
MUL = 49,
|
||||
MULH = 50,
|
||||
MULHSU = 51,
|
||||
MULHU = 52,
|
||||
DIV = 53,
|
||||
DIVU = 54,
|
||||
REM = 55,
|
||||
REMU = 56,
|
||||
CADDI4SPN = 57,
|
||||
CLW = 58,
|
||||
CSW = 59,
|
||||
CADDI = 60,
|
||||
CNOP = 61,
|
||||
CJAL = 62,
|
||||
CLI = 63,
|
||||
CLUI = 64,
|
||||
CADDI16SP = 65,
|
||||
__reserved_clui = 66,
|
||||
CSRLI = 67,
|
||||
CSRAI = 68,
|
||||
CANDI = 69,
|
||||
CSUB = 70,
|
||||
CXOR = 71,
|
||||
COR = 72,
|
||||
CAND = 73,
|
||||
CJ = 74,
|
||||
CBEQZ = 75,
|
||||
CBNEZ = 76,
|
||||
CSLLI = 77,
|
||||
CLWSP = 78,
|
||||
CMV = 79,
|
||||
CJR = 80,
|
||||
__reserved_cmv = 81,
|
||||
CADD = 82,
|
||||
CJALR = 83,
|
||||
CEBREAK = 84,
|
||||
CSWSP = 85,
|
||||
DII = 86,
|
||||
MAX_OPCODE
|
||||
};
|
||||
};
|
||||
|
||||
struct tgc_c: public arch_if {
|
||||
|
||||
using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
|
||||
using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
|
||||
using reg_t = typename traits<tgc_c>::reg_t;
|
||||
using addr_t = typename traits<tgc_c>::addr_t;
|
||||
|
||||
tgc_c();
|
||||
~tgc_c();
|
||||
|
||||
void reset(uint64_t address=0) override;
|
||||
|
||||
uint8_t* get_regs_base_ptr() override;
|
||||
|
||||
inline uint64_t get_icount() { return reg.icount; }
|
||||
|
||||
inline bool should_stop() { return interrupt_sim; }
|
||||
|
||||
inline uint64_t stop_code() { return interrupt_sim; }
|
||||
|
||||
inline phys_addr_t v2p(const iss::addr_t& addr){
|
||||
if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
|
||||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
|
||||
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
|
||||
} else
|
||||
return virt2phys(addr);
|
||||
}
|
||||
|
||||
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
|
||||
|
||||
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
|
||||
|
||||
inline uint32_t get_last_branch() { return reg.last_branch; }
|
||||
|
||||
|
||||
#pragma pack(push, 1)
|
||||
struct TGC_C_regs {
|
||||
uint32_t X0 = 0;
|
||||
uint32_t X1 = 0;
|
||||
uint32_t X2 = 0;
|
||||
uint32_t X3 = 0;
|
||||
uint32_t X4 = 0;
|
||||
uint32_t X5 = 0;
|
||||
uint32_t X6 = 0;
|
||||
uint32_t X7 = 0;
|
||||
uint32_t X8 = 0;
|
||||
uint32_t X9 = 0;
|
||||
uint32_t X10 = 0;
|
||||
uint32_t X11 = 0;
|
||||
uint32_t X12 = 0;
|
||||
uint32_t X13 = 0;
|
||||
uint32_t X14 = 0;
|
||||
uint32_t X15 = 0;
|
||||
uint32_t X16 = 0;
|
||||
uint32_t X17 = 0;
|
||||
uint32_t X18 = 0;
|
||||
uint32_t X19 = 0;
|
||||
uint32_t X20 = 0;
|
||||
uint32_t X21 = 0;
|
||||
uint32_t X22 = 0;
|
||||
uint32_t X23 = 0;
|
||||
uint32_t X24 = 0;
|
||||
uint32_t X25 = 0;
|
||||
uint32_t X26 = 0;
|
||||
uint32_t X27 = 0;
|
||||
uint32_t X28 = 0;
|
||||
uint32_t X29 = 0;
|
||||
uint32_t X30 = 0;
|
||||
uint32_t X31 = 0;
|
||||
uint32_t PC = 0;
|
||||
uint32_t NEXT_PC = 0;
|
||||
uint8_t PRIV = 0;
|
||||
uint32_t DPC = 0;
|
||||
uint32_t trap_state = 0, pending_trap = 0;
|
||||
uint64_t icount = 0;
|
||||
uint64_t cycle = 0;
|
||||
uint64_t instret = 0;
|
||||
uint32_t instruction = 0;
|
||||
uint32_t last_branch = 0;
|
||||
} reg;
|
||||
#pragma pack(pop)
|
||||
std::array<address_type, 4> addr_mode;
|
||||
|
||||
uint64_t interrupt_sim=0;
|
||||
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
|
||||
};
|
||||
|
||||
}
|
||||
}
|
||||
#endif /* _TGC_C_H_ */
|
@ -1,175 +0,0 @@
|
||||
#include "tgc_c.h"
|
||||
#include <vector>
|
||||
#include <array>
|
||||
#include <cstdlib>
|
||||
#include <algorithm>
|
||||
|
||||
namespace iss {
|
||||
namespace arch {
|
||||
namespace {
|
||||
// according to
|
||||
// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
|
||||
#ifdef __GCC__
|
||||
constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
|
||||
#elif __cplusplus < 201402L
|
||||
constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
|
||||
constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
|
||||
#else
|
||||
constexpr size_t bit_count(uint32_t u) {
|
||||
size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
|
||||
return ((uCount + (uCount >> 3)) & 030707070707) % 63;
|
||||
}
|
||||
#endif
|
||||
|
||||
using opcode_e = traits<tgc_c>::opcode_e;
|
||||
|
||||
/****************************************************************************
|
||||
* start opcode definitions
|
||||
****************************************************************************/
|
||||
struct instruction_desriptor {
|
||||
size_t length;
|
||||
uint32_t value;
|
||||
uint32_t mask;
|
||||
opcode_e op;
|
||||
};
|
||||
|
||||
const std::array<instruction_desriptor, 90> instr_descr = {{
|
||||
/* entries are: size, valid value, valid mask, function ptr */
|
||||
{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, opcode_e::LUI},
|
||||
{32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, opcode_e::AUIPC},
|
||||
{32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, opcode_e::JAL},
|
||||
{32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, opcode_e::JALR},
|
||||
{32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, opcode_e::BEQ},
|
||||
{32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, opcode_e::BNE},
|
||||
{32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, opcode_e::BLT},
|
||||
{32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, opcode_e::BGE},
|
||||
{32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, opcode_e::BLTU},
|
||||
{32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, opcode_e::BGEU},
|
||||
{32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, opcode_e::LB},
|
||||
{32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, opcode_e::LH},
|
||||
{32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, opcode_e::LW},
|
||||
{32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, opcode_e::LBU},
|
||||
{32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, opcode_e::LHU},
|
||||
{32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, opcode_e::SB},
|
||||
{32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, opcode_e::SH},
|
||||
{32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, opcode_e::SW},
|
||||
{32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, opcode_e::ADDI},
|
||||
{32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, opcode_e::SLTI},
|
||||
{32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, opcode_e::SLTIU},
|
||||
{32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, opcode_e::XORI},
|
||||
{32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, opcode_e::ORI},
|
||||
{32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, opcode_e::ANDI},
|
||||
{32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, opcode_e::SLLI},
|
||||
{32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRLI},
|
||||
{32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRAI},
|
||||
{32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::ADD},
|
||||
{32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::SUB},
|
||||
{32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::SLL},
|
||||
{32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::SLT},
|
||||
{32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::SLTU},
|
||||
{32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::XOR},
|
||||
{32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRL},
|
||||
{32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRA},
|
||||
{32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::OR},
|
||||
{32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::AND},
|
||||
{32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE},
|
||||
{32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, opcode_e::ECALL},
|
||||
{32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, opcode_e::EBREAK},
|
||||
{32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::URET},
|
||||
{32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::SRET},
|
||||
{32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::MRET},
|
||||
{32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, opcode_e::WFI},
|
||||
{32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::DRET},
|
||||
{32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRW},
|
||||
{32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRS},
|
||||
{32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRC},
|
||||
{32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRWI},
|
||||
{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRSI},
|
||||
{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRCI},
|
||||
{32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE_I},
|
||||
{32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::MUL},
|
||||
{32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::MULH},
|
||||
{32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::MULHSU},
|
||||
{32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::MULHU},
|
||||
{32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::DIV},
|
||||
{32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::DIVU},
|
||||
{32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::REM},
|
||||
{32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::REMU},
|
||||
{16, 0b0000000000000000, 0b1110000000000011, opcode_e::CADDI4SPN},
|
||||
{16, 0b0100000000000000, 0b1110000000000011, opcode_e::CLW},
|
||||
{16, 0b1100000000000000, 0b1110000000000011, opcode_e::CSW},
|
||||
{16, 0b0000000000000001, 0b1110000000000011, opcode_e::CADDI},
|
||||
{16, 0b0000000000000001, 0b1110111110000011, opcode_e::CNOP},
|
||||
{16, 0b0010000000000001, 0b1110000000000011, opcode_e::CJAL},
|
||||
{16, 0b0100000000000001, 0b1110000000000011, opcode_e::CLI},
|
||||
{16, 0b0110000000000001, 0b1110000000000011, opcode_e::CLUI},
|
||||
{16, 0b0110000100000001, 0b1110111110000011, opcode_e::CADDI16SP},
|
||||
{16, 0b0110000000000001, 0b1111000001111111, opcode_e::__reserved_clui},
|
||||
{16, 0b1000000000000001, 0b1111110000000011, opcode_e::CSRLI},
|
||||
{16, 0b1000010000000001, 0b1111110000000011, opcode_e::CSRAI},
|
||||
{16, 0b1000100000000001, 0b1110110000000011, opcode_e::CANDI},
|
||||
{16, 0b1000110000000001, 0b1111110001100011, opcode_e::CSUB},
|
||||
{16, 0b1000110000100001, 0b1111110001100011, opcode_e::CXOR},
|
||||
{16, 0b1000110001000001, 0b1111110001100011, opcode_e::COR},
|
||||
{16, 0b1000110001100001, 0b1111110001100011, opcode_e::CAND},
|
||||
{16, 0b1010000000000001, 0b1110000000000011, opcode_e::CJ},
|
||||
{16, 0b1100000000000001, 0b1110000000000011, opcode_e::CBEQZ},
|
||||
{16, 0b1110000000000001, 0b1110000000000011, opcode_e::CBNEZ},
|
||||
{16, 0b0000000000000010, 0b1111000000000011, opcode_e::CSLLI},
|
||||
{16, 0b0100000000000010, 0b1110000000000011, opcode_e::CLWSP},
|
||||
{16, 0b1000000000000010, 0b1111000000000011, opcode_e::CMV},
|
||||
{16, 0b1000000000000010, 0b1111000001111111, opcode_e::CJR},
|
||||
{16, 0b1000000000000010, 0b1111111111111111, opcode_e::__reserved_cmv},
|
||||
{16, 0b1001000000000010, 0b1111000000000011, opcode_e::CADD},
|
||||
{16, 0b1001000000000010, 0b1111000001111111, opcode_e::CJALR},
|
||||
{16, 0b1001000000000010, 0b1111111111111111, opcode_e::CEBREAK},
|
||||
{16, 0b1100000000000010, 0b1110000000000011, opcode_e::CSWSP},
|
||||
{16, 0b0000000000000000, 0b1111111111111111, opcode_e::DII},
|
||||
}};
|
||||
|
||||
}
|
||||
|
||||
template<>
|
||||
struct instruction_decoder<tgc_c> {
|
||||
using opcode_e = traits<tgc_c>::opcode_e;
|
||||
using code_word_t=traits<tgc_c>::code_word_t;
|
||||
|
||||
struct instruction_pattern {
|
||||
uint32_t value;
|
||||
uint32_t mask;
|
||||
opcode_e id;
|
||||
};
|
||||
|
||||
std::array<std::vector<instruction_pattern>, 4> qlut;
|
||||
|
||||
template<typename T>
|
||||
unsigned decode_instruction(T);
|
||||
|
||||
instruction_decoder() {
|
||||
for (auto instr : instr_descr) {
|
||||
auto quadrant = instr.value & 0x3;
|
||||
qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
|
||||
}
|
||||
for(auto& lut: qlut){
|
||||
std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
|
||||
return bit_count(a.mask) > bit_count(b.mask);
|
||||
});
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
template<>
|
||||
unsigned instruction_decoder<tgc_c>::decode_instruction<traits<tgc_c>::code_word_t>(traits<tgc_c>::code_word_t instr){
|
||||
auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
|
||||
return !((instr&e.mask) ^ e.value );
|
||||
});
|
||||
return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
|
||||
}
|
||||
|
||||
|
||||
std::unique_ptr<instruction_decoder<tgc_c>> traits<tgc_c>::get_decoder(){
|
||||
return std::make_unique<instruction_decoder<tgc_c>>();
|
||||
}
|
||||
|
||||
}
|
||||
}
|
@ -1,50 +0,0 @@
|
||||
#ifndef _ISS_ARCH_TGC_MAPPER_H
|
||||
#define _ISS_ARCH_TGC_MAPPER_H
|
||||
|
||||
#include "riscv_hart_m_p.h"
|
||||
#include "tgc_c.h"
|
||||
using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
|
||||
#ifdef CORE_TGC_A
|
||||
#include "riscv_hart_m_p.h"
|
||||
#include <iss/arch/tgc_a.h>
|
||||
using tgc_a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_a>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_B
|
||||
#include "riscv_hart_m_p.h"
|
||||
#include <iss/arch/tgc_b.h>
|
||||
using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_C_XRB_NN
|
||||
#include "riscv_hart_m_p.h"
|
||||
#include "hwl.h"
|
||||
#include <iss/arch/tgc_c_xrb_nn.h>
|
||||
using tgc_c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_D
|
||||
#include "riscv_hart_mu_p.h"
|
||||
#include <iss/arch/tgc_d.h>
|
||||
using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_D_XRB_MAC
|
||||
#include "riscv_hart_mu_p.h"
|
||||
#include <iss/arch/tgc_d_xrb_mac.h>
|
||||
using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_D_XRB_NN
|
||||
#include "riscv_hart_mu_p.h"
|
||||
#include "hwl.h"
|
||||
#include <iss/arch/tgc_d_xrb_nn.h>
|
||||
using tgc_d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_E
|
||||
#include "riscv_hart_mu_p.h"
|
||||
#include <iss/arch/tgc_e.h>
|
||||
using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_X
|
||||
#include "riscv_hart_mu_p.h"
|
||||
#include <iss/arch/tgc_x.h>
|
||||
using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
|
||||
#endif
|
||||
|
||||
#endif
|
@ -1,172 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2023 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contributors:
|
||||
* eyck@minres.com - initial implementation
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _RISCV_HART_M_P_WT_CACHE_H
|
||||
#define _RISCV_HART_M_P_WT_CACHE_H
|
||||
|
||||
#include <iss/vm_types.h>
|
||||
#include <util/ities.h>
|
||||
#include <vector>
|
||||
#include <map>
|
||||
#include <memory>
|
||||
|
||||
namespace iss {
|
||||
namespace arch {
|
||||
namespace cache {
|
||||
|
||||
enum class state { INVALID, VALID};
|
||||
struct line {
|
||||
uint64_t tag_addr{0};
|
||||
state st{state::INVALID};
|
||||
std::vector<uint8_t> data;
|
||||
line(unsigned line_sz): data(line_sz) {}
|
||||
};
|
||||
struct set {
|
||||
std::vector<line> ways;
|
||||
set(unsigned ways_count, line const& l): ways(ways_count, l) {}
|
||||
};
|
||||
struct cache {
|
||||
std::vector<set> sets;
|
||||
|
||||
cache(unsigned size, unsigned line_sz, unsigned ways) {
|
||||
line const ref_line{line_sz};
|
||||
set const ref_set{ways, ref_line};
|
||||
sets.resize(size/(ways*line_sz), ref_set);
|
||||
}
|
||||
};
|
||||
|
||||
struct wt_policy {
|
||||
bool is_cacheline_hit(cache& c );
|
||||
};
|
||||
}
|
||||
|
||||
// write thru, allocate on read, direct mapped or set-associative with round-robin replacement policy
|
||||
template <typename BASE> class wt_cache : public BASE {
|
||||
public:
|
||||
using base_class = BASE;
|
||||
using this_class = wt_cache<BASE>;
|
||||
using reg_t = typename BASE::reg_t;
|
||||
using mem_read_f = typename BASE::mem_read_f;
|
||||
using mem_write_f = typename BASE::mem_write_f;
|
||||
using phys_addr_t = typename BASE::phys_addr_t;
|
||||
|
||||
wt_cache();
|
||||
virtual ~wt_cache() = default;
|
||||
|
||||
unsigned size{4096};
|
||||
unsigned line_sz{32};
|
||||
unsigned ways{1};
|
||||
uint64_t io_address{0xf0000000};
|
||||
uint64_t io_addr_mask{0xf0000000};
|
||||
protected:
|
||||
iss::status read_cache(phys_addr_t addr, unsigned, uint8_t *const);
|
||||
iss::status write_cache(phys_addr_t addr, unsigned, uint8_t const *const);
|
||||
std::function<mem_read_f> cache_mem_rd_delegate;
|
||||
std::function<mem_write_f> cache_mem_wr_delegate;
|
||||
std::unique_ptr<cache::cache> dcache_ptr;
|
||||
std::unique_ptr<cache::cache> icache_ptr;
|
||||
size_t get_way_select() {
|
||||
return 0;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
template<typename BASE>
|
||||
inline wt_cache<BASE>::wt_cache() {
|
||||
auto cb = base_class::replace_mem_access(
|
||||
[this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l,d);},
|
||||
[this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l,d);});
|
||||
cache_mem_rd_delegate = cb.first;
|
||||
cache_mem_wr_delegate = cb.second;
|
||||
}
|
||||
|
||||
template<typename BASE>
|
||||
iss::status iss::arch::wt_cache<BASE>::read_cache(phys_addr_t a, unsigned l, uint8_t* const d) {
|
||||
if(!icache_ptr) {
|
||||
icache_ptr.reset(new cache::cache(size, line_sz, ways));
|
||||
dcache_ptr.reset(new cache::cache(size, line_sz, ways));
|
||||
}
|
||||
if((a.val&io_addr_mask) != io_address) {
|
||||
auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways);
|
||||
auto tag_addr=a.val>>util::ilog2(line_sz);
|
||||
auto& set = (is_fetch(a.access)?icache_ptr:dcache_ptr)->sets[set_addr];
|
||||
for(auto& cl: set.ways) {
|
||||
if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
|
||||
auto start_addr = a.val&(line_sz-1);
|
||||
for(auto i = 0U; i<l; ++i)
|
||||
d[i] = cl.data[start_addr+i];
|
||||
return iss::Ok;
|
||||
}
|
||||
}
|
||||
auto& cl = set.ways[get_way_select()];
|
||||
phys_addr_t cl_addr{a};
|
||||
cl_addr.val=tag_addr<<util::ilog2(line_sz);
|
||||
cache_mem_rd_delegate(cl_addr, line_sz, cl.data.data());
|
||||
cl.tag_addr=tag_addr;
|
||||
cl.st=cache::state::VALID;
|
||||
auto start_addr = a.val&(line_sz-1);
|
||||
for(auto i = 0U; i<l; ++i)
|
||||
d[i] = cl.data[start_addr+i];
|
||||
return iss::Ok;
|
||||
} else
|
||||
return cache_mem_rd_delegate(a, l, d);
|
||||
}
|
||||
|
||||
template<typename BASE>
|
||||
iss::status iss::arch::wt_cache<BASE>::write_cache(phys_addr_t a, unsigned l, const uint8_t* const d) {
|
||||
if(!dcache_ptr)
|
||||
dcache_ptr.reset(new cache::cache(size, line_sz, ways));
|
||||
auto res = cache_mem_wr_delegate(a, l, d);
|
||||
if(res == iss::Ok && ((a.val&io_addr_mask) != io_address)) {
|
||||
auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways);
|
||||
auto tag_addr=a.val>>util::ilog2(line_sz);
|
||||
auto& set = dcache_ptr->sets[set_addr];
|
||||
for(auto& cl: set.ways) {
|
||||
if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
|
||||
auto start_addr = a.val&(line_sz-1);
|
||||
for(auto i = 0U; i<l; ++i)
|
||||
cl.data[start_addr+i] = d[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
|
||||
|
||||
} // namespace arch
|
||||
} // namespace iss
|
||||
|
||||
#endif /* _RISCV_HART_M_P_H */
|
@ -1,110 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2021 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _ISS_FACTORY_H_
|
||||
#define _ISS_FACTORY_H_
|
||||
|
||||
#include <iss/iss.h>
|
||||
#include <memory>
|
||||
#include <unordered_map>
|
||||
#include <functional>
|
||||
#include <string>
|
||||
#include <algorithm>
|
||||
#include <vector>
|
||||
|
||||
namespace iss {
|
||||
|
||||
using cpu_ptr = std::unique_ptr<iss::arch_if>;
|
||||
using vm_ptr= std::unique_ptr<iss::vm_if>;
|
||||
|
||||
template<typename PLAT>
|
||||
std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){
|
||||
using core_type = typename PLAT::core;
|
||||
core_type* lcpu = new PLAT();
|
||||
if(backend == "interp")
|
||||
return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
|
||||
#ifdef WITH_LLVM
|
||||
if(backend == "llvm")
|
||||
return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
|
||||
#endif
|
||||
#ifdef WITH_TCC
|
||||
if(backend == "tcc")
|
||||
return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
|
||||
#endif
|
||||
return {nullptr, nullptr};
|
||||
}
|
||||
|
||||
|
||||
class core_factory {
|
||||
using cpu_ptr = std::unique_ptr<iss::arch_if>;
|
||||
using vm_ptr= std::unique_ptr<iss::vm_if>;
|
||||
using base_t = std::tuple<cpu_ptr, vm_ptr>;
|
||||
using create_fn = std::function<base_t(unsigned, void*) >;
|
||||
using registry_t = std::unordered_map<std::string, create_fn> ;
|
||||
|
||||
registry_t registry;
|
||||
|
||||
core_factory() = default;
|
||||
core_factory(const core_factory &) = delete;
|
||||
core_factory & operator=(const core_factory &) = delete;
|
||||
|
||||
public:
|
||||
static core_factory & instance() { static core_factory bf; return bf; }
|
||||
|
||||
bool register_creator(const std::string &, create_fn const&);
|
||||
|
||||
base_t create(const std::string &, unsigned gdb_port=0, void* init_data=nullptr) const;
|
||||
|
||||
std::vector<std::string> get_names() {
|
||||
std::vector<std::string> keys{registry.size()};
|
||||
std::transform(std::begin(registry), std::end(registry), std::begin(keys), [](std::pair<std::string, create_fn> const& p){
|
||||
return p.first;
|
||||
});
|
||||
return keys;
|
||||
}
|
||||
};
|
||||
|
||||
inline bool core_factory::register_creator(const std::string & className, create_fn const& fn) {
|
||||
registry[className] = fn;
|
||||
return true;
|
||||
}
|
||||
|
||||
inline core_factory::base_t core_factory::create(const std::string &className, unsigned gdb_port, void* data) const {
|
||||
registry_t::const_iterator regEntry = registry.find(className);
|
||||
if (regEntry != registry.end())
|
||||
return regEntry->second(gdb_port, data);
|
||||
return {nullptr, nullptr};
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif /* _ISS_FACTORY_H_ */
|
@ -1,118 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2023, MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contributors:
|
||||
* eyck@minres.com - initial API and implementation
|
||||
******************************************************************************/
|
||||
|
||||
#include "cycle_estimate.h"
|
||||
|
||||
#include <iss/arch_if.h>
|
||||
#include <util/logging.h>
|
||||
#include <rapidjson/document.h>
|
||||
#include <rapidjson/istreamwrapper.h>
|
||||
#include <rapidjson/writer.h>
|
||||
#include <rapidjson/stringbuffer.h>
|
||||
#include <rapidjson/ostreamwrapper.h>
|
||||
#include <rapidjson/error/en.h>
|
||||
#include <fstream>
|
||||
|
||||
using namespace rapidjson;
|
||||
using namespace std;
|
||||
|
||||
iss::plugin::cycle_estimate::cycle_estimate(string const& config_file_name)
|
||||
: instr_if(nullptr)
|
||||
, config_file_name(config_file_name)
|
||||
{
|
||||
}
|
||||
|
||||
iss::plugin::cycle_estimate::~cycle_estimate() {
|
||||
}
|
||||
|
||||
bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
|
||||
instr_if = vm.get_arch()->get_instrumentation_if();
|
||||
if(!instr_if) return false;
|
||||
const string core_name = instr_if->core_type_name();
|
||||
if (config_file_name.length() > 0) {
|
||||
ifstream is(config_file_name);
|
||||
if (is.is_open()) {
|
||||
try {
|
||||
IStreamWrapper isw(is);
|
||||
Document d;
|
||||
ParseResult ok = d.ParseStream(isw);
|
||||
if(ok) {
|
||||
Value& val = d[core_name.c_str()];
|
||||
if(val.IsArray()){
|
||||
delays.reserve(val.Size());
|
||||
for (auto it = val.Begin(); it != val.End(); ++it) {
|
||||
auto& name = (*it)["name"];
|
||||
auto& size = (*it)["size"];
|
||||
auto& delay = (*it)["delay"];
|
||||
auto& branch = (*it)["branch"];
|
||||
if(delay.IsArray()) {
|
||||
auto dt = delay[0].Get<unsigned>();
|
||||
auto dnt = delay[1].Get<unsigned>();
|
||||
delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
|
||||
} else if(delay.Is<unsigned>()) {
|
||||
auto d = delay.Get<unsigned>();
|
||||
delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
|
||||
} else
|
||||
throw runtime_error("JSON parse error");
|
||||
}
|
||||
} else {
|
||||
LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
|
||||
return false;
|
||||
}
|
||||
} catch (runtime_error &e) {
|
||||
LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
LOG(ERR) << "Could not open input file " << config_file_name;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
|
||||
}
|
||||
|
||||
void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
|
||||
assert(instr_if && "No instrumentation interface available but callback executed");
|
||||
auto entry = delays[instr_info.instr_id];
|
||||
bool taken = instr_if->is_branch_taken();
|
||||
if (taken && (entry.taken > 1))
|
||||
instr_if->update_last_instr_cycles(entry.taken);
|
||||
else if (entry.not_taken > 1)
|
||||
instr_if->update_last_instr_cycles(entry.not_taken);
|
||||
}
|
@ -1,214 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2023, MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contributors:
|
||||
* alex.com - initial implementation
|
||||
******************************************************************************/
|
||||
|
||||
#include <iss/arch_if.h>
|
||||
#include <iss/plugin/pctrace.h>
|
||||
#include <util/logging.h>
|
||||
#include <util/ities.h>
|
||||
#include <rapidjson/document.h>
|
||||
#include <rapidjson/istreamwrapper.h>
|
||||
#include <rapidjson/writer.h>
|
||||
#include <rapidjson/stringbuffer.h>
|
||||
#include <rapidjson/ostreamwrapper.h>
|
||||
#include <rapidjson/error/en.h>
|
||||
#include <fstream>
|
||||
#include <iostream>
|
||||
#ifdef WITH_LZ4
|
||||
#include <lz4frame.h>
|
||||
#endif
|
||||
|
||||
namespace iss {
|
||||
namespace plugin {
|
||||
|
||||
using namespace rapidjson;
|
||||
using namespace std;
|
||||
|
||||
#ifdef WITH_LZ4
|
||||
class lz4compress_steambuf: public std::streambuf {
|
||||
public:
|
||||
lz4compress_steambuf(const lz4compress_steambuf&) = delete;
|
||||
lz4compress_steambuf& operator=(const lz4compress_steambuf&) = delete;
|
||||
lz4compress_steambuf(std::ostream &sink, size_t buf_size)
|
||||
: sink(sink)
|
||||
, src_buf(buf_size)
|
||||
, dest_buf(LZ4F_compressBound(buf_size, nullptr))
|
||||
{
|
||||
auto errCode = LZ4F_createCompressionContext(&ctx, LZ4F_VERSION);
|
||||
if (LZ4F_isError(errCode) != 0)
|
||||
throw std::runtime_error(std::string("Failed to create LZ4 context: ") + LZ4F_getErrorName(errCode));
|
||||
size_t ret = LZ4F_compressBegin(ctx, &dest_buf.front(), dest_buf.capacity(), nullptr);
|
||||
if (LZ4F_isError(ret) != 0)
|
||||
throw std::runtime_error(std::string("Failed to start LZ4 compression: ") + LZ4F_getErrorName(ret));
|
||||
setp(src_buf.data(), src_buf.data() + src_buf.size() - 1);
|
||||
sink.write(dest_buf.data(), ret);
|
||||
}
|
||||
|
||||
~lz4compress_steambuf() {
|
||||
close();
|
||||
}
|
||||
|
||||
void close() {
|
||||
if (closed)
|
||||
return;
|
||||
sync();
|
||||
auto ret = LZ4F_compressEnd(ctx, dest_buf.data(), dest_buf.capacity(), nullptr);
|
||||
if (LZ4F_isError(ret) != 0)
|
||||
throw std::runtime_error(std::string("Failed to finish LZ4 compression: ") + LZ4F_getErrorName(ret));
|
||||
sink.write(dest_buf.data(), ret);
|
||||
LZ4F_freeCompressionContext(ctx);
|
||||
closed = true;
|
||||
}
|
||||
|
||||
private:
|
||||
int_type overflow(int_type ch) override {
|
||||
compress_and_write();
|
||||
*pptr() = static_cast<char_type>(ch);
|
||||
pbump(1);
|
||||
return ch;
|
||||
}
|
||||
|
||||
int_type sync() override {
|
||||
compress_and_write();
|
||||
return 0;
|
||||
}
|
||||
|
||||
void compress_and_write() {
|
||||
if (closed)
|
||||
throw std::runtime_error("Cannot write to closed stream");
|
||||
if(auto orig_size = pptr() - pbase()){
|
||||
auto ret = LZ4F_compressUpdate(ctx, dest_buf.data(), dest_buf.capacity(), pbase(), orig_size, nullptr);
|
||||
if (LZ4F_isError(ret) != 0)
|
||||
throw std::runtime_error(std::string("LZ4 compression failed: ") + LZ4F_getErrorName(ret));
|
||||
if(ret) sink.write(dest_buf.data(), ret);
|
||||
pbump(-orig_size);
|
||||
}
|
||||
}
|
||||
|
||||
std::ostream &sink;
|
||||
std::vector<char> src_buf;
|
||||
std::vector<char> dest_buf;
|
||||
LZ4F_compressionContext_t ctx{ nullptr };
|
||||
bool closed{ false };
|
||||
};
|
||||
#endif
|
||||
|
||||
pctrace::pctrace(std::string const &filename)
|
||||
: instr_if(nullptr)
|
||||
, filename(filename)
|
||||
, output("output.trc")
|
||||
#ifdef WITH_LZ4
|
||||
, strbuf(new lz4compress_steambuf(output, 4096))
|
||||
, ostr(strbuf.get())
|
||||
#endif
|
||||
{ }
|
||||
|
||||
pctrace::~pctrace() { }
|
||||
|
||||
bool pctrace::registration(const char *const version, vm_if& vm) {
|
||||
instr_if = vm.get_arch()->get_instrumentation_if();
|
||||
if(!instr_if) return false;
|
||||
const string core_name = instr_if->core_type_name();
|
||||
if (filename.length() > 0) {
|
||||
ifstream is(filename);
|
||||
if (is.is_open()) {
|
||||
try {
|
||||
IStreamWrapper isw(is);
|
||||
Document d;
|
||||
ParseResult ok = d.ParseStream(isw);
|
||||
if(ok) {
|
||||
Value& val = d[core_name.c_str()];
|
||||
if(val.IsArray()){
|
||||
delays.reserve(val.Size());
|
||||
for (auto it = val.Begin(); it != val.End(); ++it) {
|
||||
auto& name = (*it)["name"];
|
||||
auto& size = (*it)["size"];
|
||||
auto& delay = (*it)["delay"];
|
||||
auto& branch = (*it)["branch"];
|
||||
if(delay.IsArray()) {
|
||||
auto dt = delay[0].Get<unsigned>();
|
||||
auto dnt = delay[1].Get<unsigned>();
|
||||
delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
|
||||
} else if(delay.Is<unsigned>()) {
|
||||
auto d = delay.Get<unsigned>();
|
||||
delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
|
||||
} else
|
||||
throw runtime_error("JSON parse error");
|
||||
|
||||
}
|
||||
} else {
|
||||
LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
|
||||
return false;
|
||||
}
|
||||
} catch (runtime_error &e) {
|
||||
LOG(ERR) << "Could not parse input file " << filename << ", reason: " << e.what();
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
LOG(ERR) << "Could not open input file " << filename;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
void pctrace::callback(instr_info_t iinfo) {
|
||||
auto delay = 0;
|
||||
size_t id = iinfo.instr_id;
|
||||
auto entry = delays[id];
|
||||
auto instr = instr_if->get_instr_word();
|
||||
auto call = id==65 || id ==86 || ((id==2 || id==3) && bit_sub<7,5>(instr)!=0) ;//not taking care of tail calls (jalr with loading x6)
|
||||
bool taken = instr_if->is_branch_taken();
|
||||
bool compressed = (instr&0x3)!=0x3;
|
||||
if (taken) {
|
||||
delay = entry.taken;
|
||||
if(entry.taken > 1)
|
||||
instr_if->update_last_instr_cycles(entry.taken);
|
||||
} else {
|
||||
delay = entry.not_taken;
|
||||
if (entry.not_taken > 1)
|
||||
instr_if->update_last_instr_cycles(entry.not_taken);
|
||||
}
|
||||
#ifndef WITH_LZ4
|
||||
output<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
|
||||
#else
|
||||
auto rdbuf=ostr.rdbuf();
|
||||
ostr<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
@ -1,102 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2023, MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contributors:
|
||||
* eyck@minres.com - initial API and implementation
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _ISS_PLUGIN_COV_H_
|
||||
#define _ISS_PLUGIN_COV_H_
|
||||
|
||||
#include <iss/vm_plugin.h>
|
||||
#include "iss/instrumentation_if.h"
|
||||
#include <json/json.h>
|
||||
#include <string>
|
||||
#include <fstream>
|
||||
|
||||
|
||||
namespace iss {
|
||||
namespace plugin {
|
||||
class lz4compress_steambuf;
|
||||
class pctrace : public iss::vm_plugin {
|
||||
struct instr_delay {
|
||||
std::string instr_name;
|
||||
size_t size;
|
||||
size_t not_taken_delay;
|
||||
size_t taken_delay;
|
||||
};
|
||||
BEGIN_BF_DECL(instr_desc, uint32_t)
|
||||
BF_FIELD(taken, 24, 8)
|
||||
BF_FIELD(not_taken, 16, 8)
|
||||
BF_FIELD(is_branch, 8, 8)
|
||||
BF_FIELD(size, 0, 8)
|
||||
instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
|
||||
this->size=size;
|
||||
this->taken=taken;
|
||||
this->not_taken=not_taken;
|
||||
this->is_branch=branch;
|
||||
}
|
||||
END_BF_DECL();
|
||||
|
||||
public:
|
||||
|
||||
pctrace(const pctrace &) = delete;
|
||||
|
||||
pctrace(const pctrace &&) = delete;
|
||||
|
||||
pctrace(std::string const &);
|
||||
|
||||
virtual ~pctrace();
|
||||
|
||||
pctrace &operator=(const pctrace &) = delete;
|
||||
|
||||
pctrace &operator=(const pctrace &&) = delete;
|
||||
|
||||
bool registration(const char *const version, vm_if &arch) override;
|
||||
|
||||
sync_type get_sync() override { return POST_SYNC; };
|
||||
|
||||
void callback(instr_info_t) override;
|
||||
|
||||
private:
|
||||
iss::instrumentation_if *instr_if {nullptr};
|
||||
std::ofstream output;
|
||||
#ifdef WITH_LZ4
|
||||
std::unique_ptr<lz4compress_steambuf> strbuf;
|
||||
std::ostream ostr;
|
||||
#endif
|
||||
std::string filename;
|
||||
std::vector<instr_desc> delays;
|
||||
bool jumped{false}, first{true};
|
||||
};
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* _ISS_PLUGIN_COV_H_ */
|
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -29,41 +29,41 @@
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include "tgc_c.h"
|
||||
|
||||
#include "util/ities.h"
|
||||
#include <util/logging.h>
|
||||
#include <iss/arch/tgf_b.h>
|
||||
#include <cstdio>
|
||||
#include <cstring>
|
||||
#include <fstream>
|
||||
|
||||
using namespace iss::arch;
|
||||
|
||||
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_names;
|
||||
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
|
||||
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_b>::reg_names;
|
||||
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_b>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_b>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_b>::reg_byte_offsets;
|
||||
|
||||
tgc_c::tgc_c() = default;
|
||||
tgf_b::tgf_b() {
|
||||
reg.icount = 0;
|
||||
}
|
||||
|
||||
tgc_c::~tgc_c() = default;
|
||||
tgf_b::~tgf_b() = default;
|
||||
|
||||
void tgc_c::reset(uint64_t address) {
|
||||
auto base_ptr = reinterpret_cast<traits<tgc_c>::reg_t*>(get_regs_base_ptr());
|
||||
for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
|
||||
*(base_ptr+i)=0;
|
||||
void tgf_b::reset(uint64_t address) {
|
||||
for(size_t i=0; i<traits<tgf_b>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf_b>::reg_t),0));
|
||||
reg.PC=address;
|
||||
reg.NEXT_PC=reg.PC;
|
||||
reg.PRIV=0x3;
|
||||
reg.trap_state=0;
|
||||
reg.machine_state=0x3;
|
||||
reg.icount=0;
|
||||
}
|
||||
|
||||
uint8_t *tgc_c::get_regs_base_ptr() {
|
||||
uint8_t *tgf_b::get_regs_base_ptr() {
|
||||
return reinterpret_cast<uint8_t*>(®);
|
||||
}
|
||||
|
||||
tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
|
||||
tgf_b::phys_addr_t tgf_b::virt2phys(const iss::addr_t &pc) {
|
||||
return phys_addr_t(pc); // change logical address to physical address
|
||||
}
|
||||
|
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -29,48 +29,41 @@
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
<%
|
||||
def getRegisterSizes(){
|
||||
def regs = registers.collect{it.size}
|
||||
regs[-1]=64 // correct for NEXT_PC
|
||||
regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
|
||||
return regs
|
||||
}
|
||||
%>
|
||||
#include "${coreDef.name.toLowerCase()}.h"
|
||||
|
||||
#include "util/ities.h"
|
||||
#include <util/logging.h>
|
||||
#include <iss/arch/tgf_c.h>
|
||||
#include <cstdio>
|
||||
#include <cstring>
|
||||
#include <fstream>
|
||||
|
||||
using namespace iss::arch;
|
||||
|
||||
constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
|
||||
constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
|
||||
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_c>::reg_names;
|
||||
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
|
||||
|
||||
${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() = default;
|
||||
tgf_c::tgf_c() {
|
||||
reg.icount = 0;
|
||||
}
|
||||
|
||||
${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
|
||||
tgf_c::~tgf_c() = default;
|
||||
|
||||
void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
|
||||
auto base_ptr = reinterpret_cast<traits<${coreDef.name.toLowerCase()}>::reg_t*>(get_regs_base_ptr());
|
||||
for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i)
|
||||
*(base_ptr+i)=0;
|
||||
void tgf_c::reset(uint64_t address) {
|
||||
for(size_t i=0; i<traits<tgf_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgf_c>::reg_t),0));
|
||||
reg.PC=address;
|
||||
reg.NEXT_PC=reg.PC;
|
||||
reg.PRIV=0x3;
|
||||
reg.trap_state=0;
|
||||
reg.machine_state=0x3;
|
||||
reg.icount=0;
|
||||
}
|
||||
|
||||
uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
|
||||
uint8_t *tgf_c::get_regs_base_ptr() {
|
||||
return reinterpret_cast<uint8_t*>(®);
|
||||
}
|
||||
|
||||
${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
|
||||
tgf_c::phys_addr_t tgf_c::virt2phys(const iss::addr_t &pc) {
|
||||
return phys_addr_t(pc); // change logical address to physical address
|
||||
}
|
||||
|
426
src/main.cpp
426
src/main.cpp
@ -1,222 +1,204 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include <iostream>
|
||||
#include <vector>
|
||||
#include <array>
|
||||
#include <iss/factory.h>
|
||||
|
||||
#include <boost/lexical_cast.hpp>
|
||||
#include <boost/program_options.hpp>
|
||||
#include "iss/arch/tgc_mapper.h"
|
||||
#ifdef WITH_LLVM
|
||||
#include <iss/llvm/jit_helper.h>
|
||||
#endif
|
||||
#include <iss/log_categories.h>
|
||||
#include "iss/plugin/cycle_estimate.h"
|
||||
#include "iss/plugin/instruction_count.h"
|
||||
#include "iss/plugin/pctrace.h"
|
||||
#ifndef WIN32
|
||||
#include <iss/plugin/loader.h>
|
||||
#endif
|
||||
#if defined(HAS_LUA)
|
||||
#include <iss/plugin/lua.h>
|
||||
#endif
|
||||
|
||||
namespace po = boost::program_options;
|
||||
|
||||
int main(int argc, char *argv[]) {
|
||||
/*
|
||||
* Define and parse the program options
|
||||
*/
|
||||
po::variables_map clim;
|
||||
po::options_description desc("Options");
|
||||
// clang-format off
|
||||
desc.add_options()
|
||||
("help,h", "Print help message")
|
||||
("verbose,v", po::value<int>()->default_value(4), "Sets logging verbosity")
|
||||
("logfile,l", po::value<std::string>(), "Sets default log file.")
|
||||
("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
|
||||
("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
|
||||
("instructions,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
|
||||
("reset,r", po::value<std::string>(), "reset address")
|
||||
("dump-ir", "dump the intermediate representation")
|
||||
("elf,f", po::value<std::vector<std::string>>(), "ELF file(s) to load")
|
||||
("mem,m", po::value<std::string>(), "the memory input file")
|
||||
("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
|
||||
("backend", po::value<std::string>()->default_value("interp"), "the ISS backend to use, options are: interp, tcc")
|
||||
("isa", po::value<std::string>()->default_value("tgc_c"), "isa to use for simulation");
|
||||
// clang-format on
|
||||
auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
|
||||
try {
|
||||
po::store(parsed, clim); // can throw
|
||||
// --help option
|
||||
if (clim.count("help")) {
|
||||
std::cout << "DBT-RISE-RiscV simulator for RISC-V" << std::endl << desc << std::endl;
|
||||
return 0;
|
||||
}
|
||||
po::notify(clim); // throws on error, so do after help in case
|
||||
} catch (po::error &e) {
|
||||
// there are problems
|
||||
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
|
||||
std::cerr << desc << std::endl;
|
||||
return 1;
|
||||
}
|
||||
std::vector<std::string> args = collect_unrecognized(parsed.options, po::include_positional);
|
||||
|
||||
LOGGER(DEFAULT)::print_time() = false;
|
||||
LOGGER(connection)::print_time() = false;
|
||||
auto l = logging::as_log_level(clim["verbose"].as<int>());
|
||||
LOGGER(DEFAULT)::reporting_level() = l;
|
||||
LOGGER(connection)::reporting_level() = l;
|
||||
if (clim.count("logfile")) {
|
||||
// configure the connection logger
|
||||
auto f = fopen(clim["logfile"].as<std::string>().c_str(), "w");
|
||||
LOG_OUTPUT(DEFAULT)::stream() = f;
|
||||
LOG_OUTPUT(connection)::stream() = f;
|
||||
}
|
||||
|
||||
std::vector<iss::vm_plugin *> plugin_list;
|
||||
auto res = 0;
|
||||
try {
|
||||
#ifdef WITH_LLVM
|
||||
// application code comes here //
|
||||
iss::init_jit_debug(argc, argv);
|
||||
#endif
|
||||
bool dump = clim.count("dump-ir");
|
||||
auto & f = iss::core_factory::instance();
|
||||
// instantiate the simulator
|
||||
iss::vm_ptr vm{nullptr};
|
||||
iss::cpu_ptr cpu{nullptr};
|
||||
std::string isa_opt(clim["isa"].as<std::string>());
|
||||
if(isa_opt.size()==0 || isa_opt == "?") {
|
||||
std::cout<<"Available cores: "<<util::join(f.get_names(), ", ")<<std::endl;
|
||||
return 0;
|
||||
} else if (isa_opt.find('|') != std::string::npos) {
|
||||
std::tie(cpu, vm) = f.create(isa_opt+"|"+clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
|
||||
} else {
|
||||
auto base_isa = isa_opt.substr(0, 5);
|
||||
if(base_isa=="tgc_d" || base_isa=="tgc_e") {
|
||||
isa_opt += "|mu_p_clic_pmp|"+clim["backend"].as<std::string>();
|
||||
} else {
|
||||
isa_opt += "|m_p|"+clim["backend"].as<std::string>();
|
||||
}
|
||||
std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as<unsigned>());
|
||||
}
|
||||
if(!cpu ){
|
||||
LOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " <<clim["backend"].as<std::string>()<< std::endl;
|
||||
return 127;
|
||||
}
|
||||
if(!vm ){
|
||||
LOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " <<clim["backend"].as<std::string>()<< std::endl;
|
||||
return 127;
|
||||
}
|
||||
if (clim.count("plugin")) {
|
||||
for (std::string const& opt_val : clim["plugin"].as<std::vector<std::string>>()) {
|
||||
std::string plugin_name=opt_val;
|
||||
std::string arg{""};
|
||||
std::size_t found = opt_val.find('=');
|
||||
if (found != std::string::npos) {
|
||||
plugin_name = opt_val.substr(0, found);
|
||||
arg = opt_val.substr(found + 1, opt_val.size());
|
||||
}
|
||||
if (plugin_name == "ic") {
|
||||
auto *ic_plugin = new iss::plugin::instruction_count(arg);
|
||||
vm->register_plugin(*ic_plugin);
|
||||
plugin_list.push_back(ic_plugin);
|
||||
} else if (plugin_name == "ce") {
|
||||
auto *ce_plugin = new iss::plugin::cycle_estimate(arg);
|
||||
vm->register_plugin(*ce_plugin);
|
||||
plugin_list.push_back(ce_plugin);
|
||||
} else if (plugin_name == "pctrace") {
|
||||
auto *plugin = new iss::plugin::pctrace(arg);
|
||||
vm->register_plugin(*plugin);
|
||||
plugin_list.push_back(plugin);
|
||||
} else {
|
||||
#ifndef WIN32
|
||||
std::vector<char const*> a{};
|
||||
if(arg.length())
|
||||
a.push_back({arg.c_str()});
|
||||
iss::plugin::loader l(plugin_name, {{"initPlugin"}});
|
||||
auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
|
||||
if(plugin){
|
||||
vm->register_plugin(*plugin);
|
||||
plugin_list.push_back(plugin);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
|
||||
return 127;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if (clim.count("disass")) {
|
||||
vm->setDisassEnabled(true);
|
||||
LOGGER(disass)::reporting_level() = logging::INFO;
|
||||
LOGGER(disass)::print_time() = false;
|
||||
auto file_name = clim["disass"].as<std::string>();
|
||||
if (file_name.length() > 0) {
|
||||
LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
|
||||
LOGGER(disass)::print_severity() = false;
|
||||
}
|
||||
}
|
||||
uint64_t start_address = 0;
|
||||
if (clim.count("mem"))
|
||||
vm->get_arch()->load_file(clim["mem"].as<std::string>());
|
||||
if (clim.count("elf"))
|
||||
for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
|
||||
auto start_addr = vm->get_arch()->load_file(input);
|
||||
if (start_addr.second) start_address = start_addr.first;
|
||||
}
|
||||
for (std::string input : args) {
|
||||
auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files
|
||||
if (start_addr.second) start_address = start_addr.first;
|
||||
}
|
||||
if (clim.count("reset")) {
|
||||
auto str = clim["reset"].as<std::string>();
|
||||
start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), nullptr, 16) : std::stoull(str, nullptr, 10);
|
||||
}
|
||||
vm->reset(start_address);
|
||||
auto cycles = clim["instructions"].as<uint64_t>();
|
||||
res = vm->start(cycles, dump);
|
||||
} catch (std::exception &e) {
|
||||
LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
|
||||
<< std::endl;
|
||||
res = 2;
|
||||
}
|
||||
// cleanup to let plugins report of needed
|
||||
for (auto *p : plugin_list) {
|
||||
delete p;
|
||||
}
|
||||
return res;
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include <iostream>
|
||||
#include <iss/iss.h>
|
||||
|
||||
#include <boost/lexical_cast.hpp>
|
||||
#include <boost/program_options.hpp>
|
||||
#include <iss/arch/riscv_hart_m_p.h>
|
||||
#include <iss/arch/tgf_b.h>
|
||||
#include <iss/arch/tgf_c.h>
|
||||
#ifdef WITH_LLVM
|
||||
#include <iss/llvm/jit_helper.h>
|
||||
#endif
|
||||
#include <iss/log_categories.h>
|
||||
#include <iss/plugin/cycle_estimate.h>
|
||||
#include <iss/plugin/instruction_count.h>
|
||||
|
||||
namespace po = boost::program_options;
|
||||
|
||||
using cpu_ptr = std::unique_ptr<iss::arch_if>;
|
||||
using vm_ptr= std::unique_ptr<iss::vm_if>;
|
||||
|
||||
template<typename CORE>
|
||||
std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){
|
||||
CORE* lcpu = new iss::arch::riscv_hart_m_p<CORE>();
|
||||
if(backend == "interp")
|
||||
return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
|
||||
#ifdef WITH_LLVM
|
||||
if(backend == "llvm")
|
||||
return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
|
||||
#endif
|
||||
if(backend == "tcc")
|
||||
return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
|
||||
return {nullptr, nullptr};
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[]) {
|
||||
/*
|
||||
* Define and parse the program options
|
||||
*/
|
||||
po::variables_map clim;
|
||||
po::options_description desc("Options");
|
||||
// clang-format off
|
||||
desc.add_options()
|
||||
("help,h", "Print help message")
|
||||
("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
|
||||
("logfile,f", po::value<std::string>(), "Sets default log file.")
|
||||
("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
|
||||
("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
|
||||
("instructions,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
|
||||
("reset,r", po::value<std::string>(), "reset address")
|
||||
("dump-ir", "dump the intermediate representation")
|
||||
("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
|
||||
("mem,m", po::value<std::string>(), "the memory input file")
|
||||
("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
|
||||
("backend", po::value<std::string>()->default_value("tcc"), "the memory input file")
|
||||
("isa", po::value<std::string>()->default_value("tgf_c"), "isa to use for simulation");
|
||||
// clang-format on
|
||||
auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
|
||||
try {
|
||||
po::store(parsed, clim); // can throw
|
||||
// --help option
|
||||
if (clim.count("help")) {
|
||||
std::cout << "DBT-RISE-RiscV simulator for RISC-V" << std::endl << desc << std::endl;
|
||||
return 0;
|
||||
}
|
||||
po::notify(clim); // throws on error, so do after help in case
|
||||
} catch (po::error &e) {
|
||||
// there are problems
|
||||
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
|
||||
std::cerr << desc << std::endl;
|
||||
return 1;
|
||||
}
|
||||
std::vector<std::string> args = collect_unrecognized(parsed.options, po::include_positional);
|
||||
|
||||
LOGGER(DEFAULT)::print_time() = false;
|
||||
LOGGER(connection)::print_time() = false;
|
||||
if (clim.count("verbose")) {
|
||||
auto l = logging::as_log_level(clim["verbose"].as<int>());
|
||||
LOGGER(DEFAULT)::reporting_level() = l;
|
||||
LOGGER(connection)::reporting_level() = l;
|
||||
}
|
||||
if (clim.count("logfile")) {
|
||||
// configure the connection logger
|
||||
auto f = fopen(clim["logfile"].as<std::string>().c_str(), "w");
|
||||
LOG_OUTPUT(DEFAULT)::stream() = f;
|
||||
LOG_OUTPUT(connection)::stream() = f;
|
||||
}
|
||||
|
||||
std::vector<iss::vm_plugin *> plugin_list;
|
||||
auto res = 0;
|
||||
try {
|
||||
#ifdef WITH_LLVM
|
||||
// application code comes here //
|
||||
iss::init_jit_debug(argc, argv);
|
||||
#endif
|
||||
bool dump = clim.count("dump-ir");
|
||||
// instantiate the simulator
|
||||
vm_ptr vm{nullptr};
|
||||
cpu_ptr cpu{nullptr};
|
||||
std::string isa_opt(clim["isa"].as<std::string>());
|
||||
if (isa_opt == "tgf_b") {
|
||||
std::tie(cpu, vm) =
|
||||
create_cpu<iss::arch::tgf_b>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
|
||||
} else if (isa_opt == "tgf_c") {
|
||||
std::tie(cpu, vm) =
|
||||
create_cpu<iss::arch::tgf_c>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
|
||||
} else {
|
||||
LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
|
||||
return 127;
|
||||
}
|
||||
if (clim.count("plugin")) {
|
||||
for (std::string const& opt_val : clim["plugin"].as<std::vector<std::string>>()) {
|
||||
std::string plugin_name=opt_val;
|
||||
std::string filename{"cycles.txt"};
|
||||
std::size_t found = opt_val.find('=');
|
||||
if (found != std::string::npos) {
|
||||
plugin_name = opt_val.substr(0, found);
|
||||
filename = opt_val.substr(found + 1, opt_val.size());
|
||||
}
|
||||
if (plugin_name == "ic") {
|
||||
auto *ic_plugin = new iss::plugin::instruction_count(filename);
|
||||
vm->register_plugin(*ic_plugin);
|
||||
plugin_list.push_back(ic_plugin);
|
||||
} else if (plugin_name == "ce") {
|
||||
auto *ce_plugin = new iss::plugin::cycle_estimate(filename);
|
||||
vm->register_plugin(*ce_plugin);
|
||||
plugin_list.push_back(ce_plugin);
|
||||
} else {
|
||||
LOG(ERROR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
|
||||
return 127;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (clim.count("disass")) {
|
||||
vm->setDisassEnabled(true);
|
||||
LOGGER(disass)::reporting_level() = logging::INFO;
|
||||
LOGGER(disass)::print_time() = false;
|
||||
auto file_name = clim["disass"].as<std::string>();
|
||||
if (file_name.length() > 0) {
|
||||
LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
|
||||
LOGGER(disass)::print_severity() = false;
|
||||
}
|
||||
}
|
||||
uint64_t start_address = 0;
|
||||
if (clim.count("mem"))
|
||||
vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::tgf_b>::MEM);
|
||||
if (clim.count("elf"))
|
||||
for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
|
||||
auto start_addr = vm->get_arch()->load_file(input);
|
||||
if (start_addr.second) start_address = start_addr.first;
|
||||
}
|
||||
for (std::string input : args) {
|
||||
auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files
|
||||
if (start_addr.second) start_address = start_addr.first;
|
||||
}
|
||||
if (clim.count("reset")) {
|
||||
auto str = clim["reset"].as<std::string>();
|
||||
start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), nullptr, 16) : std::stoull(str, nullptr, 10);
|
||||
}
|
||||
vm->reset(start_address);
|
||||
auto cycles = clim["instructions"].as<uint64_t>();
|
||||
res = vm->start(cycles, dump);
|
||||
} catch (std::exception &e) {
|
||||
LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
|
||||
<< std::endl;
|
||||
res = 2;
|
||||
}
|
||||
// cleanup to let plugins report of needed
|
||||
for (auto *p : plugin_list) {
|
||||
delete p;
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
821
src/plugin/GCOV.cpp
Normal file
821
src/plugin/GCOV.cpp
Normal file
@ -0,0 +1,821 @@
|
||||
//===- GCOV.cpp - LLVM coverage tool --------------------------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// GCOV implements the interface to read and write coverage files that use
|
||||
// 'gcov' format.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "GCOV.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/FileSystem.h"
|
||||
#include "llvm/Support/Format.h"
|
||||
#include "llvm/Support/Path.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include <algorithm>
|
||||
#include <system_error>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// GCOVFile implementation.
|
||||
|
||||
/// readGCNO - Read GCNO buffer.
|
||||
bool GCOVFile::readGCNO(GCOVBuffer &Buffer) {
|
||||
if (!Buffer.readGCNOFormat())
|
||||
return false;
|
||||
if (!Buffer.readGCOVVersion(Version))
|
||||
return false;
|
||||
|
||||
if (!Buffer.readInt(Checksum))
|
||||
return false;
|
||||
while (true) {
|
||||
if (!Buffer.readFunctionTag())
|
||||
break;
|
||||
auto GFun = make_unique<GCOVFunction>(*this);
|
||||
if (!GFun->readGCNO(Buffer, Version))
|
||||
return false;
|
||||
Functions.push_back(std::move(GFun));
|
||||
}
|
||||
|
||||
GCNOInitialized = true;
|
||||
return true;
|
||||
}
|
||||
|
||||
/// readGCDA - Read GCDA buffer. It is required that readGCDA() can only be
|
||||
/// called after readGCNO().
|
||||
bool GCOVFile::readGCDA(GCOVBuffer &Buffer) {
|
||||
assert(GCNOInitialized && "readGCDA() can only be called after readGCNO()");
|
||||
if (!Buffer.readGCDAFormat())
|
||||
return false;
|
||||
GCOV::GCOVVersion GCDAVersion;
|
||||
if (!Buffer.readGCOVVersion(GCDAVersion))
|
||||
return false;
|
||||
if (Version != GCDAVersion) {
|
||||
errs() << "GCOV versions do not match.\n";
|
||||
return false;
|
||||
}
|
||||
|
||||
uint32_t GCDAChecksum;
|
||||
if (!Buffer.readInt(GCDAChecksum))
|
||||
return false;
|
||||
if (Checksum != GCDAChecksum) {
|
||||
errs() << "File checksums do not match: " << Checksum
|
||||
<< " != " << GCDAChecksum << ".\n";
|
||||
return false;
|
||||
}
|
||||
for (size_t i = 0, e = Functions.size(); i < e; ++i) {
|
||||
if (!Buffer.readFunctionTag()) {
|
||||
errs() << "Unexpected number of functions.\n";
|
||||
return false;
|
||||
}
|
||||
if (!Functions[i]->readGCDA(Buffer, Version))
|
||||
return false;
|
||||
}
|
||||
if (Buffer.readObjectTag()) {
|
||||
uint32_t Length;
|
||||
uint32_t Dummy;
|
||||
if (!Buffer.readInt(Length))
|
||||
return false;
|
||||
if (!Buffer.readInt(Dummy))
|
||||
return false; // checksum
|
||||
if (!Buffer.readInt(Dummy))
|
||||
return false; // num
|
||||
if (!Buffer.readInt(RunCount))
|
||||
return false;
|
||||
Buffer.advanceCursor(Length - 3);
|
||||
}
|
||||
while (Buffer.readProgramTag()) {
|
||||
uint32_t Length;
|
||||
if (!Buffer.readInt(Length))
|
||||
return false;
|
||||
Buffer.advanceCursor(Length);
|
||||
++ProgramCount;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void GCOVFile::print(raw_ostream &OS) const {
|
||||
for (const auto &FPtr : Functions)
|
||||
FPtr->print(OS);
|
||||
}
|
||||
|
||||
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
||||
/// dump - Dump GCOVFile content to dbgs() for debugging purposes.
|
||||
LLVM_DUMP_METHOD void GCOVFile::dump() const {
|
||||
print(dbgs());
|
||||
}
|
||||
#endif
|
||||
|
||||
/// collectLineCounts - Collect line counts. This must be used after
|
||||
/// reading .gcno and .gcda files.
|
||||
void GCOVFile::collectLineCounts(FileInfo &FI) {
|
||||
for (const auto &FPtr : Functions)
|
||||
FPtr->collectLineCounts(FI);
|
||||
FI.setRunCount(RunCount);
|
||||
FI.setProgramCount(ProgramCount);
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// GCOVFunction implementation.
|
||||
|
||||
/// readGCNO - Read a function from the GCNO buffer. Return false if an error
|
||||
/// occurs.
|
||||
bool GCOVFunction::readGCNO(GCOVBuffer &Buff, GCOV::GCOVVersion Version) {
|
||||
uint32_t Dummy;
|
||||
if (!Buff.readInt(Dummy))
|
||||
return false; // Function header length
|
||||
if (!Buff.readInt(Ident))
|
||||
return false;
|
||||
if (!Buff.readInt(Checksum))
|
||||
return false;
|
||||
if (Version != GCOV::V402) {
|
||||
uint32_t CfgChecksum;
|
||||
if (!Buff.readInt(CfgChecksum))
|
||||
return false;
|
||||
if (Parent.getChecksum() != CfgChecksum) {
|
||||
errs() << "File checksums do not match: " << Parent.getChecksum()
|
||||
<< " != " << CfgChecksum << " in (" << Name << ").\n";
|
||||
return false;
|
||||
}
|
||||
}
|
||||
if (!Buff.readString(Name))
|
||||
return false;
|
||||
if (!Buff.readString(Filename))
|
||||
return false;
|
||||
if (!Buff.readInt(LineNumber))
|
||||
return false;
|
||||
|
||||
// read blocks.
|
||||
if (!Buff.readBlockTag()) {
|
||||
errs() << "Block tag not found.\n";
|
||||
return false;
|
||||
}
|
||||
uint32_t BlockCount;
|
||||
if (!Buff.readInt(BlockCount))
|
||||
return false;
|
||||
for (uint32_t i = 0, e = BlockCount; i != e; ++i) {
|
||||
if (!Buff.readInt(Dummy))
|
||||
return false; // Block flags;
|
||||
Blocks.push_back(make_unique<GCOVBlock>(*this, i));
|
||||
}
|
||||
|
||||
// read edges.
|
||||
while (Buff.readEdgeTag()) {
|
||||
uint32_t EdgeCount;
|
||||
if (!Buff.readInt(EdgeCount))
|
||||
return false;
|
||||
EdgeCount = (EdgeCount - 1) / 2;
|
||||
uint32_t BlockNo;
|
||||
if (!Buff.readInt(BlockNo))
|
||||
return false;
|
||||
if (BlockNo >= BlockCount) {
|
||||
errs() << "Unexpected block number: " << BlockNo << " (in " << Name
|
||||
<< ").\n";
|
||||
return false;
|
||||
}
|
||||
for (uint32_t i = 0, e = EdgeCount; i != e; ++i) {
|
||||
uint32_t Dst;
|
||||
if (!Buff.readInt(Dst))
|
||||
return false;
|
||||
Edges.push_back(make_unique<GCOVEdge>(*Blocks[BlockNo], *Blocks[Dst]));
|
||||
GCOVEdge *Edge = Edges.back().get();
|
||||
Blocks[BlockNo]->addDstEdge(Edge);
|
||||
Blocks[Dst]->addSrcEdge(Edge);
|
||||
if (!Buff.readInt(Dummy))
|
||||
return false; // Edge flag
|
||||
}
|
||||
}
|
||||
|
||||
// read line table.
|
||||
while (Buff.readLineTag()) {
|
||||
uint32_t LineTableLength;
|
||||
// Read the length of this line table.
|
||||
if (!Buff.readInt(LineTableLength))
|
||||
return false;
|
||||
uint32_t EndPos = Buff.getCursor() + LineTableLength * 4;
|
||||
uint32_t BlockNo;
|
||||
// Read the block number this table is associated with.
|
||||
if (!Buff.readInt(BlockNo))
|
||||
return false;
|
||||
if (BlockNo >= BlockCount) {
|
||||
errs() << "Unexpected block number: " << BlockNo << " (in " << Name
|
||||
<< ").\n";
|
||||
return false;
|
||||
}
|
||||
GCOVBlock &Block = *Blocks[BlockNo];
|
||||
// Read the word that pads the beginning of the line table. This may be a
|
||||
// flag of some sort, but seems to always be zero.
|
||||
if (!Buff.readInt(Dummy))
|
||||
return false;
|
||||
|
||||
// Line information starts here and continues up until the last word.
|
||||
if (Buff.getCursor() != (EndPos - sizeof(uint32_t))) {
|
||||
StringRef F;
|
||||
// Read the source file name.
|
||||
if (!Buff.readString(F))
|
||||
return false;
|
||||
if (Filename != F) {
|
||||
errs() << "Multiple sources for a single basic block: " << Filename
|
||||
<< " != " << F << " (in " << Name << ").\n";
|
||||
return false;
|
||||
}
|
||||
// Read lines up to, but not including, the null terminator.
|
||||
while (Buff.getCursor() < (EndPos - 2 * sizeof(uint32_t))) {
|
||||
uint32_t Line;
|
||||
if (!Buff.readInt(Line))
|
||||
return false;
|
||||
// Line 0 means this instruction was injected by the compiler. Skip it.
|
||||
if (!Line)
|
||||
continue;
|
||||
Block.addLine(Line);
|
||||
}
|
||||
// Read the null terminator.
|
||||
if (!Buff.readInt(Dummy))
|
||||
return false;
|
||||
}
|
||||
// The last word is either a flag or padding, it isn't clear which. Skip
|
||||
// over it.
|
||||
if (!Buff.readInt(Dummy))
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
/// readGCDA - Read a function from the GCDA buffer. Return false if an error
|
||||
/// occurs.
|
||||
bool GCOVFunction::readGCDA(GCOVBuffer &Buff, GCOV::GCOVVersion Version) {
|
||||
uint32_t HeaderLength;
|
||||
if (!Buff.readInt(HeaderLength))
|
||||
return false; // Function header length
|
||||
|
||||
uint64_t EndPos = Buff.getCursor() + HeaderLength * sizeof(uint32_t);
|
||||
|
||||
uint32_t GCDAIdent;
|
||||
if (!Buff.readInt(GCDAIdent))
|
||||
return false;
|
||||
if (Ident != GCDAIdent) {
|
||||
errs() << "Function identifiers do not match: " << Ident
|
||||
<< " != " << GCDAIdent << " (in " << Name << ").\n";
|
||||
return false;
|
||||
}
|
||||
|
||||
uint32_t GCDAChecksum;
|
||||
if (!Buff.readInt(GCDAChecksum))
|
||||
return false;
|
||||
if (Checksum != GCDAChecksum) {
|
||||
errs() << "Function checksums do not match: " << Checksum
|
||||
<< " != " << GCDAChecksum << " (in " << Name << ").\n";
|
||||
return false;
|
||||
}
|
||||
|
||||
uint32_t CfgChecksum;
|
||||
if (Version != GCOV::V402) {
|
||||
if (!Buff.readInt(CfgChecksum))
|
||||
return false;
|
||||
if (Parent.getChecksum() != CfgChecksum) {
|
||||
errs() << "File checksums do not match: " << Parent.getChecksum()
|
||||
<< " != " << CfgChecksum << " (in " << Name << ").\n";
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
if (Buff.getCursor() < EndPos) {
|
||||
StringRef GCDAName;
|
||||
if (!Buff.readString(GCDAName))
|
||||
return false;
|
||||
if (Name != GCDAName) {
|
||||
errs() << "Function names do not match: " << Name << " != " << GCDAName
|
||||
<< ".\n";
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
if (!Buff.readArcTag()) {
|
||||
errs() << "Arc tag not found (in " << Name << ").\n";
|
||||
return false;
|
||||
}
|
||||
|
||||
uint32_t Count;
|
||||
if (!Buff.readInt(Count))
|
||||
return false;
|
||||
Count /= 2;
|
||||
|
||||
// This for loop adds the counts for each block. A second nested loop is
|
||||
// required to combine the edge counts that are contained in the GCDA file.
|
||||
for (uint32_t BlockNo = 0; Count > 0; ++BlockNo) {
|
||||
// The last block is always reserved for exit block
|
||||
if (BlockNo >= Blocks.size()) {
|
||||
errs() << "Unexpected number of edges (in " << Name << ").\n";
|
||||
return false;
|
||||
}
|
||||
if (BlockNo == Blocks.size() - 1)
|
||||
errs() << "(" << Name << ") has arcs from exit block.\n";
|
||||
GCOVBlock &Block = *Blocks[BlockNo];
|
||||
for (size_t EdgeNo = 0, End = Block.getNumDstEdges(); EdgeNo < End;
|
||||
++EdgeNo) {
|
||||
if (Count == 0) {
|
||||
errs() << "Unexpected number of edges (in " << Name << ").\n";
|
||||
return false;
|
||||
}
|
||||
uint64_t ArcCount;
|
||||
if (!Buff.readInt64(ArcCount))
|
||||
return false;
|
||||
Block.addCount(EdgeNo, ArcCount);
|
||||
--Count;
|
||||
}
|
||||
Block.sortDstEdges();
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
/// getEntryCount - Get the number of times the function was called by
|
||||
/// retrieving the entry block's count.
|
||||
uint64_t GCOVFunction::getEntryCount() const {
|
||||
return Blocks.front()->getCount();
|
||||
}
|
||||
|
||||
/// getExitCount - Get the number of times the function returned by retrieving
|
||||
/// the exit block's count.
|
||||
uint64_t GCOVFunction::getExitCount() const {
|
||||
return Blocks.back()->getCount();
|
||||
}
|
||||
|
||||
void GCOVFunction::print(raw_ostream &OS) const {
|
||||
OS << "===== " << Name << " (" << Ident << ") @ " << Filename << ":"
|
||||
<< LineNumber << "\n";
|
||||
for (const auto &Block : Blocks)
|
||||
Block->print(OS);
|
||||
}
|
||||
|
||||
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
||||
/// dump - Dump GCOVFunction content to dbgs() for debugging purposes.
|
||||
LLVM_DUMP_METHOD void GCOVFunction::dump() const {
|
||||
print(dbgs());
|
||||
}
|
||||
#endif
|
||||
|
||||
/// collectLineCounts - Collect line counts. This must be used after
|
||||
/// reading .gcno and .gcda files.
|
||||
void GCOVFunction::collectLineCounts(FileInfo &FI) {
|
||||
// If the line number is zero, this is a function that doesn't actually appear
|
||||
// in the source file, so there isn't anything we can do with it.
|
||||
if (LineNumber == 0)
|
||||
return;
|
||||
|
||||
for (const auto &Block : Blocks)
|
||||
Block->collectLineCounts(FI);
|
||||
FI.addFunctionLine(Filename, LineNumber, this);
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// GCOVBlock implementation.
|
||||
|
||||
/// ~GCOVBlock - Delete GCOVBlock and its content.
|
||||
GCOVBlock::~GCOVBlock() {
|
||||
SrcEdges.clear();
|
||||
DstEdges.clear();
|
||||
Lines.clear();
|
||||
}
|
||||
|
||||
/// addCount - Add to block counter while storing the edge count. If the
|
||||
/// destination has no outgoing edges, also update that block's count too.
|
||||
void GCOVBlock::addCount(size_t DstEdgeNo, uint64_t N) {
|
||||
assert(DstEdgeNo < DstEdges.size()); // up to caller to ensure EdgeNo is valid
|
||||
DstEdges[DstEdgeNo]->Count = N;
|
||||
Counter += N;
|
||||
if (!DstEdges[DstEdgeNo]->Dst.getNumDstEdges())
|
||||
DstEdges[DstEdgeNo]->Dst.Counter += N;
|
||||
}
|
||||
|
||||
/// sortDstEdges - Sort destination edges by block number, nop if already
|
||||
/// sorted. This is required for printing branch info in the correct order.
|
||||
void GCOVBlock::sortDstEdges() {
|
||||
if (!DstEdgesAreSorted) {
|
||||
SortDstEdgesFunctor SortEdges;
|
||||
std::stable_sort(DstEdges.begin(), DstEdges.end(), SortEdges);
|
||||
}
|
||||
}
|
||||
|
||||
/// collectLineCounts - Collect line counts. This must be used after
|
||||
/// reading .gcno and .gcda files.
|
||||
void GCOVBlock::collectLineCounts(FileInfo &FI) {
|
||||
for (uint32_t N : Lines)
|
||||
FI.addBlockLine(Parent.getFilename(), N, this);
|
||||
}
|
||||
|
||||
void GCOVBlock::print(raw_ostream &OS) const {
|
||||
OS << "Block : " << Number << " Counter : " << Counter << "\n";
|
||||
if (!SrcEdges.empty()) {
|
||||
OS << "\tSource Edges : ";
|
||||
for (const GCOVEdge *Edge : SrcEdges)
|
||||
OS << Edge->Src.Number << " (" << Edge->Count << "), ";
|
||||
OS << "\n";
|
||||
}
|
||||
if (!DstEdges.empty()) {
|
||||
OS << "\tDestination Edges : ";
|
||||
for (const GCOVEdge *Edge : DstEdges)
|
||||
OS << Edge->Dst.Number << " (" << Edge->Count << "), ";
|
||||
OS << "\n";
|
||||
}
|
||||
if (!Lines.empty()) {
|
||||
OS << "\tLines : ";
|
||||
for (uint32_t N : Lines)
|
||||
OS << (N) << ",";
|
||||
OS << "\n";
|
||||
}
|
||||
}
|
||||
|
||||
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
||||
/// dump - Dump GCOVBlock content to dbgs() for debugging purposes.
|
||||
LLVM_DUMP_METHOD void GCOVBlock::dump() const {
|
||||
print(dbgs());
|
||||
}
|
||||
#endif
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FileInfo implementation.
|
||||
|
||||
// Safe integer division, returns 0 if numerator is 0.
|
||||
static uint32_t safeDiv(uint64_t Numerator, uint64_t Divisor) {
|
||||
if (!Numerator)
|
||||
return 0;
|
||||
return Numerator / Divisor;
|
||||
}
|
||||
|
||||
// This custom division function mimics gcov's branch ouputs:
|
||||
// - Round to closest whole number
|
||||
// - Only output 0% or 100% if it's exactly that value
|
||||
static uint32_t branchDiv(uint64_t Numerator, uint64_t Divisor) {
|
||||
if (!Numerator)
|
||||
return 0;
|
||||
if (Numerator == Divisor)
|
||||
return 100;
|
||||
|
||||
uint8_t Res = (Numerator * 100 + Divisor / 2) / Divisor;
|
||||
if (Res == 0)
|
||||
return 1;
|
||||
if (Res == 100)
|
||||
return 99;
|
||||
return Res;
|
||||
}
|
||||
|
||||
namespace {
|
||||
struct formatBranchInfo {
|
||||
formatBranchInfo(const GCOV::Options &Options, uint64_t Count, uint64_t Total)
|
||||
: Options(Options), Count(Count), Total(Total) {}
|
||||
|
||||
void print(raw_ostream &OS) const {
|
||||
if (!Total)
|
||||
OS << "never executed";
|
||||
else if (Options.BranchCount)
|
||||
OS << "taken " << Count;
|
||||
else
|
||||
OS << "taken " << branchDiv(Count, Total) << "%";
|
||||
}
|
||||
|
||||
const GCOV::Options &Options;
|
||||
uint64_t Count;
|
||||
uint64_t Total;
|
||||
};
|
||||
|
||||
static raw_ostream &operator<<(raw_ostream &OS, const formatBranchInfo &FBI) {
|
||||
FBI.print(OS);
|
||||
return OS;
|
||||
}
|
||||
|
||||
class LineConsumer {
|
||||
std::unique_ptr<MemoryBuffer> Buffer;
|
||||
StringRef Remaining;
|
||||
|
||||
public:
|
||||
LineConsumer(StringRef Filename) {
|
||||
ErrorOr<std::unique_ptr<MemoryBuffer>> BufferOrErr =
|
||||
MemoryBuffer::getFileOrSTDIN(Filename);
|
||||
if (std::error_code EC = BufferOrErr.getError()) {
|
||||
errs() << Filename << ": " << EC.message() << "\n";
|
||||
Remaining = "";
|
||||
} else {
|
||||
Buffer = std::move(BufferOrErr.get());
|
||||
Remaining = Buffer->getBuffer();
|
||||
}
|
||||
}
|
||||
bool empty() { return Remaining.empty(); }
|
||||
void printNext(raw_ostream &OS, uint32_t LineNum) {
|
||||
StringRef Line;
|
||||
if (empty())
|
||||
Line = "/*EOF*/";
|
||||
else
|
||||
std::tie(Line, Remaining) = Remaining.split("\n");
|
||||
OS << format("%5u:", LineNum) << Line << "\n";
|
||||
}
|
||||
};
|
||||
} // end anonymous namespace
|
||||
|
||||
/// Convert a path to a gcov filename. If PreservePaths is true, this
|
||||
/// translates "/" to "#", ".." to "^", and drops ".", to match gcov.
|
||||
static std::string mangleCoveragePath(StringRef Filename, bool PreservePaths) {
|
||||
if (!PreservePaths)
|
||||
return sys::path::filename(Filename).str();
|
||||
|
||||
// This behaviour is defined by gcov in terms of text replacements, so it's
|
||||
// not likely to do anything useful on filesystems with different textual
|
||||
// conventions.
|
||||
llvm::SmallString<256> Result("");
|
||||
StringRef::iterator I, S, E;
|
||||
for (I = S = Filename.begin(), E = Filename.end(); I != E; ++I) {
|
||||
if (*I != '/')
|
||||
continue;
|
||||
|
||||
if (I - S == 1 && *S == '.') {
|
||||
// ".", the current directory, is skipped.
|
||||
} else if (I - S == 2 && *S == '.' && *(S + 1) == '.') {
|
||||
// "..", the parent directory, is replaced with "^".
|
||||
Result.append("^#");
|
||||
} else {
|
||||
if (S < I)
|
||||
// Leave other components intact,
|
||||
Result.append(S, I);
|
||||
// And separate with "#".
|
||||
Result.push_back('#');
|
||||
}
|
||||
S = I + 1;
|
||||
}
|
||||
|
||||
if (S < I)
|
||||
Result.append(S, I);
|
||||
return Result.str();
|
||||
}
|
||||
|
||||
std::string FileInfo::getCoveragePath(StringRef Filename,
|
||||
StringRef MainFilename) {
|
||||
if (Options.NoOutput)
|
||||
// This is probably a bug in gcov, but when -n is specified, paths aren't
|
||||
// mangled at all, and the -l and -p options are ignored. Here, we do the
|
||||
// same.
|
||||
return Filename;
|
||||
|
||||
std::string CoveragePath;
|
||||
if (Options.LongFileNames && !Filename.equals(MainFilename))
|
||||
CoveragePath =
|
||||
mangleCoveragePath(MainFilename, Options.PreservePaths) + "##";
|
||||
CoveragePath += mangleCoveragePath(Filename, Options.PreservePaths) + ".gcov";
|
||||
return CoveragePath;
|
||||
}
|
||||
|
||||
std::unique_ptr<raw_ostream>
|
||||
FileInfo::openCoveragePath(StringRef CoveragePath) {
|
||||
if (Options.NoOutput)
|
||||
return llvm::make_unique<raw_null_ostream>();
|
||||
|
||||
std::error_code EC;
|
||||
auto OS = llvm::make_unique<raw_fd_ostream>(CoveragePath, EC,
|
||||
sys::fs::F_Text);
|
||||
if (EC) {
|
||||
errs() << EC.message() << "\n";
|
||||
return llvm::make_unique<raw_null_ostream>();
|
||||
}
|
||||
return std::move(OS);
|
||||
}
|
||||
|
||||
/// print - Print source files with collected line count information.
|
||||
void FileInfo::print(raw_ostream &InfoOS, StringRef MainFilename,
|
||||
StringRef GCNOFile, StringRef GCDAFile) {
|
||||
SmallVector<StringRef, 4> Filenames;
|
||||
for (const auto &LI : LineInfo)
|
||||
Filenames.push_back(LI.first());
|
||||
std::sort(Filenames.begin(), Filenames.end());
|
||||
|
||||
for (StringRef Filename : Filenames) {
|
||||
auto AllLines = LineConsumer(Filename);
|
||||
|
||||
std::string CoveragePath = getCoveragePath(Filename, MainFilename);
|
||||
std::unique_ptr<raw_ostream> CovStream = openCoveragePath(CoveragePath);
|
||||
raw_ostream &CovOS = *CovStream;
|
||||
|
||||
CovOS << " -: 0:Source:" << Filename << "\n";
|
||||
CovOS << " -: 0:Graph:" << GCNOFile << "\n";
|
||||
CovOS << " -: 0:Data:" << GCDAFile << "\n";
|
||||
CovOS << " -: 0:Runs:" << RunCount << "\n";
|
||||
CovOS << " -: 0:Programs:" << ProgramCount << "\n";
|
||||
|
||||
const LineData &Line = LineInfo[Filename];
|
||||
GCOVCoverage FileCoverage(Filename);
|
||||
for (uint32_t LineIndex = 0; LineIndex < Line.LastLine || !AllLines.empty();
|
||||
++LineIndex) {
|
||||
if (Options.BranchInfo) {
|
||||
FunctionLines::const_iterator FuncsIt = Line.Functions.find(LineIndex);
|
||||
if (FuncsIt != Line.Functions.end())
|
||||
printFunctionSummary(CovOS, FuncsIt->second);
|
||||
}
|
||||
|
||||
BlockLines::const_iterator BlocksIt = Line.Blocks.find(LineIndex);
|
||||
if (BlocksIt == Line.Blocks.end()) {
|
||||
// No basic blocks are on this line. Not an executable line of code.
|
||||
CovOS << " -:";
|
||||
AllLines.printNext(CovOS, LineIndex + 1);
|
||||
} else {
|
||||
const BlockVector &Blocks = BlocksIt->second;
|
||||
|
||||
// Add up the block counts to form line counts.
|
||||
DenseMap<const GCOVFunction *, bool> LineExecs;
|
||||
uint64_t LineCount = 0;
|
||||
for (const GCOVBlock *Block : Blocks) {
|
||||
if (Options.AllBlocks) {
|
||||
// Only take the highest block count for that line.
|
||||
uint64_t BlockCount = Block->getCount();
|
||||
LineCount = LineCount > BlockCount ? LineCount : BlockCount;
|
||||
} else {
|
||||
// Sum up all of the block counts.
|
||||
LineCount += Block->getCount();
|
||||
}
|
||||
|
||||
if (Options.FuncCoverage) {
|
||||
// This is a slightly convoluted way to most accurately gather line
|
||||
// statistics for functions. Basically what is happening is that we
|
||||
// don't want to count a single line with multiple blocks more than
|
||||
// once. However, we also don't simply want to give the total line
|
||||
// count to every function that starts on the line. Thus, what is
|
||||
// happening here are two things:
|
||||
// 1) Ensure that the number of logical lines is only incremented
|
||||
// once per function.
|
||||
// 2) If there are multiple blocks on the same line, ensure that the
|
||||
// number of lines executed is incremented as long as at least
|
||||
// one of the blocks are executed.
|
||||
const GCOVFunction *Function = &Block->getParent();
|
||||
if (FuncCoverages.find(Function) == FuncCoverages.end()) {
|
||||
std::pair<const GCOVFunction *, GCOVCoverage> KeyValue(
|
||||
Function, GCOVCoverage(Function->getName()));
|
||||
FuncCoverages.insert(KeyValue);
|
||||
}
|
||||
GCOVCoverage &FuncCoverage = FuncCoverages.find(Function)->second;
|
||||
|
||||
if (LineExecs.find(Function) == LineExecs.end()) {
|
||||
if (Block->getCount()) {
|
||||
++FuncCoverage.LinesExec;
|
||||
LineExecs[Function] = true;
|
||||
} else {
|
||||
LineExecs[Function] = false;
|
||||
}
|
||||
++FuncCoverage.LogicalLines;
|
||||
} else if (!LineExecs[Function] && Block->getCount()) {
|
||||
++FuncCoverage.LinesExec;
|
||||
LineExecs[Function] = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (LineCount == 0)
|
||||
CovOS << " #####:";
|
||||
else {
|
||||
CovOS << format("%9" PRIu64 ":", LineCount);
|
||||
++FileCoverage.LinesExec;
|
||||
}
|
||||
++FileCoverage.LogicalLines;
|
||||
|
||||
AllLines.printNext(CovOS, LineIndex + 1);
|
||||
|
||||
uint32_t BlockNo = 0;
|
||||
uint32_t EdgeNo = 0;
|
||||
for (const GCOVBlock *Block : Blocks) {
|
||||
// Only print block and branch information at the end of the block.
|
||||
if (Block->getLastLine() != LineIndex + 1)
|
||||
continue;
|
||||
if (Options.AllBlocks)
|
||||
printBlockInfo(CovOS, *Block, LineIndex, BlockNo);
|
||||
if (Options.BranchInfo) {
|
||||
size_t NumEdges = Block->getNumDstEdges();
|
||||
if (NumEdges > 1)
|
||||
printBranchInfo(CovOS, *Block, FileCoverage, EdgeNo);
|
||||
else if (Options.UncondBranch && NumEdges == 1)
|
||||
printUncondBranchInfo(CovOS, EdgeNo,
|
||||
(*Block->dst_begin())->Count);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
FileCoverages.push_back(std::make_pair(CoveragePath, FileCoverage));
|
||||
}
|
||||
|
||||
// FIXME: There is no way to detect calls given current instrumentation.
|
||||
if (Options.FuncCoverage)
|
||||
printFuncCoverage(InfoOS);
|
||||
printFileCoverage(InfoOS);
|
||||
}
|
||||
|
||||
/// printFunctionSummary - Print function and block summary.
|
||||
void FileInfo::printFunctionSummary(raw_ostream &OS,
|
||||
const FunctionVector &Funcs) const {
|
||||
for (const GCOVFunction *Func : Funcs) {
|
||||
uint64_t EntryCount = Func->getEntryCount();
|
||||
uint32_t BlocksExec = 0;
|
||||
for (const GCOVBlock &Block : Func->blocks())
|
||||
if (Block.getNumDstEdges() && Block.getCount())
|
||||
++BlocksExec;
|
||||
|
||||
OS << "function " << Func->getName() << " called " << EntryCount
|
||||
<< " returned " << safeDiv(Func->getExitCount() * 100, EntryCount)
|
||||
<< "% blocks executed "
|
||||
<< safeDiv(BlocksExec * 100, Func->getNumBlocks() - 1) << "%\n";
|
||||
}
|
||||
}
|
||||
|
||||
/// printBlockInfo - Output counts for each block.
|
||||
void FileInfo::printBlockInfo(raw_ostream &OS, const GCOVBlock &Block,
|
||||
uint32_t LineIndex, uint32_t &BlockNo) const {
|
||||
if (Block.getCount() == 0)
|
||||
OS << " $$$$$:";
|
||||
else
|
||||
OS << format("%9" PRIu64 ":", Block.getCount());
|
||||
OS << format("%5u-block %2u\n", LineIndex + 1, BlockNo++);
|
||||
}
|
||||
|
||||
/// printBranchInfo - Print conditional branch probabilities.
|
||||
void FileInfo::printBranchInfo(raw_ostream &OS, const GCOVBlock &Block,
|
||||
GCOVCoverage &Coverage, uint32_t &EdgeNo) {
|
||||
SmallVector<uint64_t, 16> BranchCounts;
|
||||
uint64_t TotalCounts = 0;
|
||||
for (const GCOVEdge *Edge : Block.dsts()) {
|
||||
BranchCounts.push_back(Edge->Count);
|
||||
TotalCounts += Edge->Count;
|
||||
if (Block.getCount())
|
||||
++Coverage.BranchesExec;
|
||||
if (Edge->Count)
|
||||
++Coverage.BranchesTaken;
|
||||
++Coverage.Branches;
|
||||
|
||||
if (Options.FuncCoverage) {
|
||||
const GCOVFunction *Function = &Block.getParent();
|
||||
GCOVCoverage &FuncCoverage = FuncCoverages.find(Function)->second;
|
||||
if (Block.getCount())
|
||||
++FuncCoverage.BranchesExec;
|
||||
if (Edge->Count)
|
||||
++FuncCoverage.BranchesTaken;
|
||||
++FuncCoverage.Branches;
|
||||
}
|
||||
}
|
||||
|
||||
for (uint64_t N : BranchCounts)
|
||||
OS << format("branch %2u ", EdgeNo++)
|
||||
<< formatBranchInfo(Options, N, TotalCounts) << "\n";
|
||||
}
|
||||
|
||||
/// printUncondBranchInfo - Print unconditional branch probabilities.
|
||||
void FileInfo::printUncondBranchInfo(raw_ostream &OS, uint32_t &EdgeNo,
|
||||
uint64_t Count) const {
|
||||
OS << format("unconditional %2u ", EdgeNo++)
|
||||
<< formatBranchInfo(Options, Count, Count) << "\n";
|
||||
}
|
||||
|
||||
// printCoverage - Print generic coverage info used by both printFuncCoverage
|
||||
// and printFileCoverage.
|
||||
void FileInfo::printCoverage(raw_ostream &OS,
|
||||
const GCOVCoverage &Coverage) const {
|
||||
OS << format("Lines executed:%.2f%% of %u\n",
|
||||
double(Coverage.LinesExec) * 100 / Coverage.LogicalLines,
|
||||
Coverage.LogicalLines);
|
||||
if (Options.BranchInfo) {
|
||||
if (Coverage.Branches) {
|
||||
OS << format("Branches executed:%.2f%% of %u\n",
|
||||
double(Coverage.BranchesExec) * 100 / Coverage.Branches,
|
||||
Coverage.Branches);
|
||||
OS << format("Taken at least once:%.2f%% of %u\n",
|
||||
double(Coverage.BranchesTaken) * 100 / Coverage.Branches,
|
||||
Coverage.Branches);
|
||||
} else {
|
||||
OS << "No branches\n";
|
||||
}
|
||||
OS << "No calls\n"; // to be consistent with gcov
|
||||
}
|
||||
}
|
||||
|
||||
// printFuncCoverage - Print per-function coverage info.
|
||||
void FileInfo::printFuncCoverage(raw_ostream &OS) const {
|
||||
for (const auto &FC : FuncCoverages) {
|
||||
const GCOVCoverage &Coverage = FC.second;
|
||||
OS << "Function '" << Coverage.Name << "'\n";
|
||||
printCoverage(OS, Coverage);
|
||||
OS << "\n";
|
||||
}
|
||||
}
|
||||
|
||||
// printFileCoverage - Print per-file coverage info.
|
||||
void FileInfo::printFileCoverage(raw_ostream &OS) const {
|
||||
for (const auto &FC : FileCoverages) {
|
||||
const std::string &Filename = FC.first;
|
||||
const GCOVCoverage &Coverage = FC.second;
|
||||
OS << "File '" << Coverage.Name << "'\n";
|
||||
printCoverage(OS, Coverage);
|
||||
if (!Options.NoOutput)
|
||||
OS << Coverage.Name << ":creating '" << Filename << "'\n";
|
||||
OS << "\n";
|
||||
}
|
||||
}
|
460
src/plugin/GCOV.h
Normal file
460
src/plugin/GCOV.h
Normal file
@ -0,0 +1,460 @@
|
||||
//===- GCOV.h - LLVM coverage tool ------------------------------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This header provides the interface to read and write coverage files that
|
||||
// use 'gcov' format.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef LLVM_PROFILEDATA_GCOV_H
|
||||
#define LLVM_PROFILEDATA_GCOV_H
|
||||
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/MapVector.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/ADT/StringMap.h"
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
#include "llvm/ADT/iterator.h"
|
||||
#include "llvm/ADT/iterator_range.h"
|
||||
#include "llvm/Support/MemoryBuffer.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include <cassert>
|
||||
#include <cstddef>
|
||||
#include <cstdint>
|
||||
#include <memory>
|
||||
#include <string>
|
||||
#include <utility>
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class GCOVFunction;
|
||||
class GCOVBlock;
|
||||
class FileInfo;
|
||||
|
||||
namespace GCOV {
|
||||
|
||||
enum GCOVVersion { V402, V404, V704 };
|
||||
|
||||
/// \brief A struct for passing gcov options between functions.
|
||||
struct Options {
|
||||
Options(bool A, bool B, bool C, bool F, bool P, bool U, bool L, bool N)
|
||||
: AllBlocks(A), BranchInfo(B), BranchCount(C), FuncCoverage(F),
|
||||
PreservePaths(P), UncondBranch(U), LongFileNames(L), NoOutput(N) {}
|
||||
|
||||
bool AllBlocks;
|
||||
bool BranchInfo;
|
||||
bool BranchCount;
|
||||
bool FuncCoverage;
|
||||
bool PreservePaths;
|
||||
bool UncondBranch;
|
||||
bool LongFileNames;
|
||||
bool NoOutput;
|
||||
};
|
||||
|
||||
} // end namespace GCOV
|
||||
|
||||
/// GCOVBuffer - A wrapper around MemoryBuffer to provide GCOV specific
|
||||
/// read operations.
|
||||
class GCOVBuffer {
|
||||
public:
|
||||
GCOVBuffer(MemoryBuffer *B) : Buffer(B) {}
|
||||
|
||||
/// readGCNOFormat - Check GCNO signature is valid at the beginning of buffer.
|
||||
bool readGCNOFormat() {
|
||||
StringRef File = Buffer->getBuffer().slice(0, 4);
|
||||
if (File != "oncg") {
|
||||
errs() << "Unexpected file type: " << File << ".\n";
|
||||
return false;
|
||||
}
|
||||
Cursor = 4;
|
||||
return true;
|
||||
}
|
||||
|
||||
/// readGCDAFormat - Check GCDA signature is valid at the beginning of buffer.
|
||||
bool readGCDAFormat() {
|
||||
StringRef File = Buffer->getBuffer().slice(0, 4);
|
||||
if (File != "adcg") {
|
||||
errs() << "Unexpected file type: " << File << ".\n";
|
||||
return false;
|
||||
}
|
||||
Cursor = 4;
|
||||
return true;
|
||||
}
|
||||
|
||||
/// readGCOVVersion - Read GCOV version.
|
||||
bool readGCOVVersion(GCOV::GCOVVersion &Version) {
|
||||
StringRef VersionStr = Buffer->getBuffer().slice(Cursor, Cursor + 4);
|
||||
if (VersionStr == "*204") {
|
||||
Cursor += 4;
|
||||
Version = GCOV::V402;
|
||||
return true;
|
||||
}
|
||||
if (VersionStr == "*404") {
|
||||
Cursor += 4;
|
||||
Version = GCOV::V404;
|
||||
return true;
|
||||
}
|
||||
if (VersionStr == "*704") {
|
||||
Cursor += 4;
|
||||
Version = GCOV::V704;
|
||||
return true;
|
||||
}
|
||||
errs() << "Unexpected version: " << VersionStr << ".\n";
|
||||
return false;
|
||||
}
|
||||
|
||||
/// readFunctionTag - If cursor points to a function tag then increment the
|
||||
/// cursor and return true otherwise return false.
|
||||
bool readFunctionTag() {
|
||||
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
|
||||
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' ||
|
||||
Tag[3] != '\1') {
|
||||
return false;
|
||||
}
|
||||
Cursor += 4;
|
||||
return true;
|
||||
}
|
||||
|
||||
/// readBlockTag - If cursor points to a block tag then increment the
|
||||
/// cursor and return true otherwise return false.
|
||||
bool readBlockTag() {
|
||||
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
|
||||
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x41' ||
|
||||
Tag[3] != '\x01') {
|
||||
return false;
|
||||
}
|
||||
Cursor += 4;
|
||||
return true;
|
||||
}
|
||||
|
||||
/// readEdgeTag - If cursor points to an edge tag then increment the
|
||||
/// cursor and return true otherwise return false.
|
||||
bool readEdgeTag() {
|
||||
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
|
||||
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x43' ||
|
||||
Tag[3] != '\x01') {
|
||||
return false;
|
||||
}
|
||||
Cursor += 4;
|
||||
return true;
|
||||
}
|
||||
|
||||
/// readLineTag - If cursor points to a line tag then increment the
|
||||
/// cursor and return true otherwise return false.
|
||||
bool readLineTag() {
|
||||
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
|
||||
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x45' ||
|
||||
Tag[3] != '\x01') {
|
||||
return false;
|
||||
}
|
||||
Cursor += 4;
|
||||
return true;
|
||||
}
|
||||
|
||||
/// readArcTag - If cursor points to an gcda arc tag then increment the
|
||||
/// cursor and return true otherwise return false.
|
||||
bool readArcTag() {
|
||||
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
|
||||
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\xa1' ||
|
||||
Tag[3] != '\1') {
|
||||
return false;
|
||||
}
|
||||
Cursor += 4;
|
||||
return true;
|
||||
}
|
||||
|
||||
/// readObjectTag - If cursor points to an object summary tag then increment
|
||||
/// the cursor and return true otherwise return false.
|
||||
bool readObjectTag() {
|
||||
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
|
||||
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' ||
|
||||
Tag[3] != '\xa1') {
|
||||
return false;
|
||||
}
|
||||
Cursor += 4;
|
||||
return true;
|
||||
}
|
||||
|
||||
/// readProgramTag - If cursor points to a program summary tag then increment
|
||||
/// the cursor and return true otherwise return false.
|
||||
bool readProgramTag() {
|
||||
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
|
||||
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' ||
|
||||
Tag[3] != '\xa3') {
|
||||
return false;
|
||||
}
|
||||
Cursor += 4;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool readInt(uint32_t &Val) {
|
||||
if (Buffer->getBuffer().size() < Cursor + 4) {
|
||||
errs() << "Unexpected end of memory buffer: " << Cursor + 4 << ".\n";
|
||||
return false;
|
||||
}
|
||||
StringRef Str = Buffer->getBuffer().slice(Cursor, Cursor + 4);
|
||||
Cursor += 4;
|
||||
Val = *(const uint32_t *)(Str.data());
|
||||
return true;
|
||||
}
|
||||
|
||||
bool readInt64(uint64_t &Val) {
|
||||
uint32_t Lo, Hi;
|
||||
if (!readInt(Lo) || !readInt(Hi))
|
||||
return false;
|
||||
Val = ((uint64_t)Hi << 32) | Lo;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool readString(StringRef &Str) {
|
||||
uint32_t Len = 0;
|
||||
// Keep reading until we find a non-zero length. This emulates gcov's
|
||||
// behaviour, which appears to do the same.
|
||||
while (Len == 0)
|
||||
if (!readInt(Len))
|
||||
return false;
|
||||
Len *= 4;
|
||||
if (Buffer->getBuffer().size() < Cursor + Len) {
|
||||
errs() << "Unexpected end of memory buffer: " << Cursor + Len << ".\n";
|
||||
return false;
|
||||
}
|
||||
Str = Buffer->getBuffer().slice(Cursor, Cursor + Len).split('\0').first;
|
||||
Cursor += Len;
|
||||
return true;
|
||||
}
|
||||
|
||||
uint64_t getCursor() const { return Cursor; }
|
||||
void advanceCursor(uint32_t n) { Cursor += n * 4; }
|
||||
|
||||
private:
|
||||
MemoryBuffer *Buffer;
|
||||
uint64_t Cursor = 0;
|
||||
};
|
||||
|
||||
/// GCOVFile - Collects coverage information for one pair of coverage file
|
||||
/// (.gcno and .gcda).
|
||||
class GCOVFile {
|
||||
public:
|
||||
GCOVFile() = default;
|
||||
|
||||
bool readGCNO(GCOVBuffer &Buffer);
|
||||
bool readGCDA(GCOVBuffer &Buffer);
|
||||
uint32_t getChecksum() const { return Checksum; }
|
||||
void print(raw_ostream &OS) const;
|
||||
void dump() const;
|
||||
void collectLineCounts(FileInfo &FI);
|
||||
|
||||
private:
|
||||
bool GCNOInitialized = false;
|
||||
GCOV::GCOVVersion Version;
|
||||
uint32_t Checksum = 0;
|
||||
SmallVector<std::unique_ptr<GCOVFunction>, 16> Functions;
|
||||
uint32_t RunCount = 0;
|
||||
uint32_t ProgramCount = 0;
|
||||
};
|
||||
|
||||
/// GCOVEdge - Collects edge information.
|
||||
struct GCOVEdge {
|
||||
GCOVEdge(GCOVBlock &S, GCOVBlock &D) : Src(S), Dst(D) {}
|
||||
|
||||
GCOVBlock &Src;
|
||||
GCOVBlock &Dst;
|
||||
uint64_t Count = 0;
|
||||
};
|
||||
|
||||
/// GCOVFunction - Collects function information.
|
||||
class GCOVFunction {
|
||||
public:
|
||||
using BlockIterator = pointee_iterator<SmallVectorImpl<
|
||||
std::unique_ptr<GCOVBlock>>::const_iterator>;
|
||||
|
||||
GCOVFunction(GCOVFile &P) : Parent(P) {}
|
||||
|
||||
bool readGCNO(GCOVBuffer &Buffer, GCOV::GCOVVersion Version);
|
||||
bool readGCDA(GCOVBuffer &Buffer, GCOV::GCOVVersion Version);
|
||||
StringRef getName() const { return Name; }
|
||||
StringRef getFilename() const { return Filename; }
|
||||
size_t getNumBlocks() const { return Blocks.size(); }
|
||||
uint64_t getEntryCount() const;
|
||||
uint64_t getExitCount() const;
|
||||
|
||||
BlockIterator block_begin() const { return Blocks.begin(); }
|
||||
BlockIterator block_end() const { return Blocks.end(); }
|
||||
iterator_range<BlockIterator> blocks() const {
|
||||
return make_range(block_begin(), block_end());
|
||||
}
|
||||
|
||||
void print(raw_ostream &OS) const;
|
||||
void dump() const;
|
||||
void collectLineCounts(FileInfo &FI);
|
||||
|
||||
private:
|
||||
GCOVFile &Parent;
|
||||
uint32_t Ident = 0;
|
||||
uint32_t Checksum;
|
||||
uint32_t LineNumber = 0;
|
||||
StringRef Name;
|
||||
StringRef Filename;
|
||||
SmallVector<std::unique_ptr<GCOVBlock>, 16> Blocks;
|
||||
SmallVector<std::unique_ptr<GCOVEdge>, 16> Edges;
|
||||
};
|
||||
|
||||
/// GCOVBlock - Collects block information.
|
||||
class GCOVBlock {
|
||||
struct EdgeWeight {
|
||||
EdgeWeight(GCOVBlock *D) : Dst(D) {}
|
||||
|
||||
GCOVBlock *Dst;
|
||||
uint64_t Count = 0;
|
||||
};
|
||||
|
||||
struct SortDstEdgesFunctor {
|
||||
bool operator()(const GCOVEdge *E1, const GCOVEdge *E2) {
|
||||
return E1->Dst.Number < E2->Dst.Number;
|
||||
}
|
||||
};
|
||||
|
||||
public:
|
||||
using EdgeIterator = SmallVectorImpl<GCOVEdge *>::const_iterator;
|
||||
|
||||
GCOVBlock(GCOVFunction &P, uint32_t N) : Parent(P), Number(N) {}
|
||||
~GCOVBlock();
|
||||
|
||||
const GCOVFunction &getParent() const { return Parent; }
|
||||
void addLine(uint32_t N) { Lines.push_back(N); }
|
||||
uint32_t getLastLine() const { return Lines.back(); }
|
||||
void addCount(size_t DstEdgeNo, uint64_t N);
|
||||
uint64_t getCount() const { return Counter; }
|
||||
|
||||
void addSrcEdge(GCOVEdge *Edge) {
|
||||
assert(&Edge->Dst == this); // up to caller to ensure edge is valid
|
||||
SrcEdges.push_back(Edge);
|
||||
}
|
||||
|
||||
void addDstEdge(GCOVEdge *Edge) {
|
||||
assert(&Edge->Src == this); // up to caller to ensure edge is valid
|
||||
// Check if adding this edge causes list to become unsorted.
|
||||
if (DstEdges.size() && DstEdges.back()->Dst.Number > Edge->Dst.Number)
|
||||
DstEdgesAreSorted = false;
|
||||
DstEdges.push_back(Edge);
|
||||
}
|
||||
|
||||
size_t getNumSrcEdges() const { return SrcEdges.size(); }
|
||||
size_t getNumDstEdges() const { return DstEdges.size(); }
|
||||
void sortDstEdges();
|
||||
|
||||
EdgeIterator src_begin() const { return SrcEdges.begin(); }
|
||||
EdgeIterator src_end() const { return SrcEdges.end(); }
|
||||
iterator_range<EdgeIterator> srcs() const {
|
||||
return make_range(src_begin(), src_end());
|
||||
}
|
||||
|
||||
EdgeIterator dst_begin() const { return DstEdges.begin(); }
|
||||
EdgeIterator dst_end() const { return DstEdges.end(); }
|
||||
iterator_range<EdgeIterator> dsts() const {
|
||||
return make_range(dst_begin(), dst_end());
|
||||
}
|
||||
|
||||
void print(raw_ostream &OS) const;
|
||||
void dump() const;
|
||||
void collectLineCounts(FileInfo &FI);
|
||||
|
||||
private:
|
||||
GCOVFunction &Parent;
|
||||
uint32_t Number;
|
||||
uint64_t Counter = 0;
|
||||
bool DstEdgesAreSorted = true;
|
||||
SmallVector<GCOVEdge *, 16> SrcEdges;
|
||||
SmallVector<GCOVEdge *, 16> DstEdges;
|
||||
SmallVector<uint32_t, 16> Lines;
|
||||
};
|
||||
|
||||
class FileInfo {
|
||||
// It is unlikely--but possible--for multiple functions to be on the same
|
||||
// line.
|
||||
// Therefore this typedef allows LineData.Functions to store multiple
|
||||
// functions
|
||||
// per instance. This is rare, however, so optimize for the common case.
|
||||
using FunctionVector = SmallVector<const GCOVFunction *, 1>;
|
||||
using FunctionLines = DenseMap<uint32_t, FunctionVector>;
|
||||
using BlockVector = SmallVector<const GCOVBlock *, 4>;
|
||||
using BlockLines = DenseMap<uint32_t, BlockVector>;
|
||||
|
||||
struct LineData {
|
||||
LineData() = default;
|
||||
|
||||
BlockLines Blocks;
|
||||
FunctionLines Functions;
|
||||
uint32_t LastLine = 0;
|
||||
};
|
||||
|
||||
struct GCOVCoverage {
|
||||
GCOVCoverage(StringRef Name) : Name(Name) {}
|
||||
|
||||
StringRef Name;
|
||||
|
||||
uint32_t LogicalLines = 0;
|
||||
uint32_t LinesExec = 0;
|
||||
|
||||
uint32_t Branches = 0;
|
||||
uint32_t BranchesExec = 0;
|
||||
uint32_t BranchesTaken = 0;
|
||||
};
|
||||
|
||||
public:
|
||||
FileInfo(const GCOV::Options &Options) : Options(Options) {}
|
||||
|
||||
void addBlockLine(StringRef Filename, uint32_t Line, const GCOVBlock *Block) {
|
||||
if (Line > LineInfo[Filename].LastLine)
|
||||
LineInfo[Filename].LastLine = Line;
|
||||
LineInfo[Filename].Blocks[Line - 1].push_back(Block);
|
||||
}
|
||||
|
||||
void addFunctionLine(StringRef Filename, uint32_t Line,
|
||||
const GCOVFunction *Function) {
|
||||
if (Line > LineInfo[Filename].LastLine)
|
||||
LineInfo[Filename].LastLine = Line;
|
||||
LineInfo[Filename].Functions[Line - 1].push_back(Function);
|
||||
}
|
||||
|
||||
void setRunCount(uint32_t Runs) { RunCount = Runs; }
|
||||
void setProgramCount(uint32_t Programs) { ProgramCount = Programs; }
|
||||
void print(raw_ostream &OS, StringRef MainFilename, StringRef GCNOFile,
|
||||
StringRef GCDAFile);
|
||||
|
||||
private:
|
||||
std::string getCoveragePath(StringRef Filename, StringRef MainFilename);
|
||||
std::unique_ptr<raw_ostream> openCoveragePath(StringRef CoveragePath);
|
||||
void printFunctionSummary(raw_ostream &OS, const FunctionVector &Funcs) const;
|
||||
void printBlockInfo(raw_ostream &OS, const GCOVBlock &Block,
|
||||
uint32_t LineIndex, uint32_t &BlockNo) const;
|
||||
void printBranchInfo(raw_ostream &OS, const GCOVBlock &Block,
|
||||
GCOVCoverage &Coverage, uint32_t &EdgeNo);
|
||||
void printUncondBranchInfo(raw_ostream &OS, uint32_t &EdgeNo,
|
||||
uint64_t Count) const;
|
||||
|
||||
void printCoverage(raw_ostream &OS, const GCOVCoverage &Coverage) const;
|
||||
void printFuncCoverage(raw_ostream &OS) const;
|
||||
void printFileCoverage(raw_ostream &OS) const;
|
||||
|
||||
const GCOV::Options &Options;
|
||||
StringMap<LineData> LineInfo;
|
||||
uint32_t RunCount = 0;
|
||||
uint32_t ProgramCount = 0;
|
||||
|
||||
using FileCoverageList = SmallVector<std::pair<std::string, GCOVCoverage>, 4>;
|
||||
using FuncCoverageMap = MapVector<const GCOVFunction *, GCOVCoverage>;
|
||||
|
||||
FileCoverageList FileCoverages;
|
||||
FuncCoverageMap FuncCoverages;
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif // LLVM_SUPPORT_GCOV_H
|
92
src/plugin/cycle_estimate.cpp
Normal file
92
src/plugin/cycle_estimate.cpp
Normal file
@ -0,0 +1,92 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contributors:
|
||||
* eyck@minres.com - initial API and implementation
|
||||
******************************************************************************/
|
||||
|
||||
#include "iss/plugin/cycle_estimate.h"
|
||||
|
||||
#include <iss/arch_if.h>
|
||||
#include <util/logging.h>
|
||||
#include <fstream>
|
||||
|
||||
iss::plugin::cycle_estimate::cycle_estimate(std::string config_file_name)
|
||||
: arch_instr(nullptr)
|
||||
{
|
||||
if (config_file_name.length() > 0) {
|
||||
std::ifstream is(config_file_name);
|
||||
if (is.is_open()) {
|
||||
try {
|
||||
is >> root;
|
||||
} catch (Json::RuntimeError &e) {
|
||||
LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
|
||||
}
|
||||
} else {
|
||||
LOG(ERROR) << "Could not open input file " << config_file_name;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
iss::plugin::cycle_estimate::~cycle_estimate() {
|
||||
}
|
||||
|
||||
bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
|
||||
arch_instr = vm.get_arch()->get_instrumentation_if();
|
||||
if(!arch_instr) return false;
|
||||
const std::string core_name = arch_instr->core_type_name();
|
||||
Json::Value &val = root[core_name];
|
||||
if(!val.isNull() && val.isArray()){
|
||||
delays.reserve(val.size());
|
||||
for(auto it:val){
|
||||
auto name = it["name"];
|
||||
auto size = it["size"];
|
||||
auto delay = it["delay"];
|
||||
if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error");
|
||||
if(delay.isUInt()){
|
||||
delays.push_back(instr_desc{size.asUInt(), delay.asUInt(), 0});
|
||||
} else {
|
||||
delays.push_back(instr_desc{size.asUInt(), delay[0].asUInt(), delay[1].asUInt()});
|
||||
}
|
||||
}
|
||||
} else {
|
||||
LOG(ERROR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
|
||||
}
|
||||
return true;
|
||||
|
||||
}
|
||||
|
||||
void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
|
||||
assert(arch_instr && "No instrumentation interface available but callback executed");
|
||||
auto entry = delays[instr_info.instr_id];
|
||||
bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);
|
||||
uint32_t delay = taken ? entry.taken : entry.not_taken;
|
||||
if(delay>1) arch_instr->set_curr_instr_cycles(delay);
|
||||
}
|
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2023 MINRES Technologies GmbH
|
||||
* Copyright (C) 2017, MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -32,8 +32,8 @@
|
||||
* eyck@minres.com - initial API and implementation
|
||||
******************************************************************************/
|
||||
|
||||
#include "instruction_count.h"
|
||||
#include <iss/instrumentation_if.h>
|
||||
#include "iss/plugin/instruction_count.h"
|
||||
#include "iss/instrumentation_if.h"
|
||||
|
||||
#include <iss/arch_if.h>
|
||||
#include <util/logging.h>
|
||||
@ -46,10 +46,10 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
|
||||
try {
|
||||
is >> root;
|
||||
} catch (Json::RuntimeError &e) {
|
||||
LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
|
||||
LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
|
||||
}
|
||||
} else {
|
||||
LOG(ERR) << "Could not open input file " << config_file_name;
|
||||
LOG(ERROR) << "Could not open input file " << config_file_name;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -85,7 +85,7 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
|
||||
}
|
||||
rep_counts.resize(delays.size());
|
||||
} else {
|
||||
LOG(ERR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
|
||||
LOG(ERROR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
|
||||
}
|
||||
return true;
|
||||
}
|
@ -30,54 +30,26 @@
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
// clang-format off
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/encoderdecoder.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/debugger/target_adapter_if.h>
|
||||
#include <iss/iss.h>
|
||||
#include <iss/vm_types.h>
|
||||
#ifndef WIN32
|
||||
#include <iss/plugin/loader.h>
|
||||
#endif
|
||||
#include "core_complex.h"
|
||||
#include <iss/arch/tgc_mapper.h>
|
||||
#include <scc/report.h>
|
||||
#include <util/ities.h>
|
||||
#include "sysc/core_complex.h"
|
||||
#include "iss/arch/riscv_hart_m_p.h"
|
||||
#include "iss/arch/tgf_c.h"
|
||||
#include "iss/debugger/encoderdecoder.h"
|
||||
#include "iss/debugger/gdb_session.h"
|
||||
#include "iss/debugger/server.h"
|
||||
#include "iss/debugger/target_adapter_if.h"
|
||||
#include "iss/iss.h"
|
||||
#include "iss/vm_types.h"
|
||||
#include "scc/report.h"
|
||||
#include <iostream>
|
||||
#include <sstream>
|
||||
|
||||
#ifdef WITH_SCV
|
||||
#include <array>
|
||||
#include <iss/plugin/cycle_estimate.h>
|
||||
#include <iss/plugin/instruction_count.h>
|
||||
#include <iss/plugin/pctrace.h>
|
||||
|
||||
// clang-format on
|
||||
|
||||
#define STR(X) #X
|
||||
#define CREATE_CORE(CN) \
|
||||
if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend, gdb_port, hart_id); } else
|
||||
|
||||
#ifdef HAS_SCV
|
||||
#include <scv.h>
|
||||
#else
|
||||
#include <scv-tr.h>
|
||||
using namespace scv_tr;
|
||||
#endif
|
||||
|
||||
#ifndef CWR_SYSTEMC
|
||||
#define GET_PROP_VALUE(P) P.get_value()
|
||||
#else
|
||||
#define GET_PROP_VALUE(P) P.getValue()
|
||||
#endif
|
||||
|
||||
#ifdef _MSC_VER
|
||||
// not #if defined(_WIN32) || defined(_WIN64) because we have strncasecmp in mingw
|
||||
#define strncasecmp _strnicmp
|
||||
#define strcasecmp _stricmp
|
||||
#endif
|
||||
|
||||
namespace sysc {
|
||||
namespace tgfs {
|
||||
namespace SiFive {
|
||||
using namespace std;
|
||||
using namespace iss;
|
||||
using namespace logging;
|
||||
@ -85,51 +57,76 @@ using namespace sc_core;
|
||||
|
||||
namespace {
|
||||
iss::debugger::encoder_decoder encdec;
|
||||
|
||||
std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
|
||||
}
|
||||
|
||||
template<typename PLAT>
|
||||
class core_wrapper_t : public PLAT {
|
||||
using core_type = iss::arch::tgf_c;
|
||||
|
||||
namespace {
|
||||
|
||||
std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
|
||||
|
||||
std::array<const char*, 16> trap_str = { {
|
||||
"Instruction address misaligned",
|
||||
"Instruction access fault",
|
||||
"Illegal instruction",
|
||||
"Breakpoint",
|
||||
"Load address misaligned",
|
||||
"Load access fault",
|
||||
"Store/AMO address misaligned",
|
||||
"Store/AMO access fault",
|
||||
"Environment call from U-mode",
|
||||
"Environment call from S-mode",
|
||||
"Reserved",
|
||||
"Environment call from M-mode",
|
||||
"Instruction page fault",
|
||||
"Load page fault",
|
||||
"Reserved",
|
||||
"Store/AMO page fault"
|
||||
} };
|
||||
std::array<const char*, 12> irq_str = { {
|
||||
"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
|
||||
"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
|
||||
"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt" } };
|
||||
}
|
||||
|
||||
class core_wrapper : public iss::arch::riscv_hart_m_p<core_type> {
|
||||
public:
|
||||
using reg_t = typename arch::traits<typename PLAT::core>::reg_t;
|
||||
using phys_addr_t = typename arch::traits<typename PLAT::core>::phys_addr_t;
|
||||
using heart_state_t = typename PLAT::hart_state_type;
|
||||
core_wrapper_t(core_complex *owner)
|
||||
using base_type = arch::riscv_hart_m_p<core_type>;
|
||||
using phys_addr_t = typename arch::traits<core_type>::phys_addr_t;
|
||||
core_wrapper(core_complex *owner)
|
||||
: owner(owner) { }
|
||||
|
||||
uint32_t get_mode() { return this->reg.PRIV; }
|
||||
uint32_t get_mode() { return this->reg.machine_state; }
|
||||
|
||||
inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
|
||||
|
||||
inline bool get_interrupt_execution() { return this->interrupt_sim; }
|
||||
|
||||
heart_state_t &get_state() { return this->state; }
|
||||
base_type::hart_state<base_type::reg_t> &get_state() { return this->state; }
|
||||
|
||||
void notify_phase(iss::arch_if::exec_phase p) override {
|
||||
if (p == iss::arch_if::ISTART)
|
||||
owner->sync(this->instr_if.get_total_cycles());
|
||||
void notify_phase(exec_phase p) override {
|
||||
if (p == ISTART) owner->sync(this->reg.icount + cycle_offset);
|
||||
}
|
||||
|
||||
sync_type needed_sync() const override { return PRE_SYNC; }
|
||||
|
||||
void disass_output(uint64_t pc, const std::string instr) override {
|
||||
if (!owner->disass_output(pc, instr)) {
|
||||
if (INFO <= Log<Output2FILE<disass>>::reporting_level() && Output2FILE<disass>::stream()) {
|
||||
std::stringstream s;
|
||||
s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
|
||||
<< std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
|
||||
<< this->reg.icount + this->cycle_offset << "]";
|
||||
SCCDEBUG(owner->name())<<"disass: "
|
||||
s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0')
|
||||
<< std::setw(sizeof(reg_t) * 2) << (reg_t)state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
|
||||
Log<Output2FILE<disass>>().get(INFO, "disass")
|
||||
<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
|
||||
<< std::setfill(' ') << std::left << instr << s.str();
|
||||
}
|
||||
owner->disass_output(pc, instr);
|
||||
};
|
||||
|
||||
status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
|
||||
if (addr.access && access_type::DEBUG)
|
||||
return owner->read_mem_dbg(addr.val, length, data) ? Ok : Err;
|
||||
else {
|
||||
return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? Ok : Err;
|
||||
return owner->read_mem(addr.val, length, data, addr.access && access_type::FETCH) ? Ok : Err;
|
||||
}
|
||||
}
|
||||
|
||||
@ -149,7 +146,6 @@ public:
|
||||
}
|
||||
|
||||
status read_csr(unsigned addr, reg_t &val) override {
|
||||
#ifndef CWR_SYSTEMC
|
||||
if((addr==arch::time || addr==arch::timeh) && owner->mtime_o.get_interface(0)){
|
||||
uint64_t time_val;
|
||||
bool ret = owner->mtime_o->nb_peek(time_val);
|
||||
@ -160,44 +156,33 @@ public:
|
||||
val = static_cast<reg_t>(time_val >> 32);
|
||||
}
|
||||
return ret?Ok:Err;
|
||||
#else
|
||||
if((addr==arch::time || addr==arch::timeh)){
|
||||
uint64_t time_val = owner->mtime_i.read();
|
||||
if (addr == iss::arch::time) {
|
||||
val = static_cast<reg_t>(time_val);
|
||||
} else if (addr == iss::arch::timeh) {
|
||||
if (sizeof(reg_t) != 4) return iss::Err;
|
||||
val = static_cast<reg_t>(time_val >> 32);
|
||||
}
|
||||
return Ok;
|
||||
#endif
|
||||
} else {
|
||||
return PLAT::read_csr(addr, val);
|
||||
return base_type::read_csr(addr, val);
|
||||
}
|
||||
}
|
||||
|
||||
void wait_until(uint64_t flags) override {
|
||||
SCCDEBUG(owner->name()) << "Sleeping until interrupt";
|
||||
while(this->reg.pending_trap == 0 && (this->csr[arch::mip] & this->csr[arch::mie]) == 0) {
|
||||
sc_core::wait(wfi_evt);
|
||||
}
|
||||
PLAT::wait_until(flags);
|
||||
do {
|
||||
wait(wfi_evt);
|
||||
} while (this->reg.pending_trap == 0);
|
||||
base_type::wait_until(flags);
|
||||
}
|
||||
|
||||
void local_irq(short id, bool value) {
|
||||
reg_t mask = 0;
|
||||
base_type::reg_t mask = 0;
|
||||
switch (id) {
|
||||
case 3: // SW
|
||||
case 16: // SW
|
||||
mask = 1 << 3;
|
||||
break;
|
||||
case 7: // timer
|
||||
case 17: // timer
|
||||
mask = 1 << 7;
|
||||
break;
|
||||
case 11: // external
|
||||
case 18: // external
|
||||
mask = 1 << 11;
|
||||
break;
|
||||
default:
|
||||
if(id>15) mask = 1 << id;
|
||||
/* do nothing*/
|
||||
break;
|
||||
}
|
||||
if (value) {
|
||||
@ -206,8 +191,6 @@ public:
|
||||
} else
|
||||
this->csr[arch::mip] &= ~mask;
|
||||
this->check_interrupt();
|
||||
if(value)
|
||||
SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
|
||||
}
|
||||
|
||||
private:
|
||||
@ -245,109 +228,20 @@ int cmd_sysc(int argc, char *argv[], debugger::out_func of, debugger::data_func
|
||||
return Err;
|
||||
}
|
||||
|
||||
using cpu_ptr = std::unique_ptr<iss::arch_if>;
|
||||
using vm_ptr= std::unique_ptr<iss::vm_if>;
|
||||
|
||||
class core_wrapper {
|
||||
public:
|
||||
core_wrapper(core_complex *owner) : owner(owner) { }
|
||||
|
||||
void reset(uint64_t addr){vm->reset(addr);}
|
||||
inline void start(){vm->start();}
|
||||
inline std::pair<uint64_t, bool> load_file(std::string const& name){ return cpu->load_file(name);};
|
||||
|
||||
std::function<unsigned(void)> get_mode;
|
||||
std::function<uint64_t(void)> get_state;
|
||||
std::function<bool(void)> get_interrupt_execution;
|
||||
std::function<void(bool)> set_interrupt_execution;
|
||||
std::function<void(short, bool)> local_irq;
|
||||
|
||||
template<typename PLAT>
|
||||
std::tuple<cpu_ptr, vm_ptr> create_core(std::string const& backend, unsigned gdb_port, uint32_t hart_id){
|
||||
auto* lcpu = new core_wrapper_t<PLAT>(owner);
|
||||
lcpu->set_mhartid(hart_id);
|
||||
get_mode = [lcpu]() { return lcpu->get_mode(); };
|
||||
get_state = [lcpu]() { return lcpu->get_state().mstatus.backing.val; };
|
||||
get_interrupt_execution = [lcpu]() { return lcpu->get_interrupt_execution(); };
|
||||
set_interrupt_execution = [lcpu](bool b) { return lcpu->set_interrupt_execution(b); };
|
||||
local_irq = [lcpu](short s, bool b) { return lcpu->local_irq(s, b); };
|
||||
if(backend == "interp")
|
||||
return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(static_cast<typename PLAT::core*>(lcpu), gdb_port)}};
|
||||
#ifdef WITH_LLVM
|
||||
if(backend == "llvm")
|
||||
return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
|
||||
#endif
|
||||
#ifdef WITH_TCC
|
||||
if(backend == "tcc")
|
||||
s return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
|
||||
#endif
|
||||
return {nullptr, nullptr};
|
||||
}
|
||||
|
||||
void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id){
|
||||
CREATE_CORE(tgc_c)
|
||||
#ifdef CORE_TGC_B
|
||||
CREATE_CORE(tgc_b)
|
||||
#endif
|
||||
#ifdef CORE_TGC_D
|
||||
CREATE_CORE(tgc_d)
|
||||
#endif
|
||||
#ifdef CORE_TGC_D_XRB_MAC
|
||||
CREATE_CORE(tgc_d_xrb_mac)
|
||||
#endif
|
||||
#ifdef CORE_TGC_D_XRB_NN
|
||||
CREATE_CORE(tgc_d_xrb_nn)
|
||||
#endif
|
||||
{
|
||||
LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
|
||||
}
|
||||
auto *srv = debugger::server<debugger::gdb_session>::get();
|
||||
if (srv) tgt_adapter = srv->get_target();
|
||||
if (tgt_adapter)
|
||||
tgt_adapter->add_custom_command(
|
||||
{"sysc", [this](int argc, char *argv[], debugger::out_func of,
|
||||
debugger::data_func df) -> int { return cmd_sysc(argc, argv, of, df, tgt_adapter); },
|
||||
"SystemC sub-commands: break <time>, print_time"});
|
||||
|
||||
}
|
||||
|
||||
core_complex * const owner;
|
||||
vm_ptr vm{nullptr};
|
||||
cpu_ptr cpu{nullptr};
|
||||
iss::debugger::target_adapter_if *tgt_adapter{nullptr};
|
||||
};
|
||||
|
||||
struct core_trace {
|
||||
//! transaction recording database
|
||||
scv_tr_db *m_db{nullptr};
|
||||
//! blocking transaction recording stream handle
|
||||
scv_tr_stream *stream_handle{nullptr};
|
||||
//! transaction generator handle for blocking transactions
|
||||
scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data> *instr_tr_handle{nullptr};
|
||||
scv_tr_handle tr_handle;
|
||||
};
|
||||
|
||||
SC_HAS_PROCESS(core_complex);// NOLINT
|
||||
#ifndef CWR_SYSTEMC
|
||||
core_complex::core_complex(sc_module_name const& name)
|
||||
core_complex::core_complex(sc_module_name name)
|
||||
: sc_module(name)
|
||||
, fetch_lut(tlm_dmi_ext())
|
||||
, read_lut(tlm_dmi_ext())
|
||||
, write_lut(tlm_dmi_ext())
|
||||
{
|
||||
init();
|
||||
}
|
||||
, tgt_adapter(nullptr)
|
||||
#ifdef WITH_SCV
|
||||
, m_db(scv_tr_db::get_default_db())
|
||||
, stream_handle(nullptr)
|
||||
, instr_tr_handle(nullptr)
|
||||
, fetch_tr_handle(nullptr)
|
||||
#endif
|
||||
|
||||
void core_complex::init(){
|
||||
trc=new core_trace();
|
||||
ibus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
|
||||
auto lut_entry = fetch_lut.getEntry(start);
|
||||
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
|
||||
fetch_lut.removeEntry(lut_entry);
|
||||
}
|
||||
});
|
||||
dbus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
|
||||
{
|
||||
SC_HAS_PROCESS(core_complex);// NOLINT
|
||||
initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
|
||||
auto lut_entry = read_lut.getEntry(start);
|
||||
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
|
||||
read_lut.removeEntry(lut_entry);
|
||||
@ -359,201 +253,147 @@ void core_complex::init(){
|
||||
});
|
||||
|
||||
SC_THREAD(run);
|
||||
SC_METHOD(clk_cb);
|
||||
sensitive << clk_i;
|
||||
SC_METHOD(rst_cb);
|
||||
sensitive << rst_i;
|
||||
SC_METHOD(sw_irq_cb);
|
||||
sensitive << sw_irq_i;
|
||||
SC_METHOD(timer_irq_cb);
|
||||
sensitive << timer_irq_i;
|
||||
SC_METHOD(ext_irq_cb);
|
||||
sensitive << ext_irq_i;
|
||||
SC_METHOD(local_irq_cb);
|
||||
for(auto pin:local_irq_i)
|
||||
sensitive << pin;
|
||||
trc->m_db=scv_tr_db::get_default_db();
|
||||
|
||||
SC_METHOD(forward);
|
||||
#ifndef CWR_SYSTEMC
|
||||
sensitive<<clk_i;
|
||||
#else
|
||||
sensitive<<curr_clk;
|
||||
t2t.reset(new scc::tick2time{"t2t"});
|
||||
t2t->clk_i(clk_i);
|
||||
t2t->clk_o(curr_clk);
|
||||
#endif
|
||||
SC_METHOD(global_irq_cb);
|
||||
sensitive << global_irq_i;
|
||||
}
|
||||
|
||||
core_complex::~core_complex(){
|
||||
delete cpu;
|
||||
delete trc;
|
||||
for (auto *p : plugin_list)
|
||||
delete p;
|
||||
}
|
||||
core_complex::~core_complex() = default;
|
||||
|
||||
void core_complex::trace(sc_trace_file *trf) const {}
|
||||
|
||||
void core_complex::before_end_of_elaboration() {
|
||||
SCCDEBUG(SCMOD)<<"instantiating iss::arch::tgf with "<<GET_PROP_VALUE(backend)<<" backend";
|
||||
// cpu = scc::make_unique<core_wrapper>(this);
|
||||
cpu = new core_wrapper(this);
|
||||
cpu->create_cpu(GET_PROP_VALUE(core_type), GET_PROP_VALUE(backend), GET_PROP_VALUE(gdb_server_port), GET_PROP_VALUE(mhartid));
|
||||
sc_assert(cpu->vm!=nullptr);
|
||||
cpu->vm->setDisassEnabled(GET_PROP_VALUE(enable_disass) || trc->m_db != nullptr);
|
||||
if (GET_PROP_VALUE(plugins).length()) {
|
||||
auto p = util::split(GET_PROP_VALUE(plugins), ';');
|
||||
for (std::string const& opt_val : p) {
|
||||
std::string plugin_name=opt_val;
|
||||
std::string filename{"cycles.txt"};
|
||||
std::size_t found = opt_val.find('=');
|
||||
if (found != std::string::npos) {
|
||||
plugin_name = opt_val.substr(0, found);
|
||||
filename = opt_val.substr(found + 1, opt_val.size());
|
||||
}
|
||||
if (plugin_name == "ic") {
|
||||
auto *plugin = new iss::plugin::instruction_count(filename);
|
||||
cpu->vm->register_plugin(*plugin);
|
||||
plugin_list.push_back(plugin);
|
||||
} else if (plugin_name == "ce") {
|
||||
auto *plugin = new iss::plugin::cycle_estimate(filename);
|
||||
cpu->vm->register_plugin(*plugin);
|
||||
plugin_list.push_back(plugin);
|
||||
} else if (plugin_name == "pctrace") {
|
||||
auto *plugin = new iss::plugin::pctrace(filename);
|
||||
cpu->vm->register_plugin(*plugin);
|
||||
plugin_list.push_back(plugin);
|
||||
} else {
|
||||
#ifndef WIN32
|
||||
std::array<char const*, 1> a{{filename.c_str()}};
|
||||
iss::plugin::loader l(plugin_name, {{"initPlugin"}});
|
||||
auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
|
||||
if(plugin){
|
||||
cpu->vm->register_plugin(*plugin);
|
||||
plugin_list.push_back(plugin);
|
||||
} else
|
||||
using vm_ptr= std::unique_ptr<iss::vm_if>;
|
||||
vm_ptr create_cpu(core_wrapper* cpu, std::string const& backend, unsigned gdb_port){
|
||||
if(backend == "interp")
|
||||
return vm_ptr{iss::interp::create<core_type>(cpu, gdb_port)};
|
||||
#ifdef WITH_LLVM
|
||||
if(backend == "llvm")
|
||||
return vm_ptr{iss::llvm::create(lcpu, gdb_port)};
|
||||
#endif
|
||||
SCCERR(SCMOD) << "Unknown plugin '" << plugin_name << "' or plugin not found";
|
||||
}
|
||||
}
|
||||
}
|
||||
if(backend == "tcc")
|
||||
return vm_ptr{iss::tcc::create<core_type>(cpu, gdb_port)};
|
||||
return {nullptr};
|
||||
}
|
||||
|
||||
void core_complex::before_end_of_elaboration() {
|
||||
SCCDEBUG(SCMOD)<<"instantiating iss::arch::tgf with "<<backend.get_value()<<" backend";
|
||||
cpu = scc::make_unique<core_wrapper>(this);
|
||||
cpu->set_mhartid(mhartid.get_value());
|
||||
|
||||
vm = create_cpu(cpu.get(), backend.get_value(), gdb_server_port.get_value());
|
||||
#ifdef WITH_SCV
|
||||
vm->setDisassEnabled(enable_disass.get_value() || m_db != nullptr);
|
||||
#else
|
||||
vm->setDisassEnabled(enable_disass.get_value());
|
||||
#endif
|
||||
auto *srv = debugger::server<debugger::gdb_session>::get();
|
||||
if (srv) tgt_adapter = srv->get_target();
|
||||
if (tgt_adapter)
|
||||
tgt_adapter->add_custom_command(
|
||||
{"sysc", [this](int argc, char *argv[], debugger::out_func of,
|
||||
debugger::data_func df) -> int { return cmd_sysc(argc, argv, of, df, tgt_adapter); },
|
||||
"SystemC sub-commands: break <time>, print_time"});
|
||||
}
|
||||
|
||||
void core_complex::start_of_simulation() {
|
||||
// quantum_keeper.reset();
|
||||
if (GET_PROP_VALUE(elf_file).size() > 0) {
|
||||
istringstream is(GET_PROP_VALUE(elf_file));
|
||||
quantum_keeper.reset();
|
||||
if (elf_file.get_value().size() > 0) {
|
||||
istringstream is(elf_file.get_value());
|
||||
string s;
|
||||
while (getline(is, s, ',')) {
|
||||
std::pair<uint64_t, bool> start_addr = cpu->load_file(s);
|
||||
#ifndef CWR_SYSTEMC
|
||||
if (reset_address.is_default_value() && start_addr.second == true)
|
||||
reset_address.set_value(start_addr.first);
|
||||
#else
|
||||
if (start_addr.second == true)
|
||||
reset_address=start_addr.first;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
if (trc->m_db != nullptr && trc->stream_handle == nullptr) {
|
||||
#ifdef WITH_SCV
|
||||
if (m_db != nullptr && stream_handle == nullptr) {
|
||||
string basename(this->name());
|
||||
trc->stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", trc->m_db);
|
||||
trc->instr_tr_handle = new scv_tr_generator<>("execute", *trc->stream_handle);
|
||||
stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", m_db);
|
||||
instr_tr_handle = new scv_tr_generator<>("execute", *stream_handle);
|
||||
fetch_tr_handle = new scv_tr_generator<uint64_t>("fetch", *stream_handle);
|
||||
}
|
||||
}
|
||||
|
||||
bool core_complex::disass_output(uint64_t pc, const std::string instr_str) {
|
||||
if (trc->m_db == nullptr) return false;
|
||||
if (trc->tr_handle.is_active()) trc->tr_handle.end_transaction();
|
||||
trc->tr_handle = trc->instr_tr_handle->begin_transaction();
|
||||
trc->tr_handle.record_attribute("PC", pc);
|
||||
trc->tr_handle.record_attribute("INSTR", instr_str);
|
||||
trc->tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
|
||||
trc->tr_handle.record_attribute("MSTATUS", cpu->get_state());
|
||||
trc->tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
|
||||
return true;
|
||||
}
|
||||
|
||||
void core_complex::forward() {
|
||||
#ifndef CWR_SYSTEMC
|
||||
set_clock_period(clk_i.read());
|
||||
#else
|
||||
set_clock_period(curr_clk.read());
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void core_complex::set_clock_period(sc_core::sc_time period) {
|
||||
curr_clk = period;
|
||||
if (period == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
|
||||
void core_complex::disass_output(uint64_t pc, const std::string instr_str) {
|
||||
#ifdef WITH_SCV
|
||||
if (m_db == nullptr) return;
|
||||
if (tr_handle.is_active()) tr_handle.end_transaction();
|
||||
tr_handle = instr_tr_handle->begin_transaction();
|
||||
tr_handle.record_attribute("PC", pc);
|
||||
tr_handle.record_attribute("INSTR", instr_str);
|
||||
tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
|
||||
tr_handle.record_attribute("MSTATUS", cpu->get_state().mstatus.backing.val);
|
||||
tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
|
||||
#endif
|
||||
}
|
||||
|
||||
void core_complex::clk_cb() {
|
||||
curr_clk = clk_i.read();
|
||||
if (curr_clk == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
|
||||
}
|
||||
|
||||
void core_complex::rst_cb() {
|
||||
if (rst_i.read()) cpu->set_interrupt_execution(true);
|
||||
}
|
||||
|
||||
void core_complex::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
|
||||
void core_complex::sw_irq_cb() { cpu->local_irq(16, sw_irq_i.read()); }
|
||||
|
||||
void core_complex::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
|
||||
void core_complex::timer_irq_cb() { cpu->local_irq(17, timer_irq_i.read()); }
|
||||
|
||||
void core_complex::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
|
||||
|
||||
void core_complex::local_irq_cb() {
|
||||
for(auto i=0U; i<local_irq_i.size(); ++i) {
|
||||
if(local_irq_i[i].event()) {
|
||||
cpu->local_irq(16+i, local_irq_i[i].read());
|
||||
}
|
||||
}
|
||||
}
|
||||
void core_complex::global_irq_cb() { cpu->local_irq(18, global_irq_i.read()); }
|
||||
|
||||
void core_complex::run() {
|
||||
wait(SC_ZERO_TIME); // separate from elaboration phase
|
||||
do {
|
||||
wait(SC_ZERO_TIME);
|
||||
if (rst_i.read()) {
|
||||
cpu->reset(GET_PROP_VALUE(reset_address));
|
||||
cpu->reset(reset_address.get_value());
|
||||
wait(rst_i.negedge_event());
|
||||
}
|
||||
while (curr_clk.read() == SC_ZERO_TIME) {
|
||||
wait(curr_clk.value_changed_event());
|
||||
while (clk_i.read() == SC_ZERO_TIME) {
|
||||
wait(clk_i.value_changed_event());
|
||||
}
|
||||
quantum_keeper.reset();
|
||||
cpu->set_interrupt_execution(false);
|
||||
cpu->start();
|
||||
vm->start();
|
||||
} while (cpu->get_interrupt_execution());
|
||||
sc_stop();
|
||||
}
|
||||
|
||||
bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch) {
|
||||
auto& dmi_lut = is_fetch?fetch_lut:read_lut;
|
||||
auto lut_entry = dmi_lut.getEntry(addr);
|
||||
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
|
||||
auto lut_entry = read_lut.getEntry(addr);
|
||||
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
|
||||
addr + length <= lut_entry.get_end_address() + 1) {
|
||||
auto offset = addr - lut_entry.get_start_address();
|
||||
std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
|
||||
quantum_keeper.inc(lut_entry.get_read_latency());
|
||||
return true;
|
||||
} else {
|
||||
auto& sckt = is_fetch? ibus : dbus;
|
||||
tlm::tlm_generic_payload gp;
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(addr);
|
||||
gp.set_data_ptr(data);
|
||||
gp.set_data_length(length);
|
||||
gp.set_streaming_width(length);
|
||||
sc_time delay=quantum_keeper.get_local_time();
|
||||
if (trc->m_db != nullptr && trc->tr_handle.is_valid()) {
|
||||
if (is_fetch && trc->tr_handle.is_active()) {
|
||||
trc->tr_handle.end_transaction();
|
||||
sc_time delay{quantum_keeper.get_local_time()};
|
||||
#ifdef WITH_SCV
|
||||
if (m_db != nullptr && tr_handle.is_valid()) {
|
||||
if (is_fetch && tr_handle.is_active()) {
|
||||
tr_handle.end_transaction();
|
||||
}
|
||||
auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
|
||||
auto preExt = new tlm::scc::scv4tlm::tlm_recording_extension(tr_handle, this);
|
||||
gp.set_extension(preExt);
|
||||
}
|
||||
sckt->b_transport(gp, delay);
|
||||
auto incr = delay-quantum_keeper.get_local_time();
|
||||
if(is_fetch)
|
||||
ibus_inc+=incr;
|
||||
else
|
||||
dbus_inc+=incr;
|
||||
SCCTRACE(this->name()) << "[local time: "<<delay<<"]: finish read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
|
||||
#endif
|
||||
initiator->b_transport(gp, delay);
|
||||
SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : " << data;
|
||||
if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
|
||||
return false;
|
||||
}
|
||||
@ -561,10 +401,13 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(addr);
|
||||
tlm_dmi_ext dmi_data;
|
||||
if (sckt->get_direct_mem_ptr(gp, dmi_data)) {
|
||||
if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
|
||||
if (dmi_data.is_read_allowed())
|
||||
dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(),
|
||||
read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
|
||||
dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
|
||||
if (dmi_data.is_write_allowed())
|
||||
write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
|
||||
dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
|
||||
}
|
||||
}
|
||||
return true;
|
||||
@ -588,14 +431,16 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
|
||||
gp.set_data_ptr(write_buf.data());
|
||||
gp.set_data_length(length);
|
||||
gp.set_streaming_width(length);
|
||||
sc_time delay=quantum_keeper.get_local_time();
|
||||
if (trc->m_db != nullptr && trc->tr_handle.is_valid()) {
|
||||
auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
|
||||
sc_time delay{quantum_keeper.get_local_time()};
|
||||
#ifdef WITH_SCV
|
||||
if (m_db != nullptr && tr_handle.is_valid()) {
|
||||
auto preExt = new tlm::scc::scv4tlm::tlm_recording_extension(tr_handle, this);
|
||||
gp.set_extension(preExt);
|
||||
}
|
||||
dbus->b_transport(gp, delay);
|
||||
dbus_inc+=delay-quantum_keeper.get_local_time();
|
||||
SCCTRACE() << "[local time: "<<delay<<"]: finish write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
|
||||
#endif
|
||||
initiator->b_transport(gp, delay);
|
||||
quantum_keeper.set(delay);
|
||||
SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : " << data;
|
||||
if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
|
||||
return false;
|
||||
}
|
||||
@ -603,7 +448,10 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(addr);
|
||||
tlm_dmi_ext dmi_data;
|
||||
if (dbus->get_direct_mem_ptr(gp, dmi_data)) {
|
||||
if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
|
||||
if (dmi_data.is_read_allowed())
|
||||
read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
|
||||
dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
|
||||
if (dmi_data.is_write_allowed())
|
||||
write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
|
||||
dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
|
||||
@ -614,25 +462,44 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
|
||||
}
|
||||
|
||||
bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data) {
|
||||
tlm::tlm_generic_payload gp;
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(addr);
|
||||
gp.set_data_ptr(data);
|
||||
gp.set_data_length(length);
|
||||
gp.set_streaming_width(length);
|
||||
return dbus->transport_dbg(gp) == length;
|
||||
auto lut_entry = read_lut.getEntry(addr);
|
||||
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
|
||||
addr + length <= lut_entry.get_end_address() + 1) {
|
||||
auto offset = addr - lut_entry.get_start_address();
|
||||
std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
|
||||
quantum_keeper.inc(lut_entry.get_read_latency());
|
||||
return true;
|
||||
} else {
|
||||
tlm::tlm_generic_payload gp;
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(addr);
|
||||
gp.set_data_ptr(data);
|
||||
gp.set_data_length(length);
|
||||
gp.set_streaming_width(length);
|
||||
return initiator->transport_dbg(gp) == length;
|
||||
}
|
||||
}
|
||||
|
||||
bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data) {
|
||||
write_buf.resize(length);
|
||||
std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
|
||||
tlm::tlm_generic_payload gp;
|
||||
gp.set_command(tlm::TLM_WRITE_COMMAND);
|
||||
gp.set_address(addr);
|
||||
gp.set_data_ptr(write_buf.data());
|
||||
gp.set_data_length(length);
|
||||
gp.set_streaming_width(length);
|
||||
return dbus->transport_dbg(gp) == length;
|
||||
auto lut_entry = write_lut.getEntry(addr);
|
||||
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
|
||||
addr + length <= lut_entry.get_end_address() + 1) {
|
||||
auto offset = addr - lut_entry.get_start_address();
|
||||
std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
|
||||
quantum_keeper.inc(lut_entry.get_read_latency());
|
||||
return true;
|
||||
} else {
|
||||
write_buf.resize(length);
|
||||
std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
|
||||
tlm::tlm_generic_payload gp;
|
||||
gp.set_command(tlm::TLM_WRITE_COMMAND);
|
||||
gp.set_address(addr);
|
||||
gp.set_data_ptr(write_buf.data());
|
||||
gp.set_data_length(length);
|
||||
gp.set_streaming_width(length);
|
||||
return initiator->transport_dbg(gp) == length;
|
||||
}
|
||||
}
|
||||
|
||||
} /* namespace SiFive */
|
||||
} /* namespace sysc */
|
||||
|
@ -1,33 +0,0 @@
|
||||
/*
|
||||
* register_tgc_c.cpp
|
||||
*
|
||||
* Created on: Jul 5, 2023
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
#include <iss/factory.h>
|
||||
#include <iss/arch/tgc_c.h>
|
||||
#include <iss/arch/riscv_hart_m_p.h>
|
||||
#include <iss/arch/riscv_hart_mu_p.h>
|
||||
#include "sc_core_adapter.h"
|
||||
#include "core_complex.h"
|
||||
|
||||
namespace iss {
|
||||
namespace {
|
||||
volatile std::array<bool, 2> dummy = {
|
||||
core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
arch::tgc_c* lcpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
|
||||
return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
|
||||
}),
|
||||
core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
arch::tgc_c* lcpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
|
||||
return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
|
||||
})
|
||||
};
|
||||
}
|
||||
}
|
@ -1,148 +0,0 @@
|
||||
/*
|
||||
* sc_core_adapter.h
|
||||
*
|
||||
* Created on: Jul 5, 2023
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#ifndef _SYSC_SC_CORE_ADAPTER_H_
|
||||
#define _SYSC_SC_CORE_ADAPTER_H_
|
||||
|
||||
|
||||
#include <scc/report.h>
|
||||
#include <util/ities.h>
|
||||
#include "core_complex.h"
|
||||
#include <iss/iss.h>
|
||||
#include <iss/vm_types.h>
|
||||
#include <iostream>
|
||||
|
||||
|
||||
template<typename PLAT>
|
||||
class sc_core_adapter : public PLAT {
|
||||
public:
|
||||
using reg_t = typename iss::arch::traits<typename PLAT::core>::reg_t;
|
||||
using phys_addr_t = typename iss::arch::traits<typename PLAT::core>::phys_addr_t;
|
||||
using heart_state_t = typename PLAT::hart_state_type;
|
||||
sc_core_adapter(sysc::tgfs::core_complex *owner)
|
||||
: owner(owner) { }
|
||||
|
||||
uint32_t get_mode() { return this->reg.PRIV; }
|
||||
|
||||
inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
|
||||
|
||||
inline bool get_interrupt_execution() { return this->interrupt_sim; }
|
||||
|
||||
heart_state_t &get_state() { return this->state; }
|
||||
|
||||
void notify_phase(iss::arch_if::exec_phase p) override {
|
||||
if (p == iss::arch_if::ISTART)
|
||||
owner->sync(this->instr_if.get_total_cycles());
|
||||
}
|
||||
|
||||
iss::sync_type needed_sync() const override { return iss::PRE_SYNC; }
|
||||
|
||||
void disass_output(uint64_t pc, const std::string instr) override {
|
||||
static constexpr std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
|
||||
if (!owner->disass_output(pc, instr)) {
|
||||
std::stringstream s;
|
||||
s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
|
||||
<< std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
|
||||
<< this->reg.icount + this->cycle_offset << "]";
|
||||
SCCDEBUG(owner->name())<<"disass: "
|
||||
<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
|
||||
<< std::setfill(' ') << std::left << instr << s.str();
|
||||
}
|
||||
};
|
||||
|
||||
iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
|
||||
if (addr.access && iss::access_type::DEBUG)
|
||||
return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
|
||||
else {
|
||||
return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? iss::Ok : iss::Err;
|
||||
}
|
||||
}
|
||||
|
||||
iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) override {
|
||||
if (addr.access && iss::access_type::DEBUG)
|
||||
return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
|
||||
else {
|
||||
auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
|
||||
// clear MTIP on mtimecmp write
|
||||
if (addr.val == 0x2004000) {
|
||||
reg_t val;
|
||||
this->read_csr(iss::arch::mip, val);
|
||||
if (val & (1ULL << 7)) this->write_csr(iss::arch::mip, val & ~(1ULL << 7));
|
||||
}
|
||||
return res;
|
||||
}
|
||||
}
|
||||
|
||||
iss::status read_csr(unsigned addr, reg_t &val) override {
|
||||
#ifndef CWR_SYSTEMC
|
||||
if((addr==iss::arch::time || addr==iss::arch::timeh) && owner->mtime_o.get_interface(0)){
|
||||
uint64_t time_val;
|
||||
bool ret = owner->mtime_o->nb_peek(time_val);
|
||||
if (addr == iss::arch::time) {
|
||||
val = static_cast<reg_t>(time_val);
|
||||
} else if (addr == iss::arch::timeh) {
|
||||
if (sizeof(reg_t) != 4) return iss::Err;
|
||||
val = static_cast<reg_t>(time_val >> 32);
|
||||
}
|
||||
return ret?Ok:Err;
|
||||
#else
|
||||
if((addr==iss::arch::time || addr==iss::arch::timeh)){
|
||||
uint64_t time_val = owner->mtime_i.read();
|
||||
if (addr == iss::arch::time) {
|
||||
val = static_cast<reg_t>(time_val);
|
||||
} else if (addr == iss::arch::timeh) {
|
||||
if (sizeof(reg_t) != 4) return iss::Err;
|
||||
val = static_cast<reg_t>(time_val >> 32);
|
||||
}
|
||||
return iss::Ok;
|
||||
#endif
|
||||
} else {
|
||||
return PLAT::read_csr(addr, val);
|
||||
}
|
||||
}
|
||||
|
||||
void wait_until(uint64_t flags) override {
|
||||
SCCDEBUG(owner->name()) << "Sleeping until interrupt";
|
||||
while(this->reg.pending_trap == 0 && (this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
|
||||
sc_core::wait(wfi_evt);
|
||||
}
|
||||
PLAT::wait_until(flags);
|
||||
}
|
||||
|
||||
void local_irq(short id, bool value) {
|
||||
reg_t mask = 0;
|
||||
switch (id) {
|
||||
case 3: // SW
|
||||
mask = 1 << 3;
|
||||
break;
|
||||
case 7: // timer
|
||||
mask = 1 << 7;
|
||||
break;
|
||||
case 11: // external
|
||||
mask = 1 << 11;
|
||||
break;
|
||||
default:
|
||||
if(id>15) mask = 1 << id;
|
||||
break;
|
||||
}
|
||||
if (value) {
|
||||
this->csr[iss::arch::mip] |= mask;
|
||||
wfi_evt.notify();
|
||||
} else
|
||||
this->csr[iss::arch::mip] &= ~mask;
|
||||
this->check_interrupt();
|
||||
if(value)
|
||||
SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
|
||||
}
|
||||
|
||||
private:
|
||||
sysc::tgfs::core_complex *const owner;
|
||||
sc_event wfi_evt;
|
||||
};
|
||||
|
||||
|
||||
#endif /* _SYSC_SC_CORE_ADAPTER_H_ */
|
File diff suppressed because it is too large
Load Diff
2072
src/vm/interp/vm_tgf_b.cpp
Normal file
2072
src/vm/interp/vm_tgf_b.cpp
Normal file
File diff suppressed because it is too large
Load Diff
3323
src/vm/interp/vm_tgf_c.cpp
Normal file
3323
src/vm/interp/vm_tgf_c.cpp
Normal file
File diff suppressed because it is too large
Load Diff
2582
src/vm/llvm/vm_tgf_b.cpp
Normal file
2582
src/vm/llvm/vm_tgf_b.cpp
Normal file
File diff suppressed because it is too large
Load Diff
@ -30,7 +30,7 @@
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include <iss/arch/tgc_c.h>
|
||||
#include <iss/arch/tgf_c.h>
|
||||
#include <iss/arch/riscv_hart_m_p.h>
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
@ -52,7 +52,7 @@ namespace fp_impl {
|
||||
void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
|
||||
}
|
||||
|
||||
namespace tgc_c {
|
||||
namespace tgf_c {
|
||||
using namespace ::llvm;
|
||||
using namespace iss::arch;
|
||||
using namespace iss::debugger;
|
||||
@ -4151,11 +4151,11 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *b
|
||||
bb, this->trap_blk, 1);
|
||||
}
|
||||
|
||||
} // namespace tgc_c
|
||||
} // namespace tgf_c
|
||||
|
||||
template <>
|
||||
std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
|
||||
auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
|
||||
std::unique_ptr<vm_if> create<arch::tgf_c>(arch::tgf_c *core, unsigned short port, bool dump) {
|
||||
auto ret = new tgf_c::vm_impl<arch::tgf_c>(*core, dump);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||
return std::unique_ptr<vm_if>(ret);
|
||||
}
|
File diff suppressed because it is too large
Load Diff
2086
src/vm/tcc/vm_tgf_b.cpp
Normal file
2086
src/vm/tcc/vm_tgf_b.cpp
Normal file
File diff suppressed because it is too large
Load Diff
3278
src/vm/tcc/vm_tgf_c.cpp
Normal file
3278
src/vm/tcc/vm_tgf_c.cpp
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user