Merge remote-tracking branch 'origin/develop'

this relates to https://github.com/Minres/DBT-RISE-RISCV/issues/8 :
Debugger loses control when trap vector fetch fails

and https://github.com/Minres/DBT-RISE-RISCV/issues/7 : Two debugger
single-steps are required at reset vector

CMakeLists.txt

@@ -20,6 +20,7 @@ set(LIB_SOURCES
     src/iss/arch/tgc5c.cpp
     src/vm/interp/vm_tgc5c.cpp
     src/vm/fp_functions.cpp
+    src/iss/debugger/csr_names.cpp
     src/iss/semihosting/semihosting.cpp
 )
 
@@ -261,3 +262,9 @@ if(TARGET scc-sysc)
         INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
     )
 endif()
+
+project(elfio-test)
+find_package(Boost COMPONENTS program_options thread REQUIRED)
+
+add_executable(${PROJECT_NAME} src/elfio.cpp)
+target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)

gen_input/templates/CORENAME_sysc.cpp.gtl

@@ -45,17 +45,17 @@ namespace interp {
 using namespace sysc;
 volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         }),
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%}%>
@@ -66,17 +66,17 @@ namespace llvm {
 using namespace sysc;
 volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         }),
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%}%>
@@ -88,17 +88,17 @@ namespace tcc {
 using namespace sysc;
 volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         }),
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%}%>
@@ -110,17 +110,17 @@ namespace asmjit {
 using namespace sysc;
 volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         }),
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%}%>

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -263,6 +263,7 @@ void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
     cmp(cc, current_trap_state, 0);
     cc.jne(jh.trap_entry);
     cc.inc(get_ptr_for(jh, traits::ICOUNT));
+    cc.inc(get_ptr_for(jh, traits::CYCLE));
 }
 template <typename ARCH>
 void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
@@ -308,6 +309,7 @@ inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t
     auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
     mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
     mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);
+    cc.jmp(jh.trap_entry);
 }
 template <typename ARCH>
 template <typename T, typename>

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -257,10 +257,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
     while(!this->core.should_stop() &&
             !(is_icount_limit_enabled(cond) && icount >= count_limit) &&
             !(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
-        fetch_count++;
+        if(this->debugging_enabled())
+            this->tgt_adapter->check_continue(*PC);
+        pc.val=*PC;
         if(fetch_ins(pc, data)!=iss::Ok){
-            this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
+            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
-            pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
+            process_spawn_blocks();
+            if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
+            pc.val = super::core.enter_trap(arch::traits<ARCH>::RV_CAUSE_FETCH_ACCESS<<16, pc.val, 0);
         } else {
             if (is_jump_to_self_enabled(cond) &&
                     (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
@@ -311,11 +315,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 icount++;
                 instret++;
             }
-            cycle++;
+            *PC = *NEXT_PC;
-            pc.val=*NEXT_PC;
-            this->core.reg.PC = this->core.reg.NEXT_PC;
             this->core.reg.trap_state =  this->core.reg.pending_trap;
         }
+        fetch_count++;
+        cycle++;
     }
     return pc;
 }

gen_input/templates/llvm/CORENAME.cpp.gtl

@@ -204,7 +204,7 @@ private:
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
+        this->gen_sync(iss::PRE_SYNC, instr_descr.size());
         this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
                                    get_reg_ptr(traits::PC), true);
         this->builder.CreateStore(
@@ -279,6 +279,7 @@ template <typename ARCH>
 void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
     auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
     this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
+    this->builder.CreateBr(this->trap_blk);
 }
 
 template <typename ARCH>
@@ -381,4 +382,4 @@ volatile std::array<bool, 2> dummy = {
 };
 }
 }
-// clang-format on
+// clang-format on

src/elfio.cpp

@@ -0,0 +1,35 @@
+#ifdef _MSC_VER
+#define _SCL_SECURE_NO_WARNINGS
+#define ELFIO_NO_INTTYPES
+#endif
+
+#include <elfio/elfio_dump.hpp>
+#include <iostream>
+
+using namespace ELFIO;
+
+int main(int argc, char** argv) {
+    if(argc != 2) {
+        printf("Usage: elfdump <file_name>\n");
+        return 1;
+    }
+
+    elfio reader;
+
+    if(!reader.load(argv[1])) {
+        printf("File %s is not found or it is not an ELF file\n", argv[1]);
+        return 1;
+    }
+
+    dump::header(std::cout, reader);
+    dump::section_headers(std::cout, reader);
+    dump::segment_headers(std::cout, reader);
+    dump::symbol_tables(std::cout, reader);
+    dump::notes(std::cout, reader);
+    dump::modinfo(std::cout, reader);
+    dump::dynamic_tags(std::cout, reader);
+    dump::section_datas(std::cout, reader);
+    dump::segment_datas(std::cout, reader);
+
+    return 0;
+}

src/iss/arch/riscv_hart_common.h

@@ -35,6 +35,7 @@
 #ifndef _RISCV_HART_COMMON
 #define _RISCV_HART_COMMON
 
+#include "iss/vm_types.h"
 #include <cstdint>
 #include <elfio/elfio.hpp>
 #include <fmt/format.h>
@@ -314,55 +315,67 @@ struct riscv_hart_common {
     riscv_hart_common(){};
     ~riscv_hart_common(){};
     std::unordered_map<std::string, uint64_t> symbol_table;
+    uint64_t entry_address{0};
+    uint64_t tohost = tohost_dflt;
+    uint64_t fromhost = fromhost_dflt;
 
-    std::unordered_map<std::string, uint64_t> get_sym_table(std::string name) {
+    bool read_elf_file(std::string name, uint8_t expected_elf_class,
-        if(!symbol_table.empty())
+                       std::function<iss::status(uint64_t, uint64_t, const uint8_t* const)> cb) {
-            return symbol_table;
+        // Create elfio reader
-        FILE* fp = fopen(name.c_str(), "r");
+        ELFIO::elfio reader;
-        if(fp) {
+        // Load ELF data
-            std::array<char, 5> buf;
+        if(reader.load(name)) {
-            auto n = fread(buf.data(), 1, 4, fp);
+            // check elf properties
-            fclose(fp);
+            if(reader.get_class() != expected_elf_class)
-            if(n != 4)
+                return false;
-                throw std::runtime_error("input file has insufficient size");
+            if(reader.get_type() != ELFIO::ET_EXEC)
-            buf[4] = 0;
+                return false;
-            if(strcmp(buf.data() + 1, "ELF") == 0) {
+            if(reader.get_machine() != ELFIO::EM_RISCV)
-                // Create elfio reader
+                return false;
-                ELFIO::elfio reader;
+            entry_address = reader.get_entry();
-                // Load ELF data
+            for(const auto& pseg : reader.segments) {
-                if(!reader.load(name))
+                const auto fsize = pseg->get_file_size(); // 0x42c/0x0
-                    throw std::runtime_error("could not process elf file");
+                const auto seg_data = pseg->get_data();
-                // check elf properties
+                const auto type = pseg->get_type();
-                if(reader.get_type() != ET_EXEC)
+                if(type == 1 && fsize > 0) {
-                    throw std::runtime_error("wrong elf type in file");
+                    auto res = cb(pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
-                if(reader.get_machine() != EM_RISCV)
+                    if(res != iss::Ok)
-                    throw std::runtime_error("wrong elf machine in file");
+                        CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
-                const auto sym_sec = reader.sections[".symtab"];
+                }
-                if(SHT_SYMTAB == sym_sec->get_type() || SHT_DYNSYM == sym_sec->get_type()) {
+            }
-                    ELFIO::symbol_section_accessor symbols(reader, sym_sec);
+            const auto sym_sec = reader.sections[".symtab"];
-                    auto sym_no = symbols.get_symbols_num();
+            if(ELFIO::SHT_SYMTAB == sym_sec->get_type() || ELFIO::SHT_DYNSYM == sym_sec->get_type()) {
-                    std::string name;
+                ELFIO::symbol_section_accessor symbols(reader, sym_sec);
-                    ELFIO::Elf64_Addr value = 0;
+                auto sym_no = symbols.get_symbols_num();
-                    ELFIO::Elf_Xword size = 0;
+                std::string name;
-                    unsigned char bind = 0;
+                ELFIO::Elf64_Addr value = 0;
-                    unsigned char type = 0;
+                ELFIO::Elf_Xword size = 0;
-                    ELFIO::Elf_Half section = 0;
+                unsigned char bind = 0;
-                    unsigned char other = 0;
+                unsigned char type = 0;
-                    for(auto i = 0U; i < sym_no; ++i) {
+                ELFIO::Elf_Half section = 0;
-                        symbols.get_symbol(i, name, value, size, bind, type, section, other);
+                unsigned char other = 0;
-                        if(name != "") {
+                for(auto i = 0U; i < sym_no; ++i) {
-                            this->symbol_table[name] = value;
+                    symbols.get_symbol(i, name, value, size, bind, type, section, other);
+                    if(name != "") {
+                        this->symbol_table[name] = value;
 #ifndef NDEBUG
-                            CPPLOG(DEBUG) << "Found Symbol " << name;
+                        CPPLOG(DEBUG) << "Found Symbol " << name;
 #endif
-                        }
                     }
                 }
-                return symbol_table;
+                try {
+                    tohost = symbol_table.at("tohost");
+                    try {
+                        fromhost = symbol_table.at("fromhost");
+                    } catch(std::out_of_range& e) {
+                        fromhost = tohost + 0x40;
+                    }
+                } catch(std::out_of_range& e) {
+                }
             }
-            throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name));
+            return true;
-        } else
+        }
-            throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
+        return false;
     };
 };
 

src/iss/arch/riscv_hart_m_p.h

@@ -41,6 +41,7 @@
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
 #include "riscv_hart_common.h"
+#include <elfio/elf_types.hpp>
 #include <stdexcept>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -278,7 +279,7 @@ public:
 
     void disass_output(uint64_t pc, const std::string instr) override {
         NSCLOG(INFO, LOGCAT) << fmt::format("0x{:016x}    {:40} [s:0x{:x};c:{}]", pc, instr, (reg_t)state.mstatus,
-                                            this->reg.icount + cycle_offset);
+                                            this->reg.cycle + cycle_offset);
     };
 
     iss::instrumentation_if* get_instrumentation_if() override { return &instr_if; }
@@ -311,7 +312,7 @@ protected:
 
         uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
 
-        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
+        uint64_t get_total_cycles() override { return arch.reg.cycle + arch.cycle_offset; }
 
         void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
 
@@ -321,7 +322,7 @@ protected:
 
         unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
 
-        std::unordered_map<std::string, uint64_t> get_symbol_table(std::string name) override { return arch.get_sym_table(name); }
+        std::unordered_map<std::string, uint64_t> const& get_symbol_table(std::string name) override { return arch.symbol_table; }
 
         riscv_hart_m_p<BASE, FEAT, LOGCAT>& arch;
     };
@@ -343,8 +344,6 @@ protected:
     int64_t instret_offset{0};
     uint64_t minstret_csr{0};
     reg_t fault_data;
-    uint64_t tohost = tohost_dflt;
-    uint64_t fromhost = fromhost_dflt;
     bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
@@ -573,57 +572,14 @@ riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p(feature_config cfg)
 
 template <typename BASE, features_e FEAT, typename LOGCAT>
 std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT, LOGCAT>::load_file(std::string name, int type) {
-    get_sym_table(name);
+    if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFIO::ELFCLASS32 : ELFIO::ELFCLASS64,
-    try {
+                     [this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
-        tohost = symbol_table.at("tohost");
+                         return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, addr, size,
-        fromhost = symbol_table.at("fromhost");
+                                            data);
-    } catch(std::out_of_range& e) {
+                     })) {
+        return std::make_pair(entry_address, true);
     }
-    FILE* fp = fopen(name.c_str(), "r");
+    return std::make_pair(entry_address, false);
-    if(fp) {
-        std::array<char, 5> buf;
-        auto n = fread(buf.data(), 1, 4, fp);
-        fclose(fp);
-        if(n != 4)
-            throw std::runtime_error("input file has insufficient size");
-        buf[4] = 0;
-        if(strcmp(buf.data() + 1, "ELF") == 0) {
-            // Create elfio reader
-            ELFIO::elfio reader;
-            // Load ELF data
-            if(!reader.load(name))
-                throw std::runtime_error("could not process elf file");
-            // check elf properties
-            if(reader.get_class() != ELFCLASS32)
-                if(sizeof(reg_t) == 4)
-                    throw std::runtime_error("wrong elf class in file");
-            if(reader.get_type() != ET_EXEC)
-                throw std::runtime_error("wrong elf type in file");
-            if(reader.get_machine() != EM_RISCV)
-                throw std::runtime_error("wrong elf machine in file");
-            auto entry = reader.get_entry();
-            for(const auto pseg : reader.segments) {
-                const auto fsize = pseg->get_file_size(); // 0x42c/0x0
-                const auto seg_data = pseg->get_data();
-                const auto type = pseg->get_type();
-                if(type == 1 && fsize > 0) {
-                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
-                                           pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
-                    if(res != iss::Ok)
-                        CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
-                }
-            }
-            for(const auto& sec : reader.sections) {
-                if(sec->get_name() == ".tohost") {
-                    tohost = sec->get_address();
-                    fromhost = tohost + 0x40;
-                }
-            }
-            return std::make_pair(entry, true);
-        }
-        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name));
-    }
-    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
 }
 
 template <typename BASE, features_e FEAT, typename LOGCAT>
@@ -689,8 +645,10 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
                 }
                 return res;
             } catch(trap_access& ta) {
-                this->reg.trap_state = (1UL << 31) | ta.id;
+                if((access & access_type::DEBUG) == 0) {
-                fault_data = ta.addr;
+                    this->reg.trap_state = (1UL << 31) | ta.id;
+                    fault_data = ta.addr;
+                }
                 return iss::Err;
             }
         } break;
@@ -717,8 +675,10 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
         }
         return iss::Ok;
     } catch(trap_access& ta) {
-        this->reg.trap_state = (1UL << 31) | ta.id;
+        if((access & access_type::DEBUG) == 0) {
-        fault_data = ta.addr;
+            this->reg.trap_state = (1UL << 31) | ta.id;
+            fault_data = ta.addr;
+        }
         return iss::Err;
     }
 }
@@ -746,7 +706,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
                       << std::hex << addr;
         break;
     default:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr 0x" << std::hex << addr;
     }
 #endif
     try {
@@ -848,8 +808,10 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
         }
         return iss::Ok;
     } catch(trap_access& ta) {
-        this->reg.trap_state = (1UL << 31) | ta.id;
+        if((access & access_type::DEBUG) == 0) {
-        fault_data = ta.addr;
+            this->reg.trap_state = (1UL << 31) | ta.id;
+            fault_data = ta.addr;
+        }
         return iss::Err;
     }
 }
@@ -902,7 +864,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_plain(unsigned addr, reg_t
 
 template <typename BASE, features_e FEAT, typename LOGCAT>
 iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_cycle(unsigned addr, reg_t& val) {
-    auto cycle_val = this->reg.icount + cycle_offset;
+    auto cycle_val = this->reg.cycle + cycle_offset;
     if(addr == mcycle) {
         val = static_cast<reg_t>(cycle_val);
     } else if(addr == mcycleh) {
@@ -922,7 +884,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_cycle(unsigned addr, reg_t
             mcycle_csr = (static_cast<uint64_t>(val) << 32) + (mcycle_csr & 0xffffffff);
         }
     }
-    cycle_offset = mcycle_csr - this->reg.icount; // TODO: relying on wrap-around
+    cycle_offset = mcycle_csr - this->reg.cycle; // TODO: relying on wrap-around
     return iss::Ok;
 }
 
@@ -953,7 +915,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_instret(unsigned addr, reg
 
 template <typename BASE, features_e FEAT, typename LOGCAT>
 iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_time(unsigned addr, reg_t& val) {
-    uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
+    uint64_t time_val = this->reg.cycle / (100000000 / 32768 - 1); //-> ~3052;
     if(addr == time) {
         val = static_cast<reg_t>(time_val);
     } else if(addr == timeh) {

src/iss/arch/riscv_hart_msu_vp.h

@@ -328,7 +328,7 @@ public:
 
     void disass_output(uint64_t pc, const std::string instr) override {
         CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus,
-                                          this->reg.icount + cycle_offset);
+                                          this->reg.cycle + cycle_offset);
     };
 
     iss::instrumentation_if* get_instrumentation_if() override { return &instr_if; }
@@ -361,7 +361,7 @@ protected:
 
         uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
 
-        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
+        uint64_t get_total_cycles() override { return arch.reg.cycle + arch.cycle_offset; }
 
         void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
 
@@ -371,7 +371,7 @@ protected:
 
         unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
 
-        std::unordered_map<std::string, uint64_t> get_symbol_table(std::string name) override { return arch.get_sym_table(name); }
+        std::unordered_map<std::string, uint64_t> const& get_symbol_table(std::string name) override { return arch.symbol_table; }
 
         riscv_hart_msu_vp<BASE>& arch;
     };
@@ -393,8 +393,6 @@ protected:
     uint64_t minstret_csr{0};
     reg_t fault_data;
     std::array<vm_info, 2> vm;
-    uint64_t tohost = tohost_dflt;
-    uint64_t fromhost = fromhost_dflt;
     bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
@@ -557,71 +555,14 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
 }
 
 template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load_file(std::string name, int type) {
-    FILE* fp = fopen(name.c_str(), "r");
+    if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFIO::ELFCLASS32 : ELFIO::ELFCLASS64,
-    if(fp) {
+                     [this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
-        std::array<char, 5> buf;
+                         return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, addr, size,
-        auto n = fread(buf.data(), 1, 4, fp);
+                                            data);
-        fclose(fp);
+                     })) {
-        if(n != 4)
+        return std::make_pair(entry_address, true);
-            throw std::runtime_error("input file has insufficient size");
-        buf[4] = 0;
-        if(strcmp(buf.data() + 1, "ELF") == 0) {
-            // Create elfio reader
-            ELFIO::elfio reader;
-            // Load ELF data
-            if(!reader.load(name))
-                throw std::runtime_error("could not process elf file");
-            // check elf properties
-            if(reader.get_class() != ELFCLASS32)
-                if(sizeof(reg_t) == 4)
-                    throw std::runtime_error("wrong elf class in file");
-            if(reader.get_type() != ET_EXEC)
-                throw std::runtime_error("wrong elf type in file");
-            if(reader.get_machine() != EM_RISCV)
-                throw std::runtime_error("wrong elf machine in file");
-            auto entry = reader.get_entry();
-            for(const auto pseg : reader.segments) {
-                const auto fsize = pseg->get_file_size(); // 0x42c/0x0
-                const auto seg_data = pseg->get_data();
-                const auto type = pseg->get_type();
-                if(type == 1 && fsize > 0) {
-                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
-                                           pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
-                    if(res != iss::Ok)
-                        CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
-                }
-            }
-            for(const auto sec : reader.sections) {
-                if(sec->get_name() == ".symtab") {
-                    if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) {
-                        ELFIO::symbol_section_accessor symbols(reader, sec);
-                        auto sym_no = symbols.get_symbols_num();
-                        std::string name;
-                        ELFIO::Elf64_Addr value = 0;
-                        ELFIO::Elf_Xword size = 0;
-                        unsigned char bind = 0;
-                        unsigned char type = 0;
-                        ELFIO::Elf_Half section = 0;
-                        unsigned char other = 0;
-                        for(auto i = 0U; i < sym_no; ++i) {
-                            symbols.get_symbol(i, name, value, size, bind, type, section, other);
-                            if(name == "tohost") {
-                                tohost = value;
-                            } else if(name == "fromhost") {
-                                fromhost = value;
-                            }
-                        }
-                    }
-                } else if(sec->get_name() == ".tohost") {
-                    tohost = sec->get_address();
-                    fromhost = tohost + 0x40;
-                }
-            }
-            return std::make_pair(entry, true);
-        }
-        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name));
     }
-    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
+    return std::make_pair(entry_address, false);
 }
 
 template <typename BASE>
@@ -671,8 +612,10 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
                 }
                 return res;
             } catch(trap_access& ta) {
-                this->reg.trap_state = (1 << 31) | ta.id;
+                if((access & access_type::DEBUG) == 0) {
-                fault_data = ta.addr;
+                    this->reg.trap_state = (1UL << 31) | ta.id;
+                    fault_data = ta.addr;
+                }
                 return iss::Err;
             }
         } break;
@@ -710,8 +653,10 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
         }
         return iss::Ok;
     } catch(trap_access& ta) {
-        this->reg.trap_state = (1UL << 31) | ta.id;
+        if((access & access_type::DEBUG) == 0) {
-        fault_data = ta.addr;
+            this->reg.trap_state = (1UL << 31) | ta.id;
+            fault_data = ta.addr;
+        }
         return iss::Err;
     }
 }
@@ -841,8 +786,10 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
         }
         return iss::Ok;
     } catch(trap_access& ta) {
-        this->reg.trap_state = (1UL << 31) | ta.id;
+        if((access & access_type::DEBUG) == 0) {
-        fault_data = ta.addr;
+            this->reg.trap_state = (1UL << 31) | ta.id;
+            fault_data = ta.addr;
+        }
         return iss::Err;
     }
 }
@@ -889,7 +836,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_reg(unsigned
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigned addr, reg_t& val) {
-    auto cycle_val = this->reg.icount + cycle_offset;
+    auto cycle_val = this->reg.cycle + cycle_offset;
     if(addr == mcycle) {
         val = static_cast<reg_t>(cycle_val);
     } else if(addr == mcycleh) {
@@ -910,7 +857,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_cycle(unsign
             mcycle_csr = (static_cast<uint64_t>(val) << 32) + (mcycle_csr & 0xffffffff);
         }
     }
-    cycle_offset = mcycle_csr - this->reg.icount; // TODO: relying on wrap-around
+    cycle_offset = mcycle_csr - this->reg.cycle; // TODO: relying on wrap-around
     return iss::Ok;
 }
 
@@ -938,7 +885,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_instret(unsi
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned addr, reg_t& val) {
-    uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
+    uint64_t time_val = this->reg.cycle / (100000000 / 32768 - 1); //-> ~3052;
     if(addr == time) {
         val = static_cast<reg_t>(time_val);
     } else if(addr == timeh) {

src/iss/arch/riscv_hart_mu_p.h

@@ -305,7 +305,7 @@ public:
 
     void disass_output(uint64_t pc, const std::string instr) override {
         NSCLOG(INFO, LOGCAT) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus,
-                                            this->reg.icount + cycle_offset);
+                                            this->reg.cycle + cycle_offset);
     };
 
     iss::instrumentation_if* get_instrumentation_if() override { return &instr_if; }
@@ -338,7 +338,7 @@ protected:
 
         uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
 
-        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
+        uint64_t get_total_cycles() override { return arch.reg.cycle + arch.cycle_offset; }
 
         void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
 
@@ -348,7 +348,7 @@ protected:
 
         unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
 
-        std::unordered_map<std::string, uint64_t> get_symbol_table(std::string name) override { return arch.get_sym_table(name); }
+        std::unordered_map<std::string, uint64_t> const& get_symbol_table(std::string name) override { return arch.symbol_table; }
 
         riscv_hart_mu_p<BASE, FEAT, LOGCAT>& arch;
     };
@@ -370,8 +370,6 @@ protected:
     int64_t instret_offset{0};
     uint64_t minstret_csr{0};
     reg_t fault_data;
-    uint64_t tohost = tohost_dflt;
-    uint64_t fromhost = fromhost_dflt;
     bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
@@ -651,71 +649,14 @@ riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p(feature_config cfg)
 
 template <typename BASE, features_e FEAT, typename LOGCAT>
 std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT, LOGCAT>::load_file(std::string name, int type) {
-    FILE* fp = fopen(name.c_str(), "r");
+    if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFIO::ELFCLASS32 : ELFIO::ELFCLASS64,
-    if(fp) {
+                     [this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
-        std::array<char, 5> buf;
+                         return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, addr, size,
-        auto n = fread(buf.data(), 1, 4, fp);
+                                            data);
-        fclose(fp);
+                     })) {
-        if(n != 4)
+        return std::make_pair(entry_address, true);
-            throw std::runtime_error("input file has insufficient size");
-        buf[4] = 0;
-        if(strcmp(buf.data() + 1, "ELF") == 0) {
-            // Create elfio reader
-            ELFIO::elfio reader;
-            // Load ELF data
-            if(!reader.load(name))
-                throw std::runtime_error("could not process elf file");
-            // check elf properties
-            if(reader.get_class() != ELFCLASS32)
-                if(sizeof(reg_t) == 4)
-                    throw std::runtime_error("wrong elf class in file");
-            if(reader.get_type() != ET_EXEC)
-                throw std::runtime_error("wrong elf type in file");
-            if(reader.get_machine() != EM_RISCV)
-                throw std::runtime_error("wrong elf machine in file");
-            auto entry = reader.get_entry();
-            for(const auto pseg : reader.segments) {
-                const auto fsize = pseg->get_file_size(); // 0x42c/0x0
-                const auto seg_data = pseg->get_data();
-                const auto type = pseg->get_type();
-                if(type == 1 && fsize > 0) {
-                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
-                                           pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
-                    if(res != iss::Ok)
-                        CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
-                }
-            }
-            for(const auto sec : reader.sections) {
-                if(sec->get_name() == ".symtab") {
-                    if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) {
-                        ELFIO::symbol_section_accessor symbols(reader, sec);
-                        auto sym_no = symbols.get_symbols_num();
-                        std::string name;
-                        ELFIO::Elf64_Addr value = 0;
-                        ELFIO::Elf_Xword size = 0;
-                        unsigned char bind = 0;
-                        unsigned char type = 0;
-                        ELFIO::Elf_Half section = 0;
-                        unsigned char other = 0;
-                        for(auto i = 0U; i < sym_no; ++i) {
-                            symbols.get_symbol(i, name, value, size, bind, type, section, other);
-                            if(name == "tohost") {
-                                tohost = value;
-                            } else if(name == "fromhost") {
-                                fromhost = value;
-                            }
-                        }
-                    }
-                } else if(sec->get_name() == ".tohost") {
-                    tohost = sec->get_address();
-                    fromhost = tohost + 0x40;
-                }
-            }
-            return std::make_pair(entry, true);
-        }
-        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name));
     }
-    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
+    return std::make_pair(entry_address, false);
 }
 
 template <typename BASE, features_e FEAT, typename LOGCAT>
@@ -877,8 +818,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read(const address_type type, c
                 }
                 return res;
             } catch(trap_access& ta) {
-                this->reg.trap_state = (1UL << 31) | ta.id;
+                if((access & access_type::DEBUG) == 0) {
-                fault_data = ta.addr;
+                    this->reg.trap_state = (1UL << 31) | ta.id;
+                    fault_data = ta.addr;
+                }
                 return iss::Err;
             }
         } break;
@@ -905,8 +848,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read(const address_type type, c
         }
         return iss::Ok;
     } catch(trap_access& ta) {
-        this->reg.trap_state = (1UL << 31) | ta.id;
+        if((access & access_type::DEBUG) == 0) {
-        fault_data = ta.addr;
+            this->reg.trap_state = (1UL << 31) | ta.id;
+            fault_data = ta.addr;
+        }
         return iss::Err;
     }
 }
@@ -1045,8 +990,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write(const address_type type,
         }
         return iss::Ok;
     } catch(trap_access& ta) {
-        this->reg.trap_state = (1UL << 31) | ta.id;
+        if((access & access_type::DEBUG) == 0) {
-        fault_data = ta.addr;
+            this->reg.trap_state = (1UL << 31) | ta.id;
+            fault_data = ta.addr;
+        }
         return iss::Err;
     }
 }
@@ -1099,7 +1046,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_plain(unsigned addr, reg_
 
 template <typename BASE, features_e FEAT, typename LOGCAT>
 iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read_cycle(unsigned addr, reg_t& val) {
-    auto cycle_val = this->reg.icount + cycle_offset;
+    auto cycle_val = this->reg.cycle + cycle_offset;
     if(addr == mcycle) {
         val = static_cast<reg_t>(cycle_val);
     } else if(addr == mcycleh) {
@@ -1119,7 +1066,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_cycle(unsigned addr, reg_
             mcycle_csr = (static_cast<uint64_t>(val) << 32) + (mcycle_csr & 0xffffffff);
         }
     }
-    cycle_offset = mcycle_csr - this->reg.icount; // TODO: relying on wrap-around
+    cycle_offset = mcycle_csr - this->reg.cycle; // TODO: relying on wrap-around
     return iss::Ok;
 }
 
@@ -1150,7 +1097,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_instret(unsigned addr, re
 
 template <typename BASE, features_e FEAT, typename LOGCAT>
 iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read_time(unsigned addr, reg_t& val) {
-    uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
+    uint64_t time_val = this->reg.cycle / (100000000 / 32768 - 1); //-> ~3052;
     if(addr == time) {
         val = static_cast<reg_t>(time_val);
     } else if(addr == timeh) {

src/iss/debugger/riscv_target_adapter.h

@@ -30,8 +30,8 @@
  *
  *******************************************************************************/
 
-#ifndef _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
+#ifndef _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_
-#define _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
+#define _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_
 
 #include "iss/arch_if.h"
 #include <iss/arch/traits.h>
@@ -48,6 +48,10 @@
 
 namespace iss {
 namespace debugger {
+
+char const* const get_csr_name(unsigned);
+constexpr auto csr_offset = 100U;
+
 using namespace iss::arch;
 using namespace iss::debugger;
 
@@ -129,11 +133,17 @@ public:
 
 protected:
     static inline constexpr addr_t map_addr(const addr_t& i) { return i; }
-
+    std::string csr_xml;
     iss::arch_if* core;
     rp_thread_ref thread_idx;
 };
 
+template <typename ARCH> typename std::enable_if<iss::arch::traits<ARCH>::FLEN != 0, unsigned>::type get_f0_offset() {
+    return iss::arch::traits<ARCH>::F0;
+}
+
+template <typename ARCH> typename std::enable_if<iss::arch::traits<ARCH>::FLEN == 0, unsigned>::type get_f0_offset() { return 0; }
+
 template <typename ARCH> status riscv_target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) {
     thread_idx = thread;
     return Ok;
@@ -175,34 +185,37 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
     CPPLOG(TRACE) << "reading target registers";
-    // return idx<0?:;
     data.clear();
     avail.clear();
     const uint8_t* reg_base = core->get_regs_base_ptr();
     auto start_reg = arch::traits<ARCH>::X0;
-    for(size_t reg_no = start_reg; reg_no < start_reg + 33 /*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
+    for(size_t i = 0; i < 33; ++i) {
-        auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
+        if(i < arch::traits<ARCH>::RFS || i == arch::traits<ARCH>::PC) {
-        unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
+            auto reg_no = i < 32 ? start_reg + i : arch::traits<ARCH>::PC;
-        for(size_t j = 0; j < reg_width; ++j) {
+            unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
-            data.push_back(*(reg_base + offset + j));
+            for(size_t j = 0; j < arch::traits<ARCH>::XLEN / 8; ++j) {
-            avail.push_back(0xff);
+                data.push_back(*(reg_base + offset + j));
+                avail.push_back(0xff);
+            }
+        } else {
+            for(size_t j = 0; j < arch::traits<ARCH>::XLEN / 8; ++j) {
+                data.push_back(0);
+                avail.push_back(0);
+            }
+        }
+    }
+    if(iss::arch::traits<ARCH>::FLEN > 0) {
+        auto fstart_reg = get_f0_offset<ARCH>();
+        for(size_t i = 0; i < 32; ++i) {
+            auto reg_no = fstart_reg + i;
+            auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
+            unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
+            for(size_t j = 0; j < reg_width; ++j) {
+                data.push_back(*(reg_base + offset + j));
+                avail.push_back(0xff);
+            }
         }
     }
-    // work around fill with F type registers
-    //    if (arch::traits<ARCH>::NUM_REGS < 65) {
-    //        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
-    //        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
-    //            for (size_t j = 0; j < reg_width; ++j) {
-    //                data.push_back(0x0);
-    //                avail.push_back(0x00);
-    //            }
-    //            // if(arch::traits<ARCH>::XLEN < 64)
-    //            //     for(unsigned j=0; j<4; ++j){
-    //            //         data.push_back(0x0);
-    //            //         avail.push_back(0x00);
-    //            //     }
-    //        }
-    //    }
     return Ok;
 }
 
@@ -210,25 +223,25 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
     auto start_reg = arch::traits<ARCH>::X0;
     auto* reg_base = core->get_regs_base_ptr();
     auto iter = data.data();
-    bool e_ext = arch::traits<ARCH>::PC < 32;
+    auto iter_end = data.data() + data.size();
-    for(size_t reg_no = 0; reg_no < start_reg + 33 /*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
+    for(size_t i = 0; i < 33 && iter < iter_end; ++i) {
-        if(e_ext && reg_no > 15) {
+        auto reg_width = arch::traits<ARCH>::XLEN / 8;
-            if(reg_no == 32) {
+        if(i < arch::traits<ARCH>::RFS) {
-                auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
+            auto offset = traits<ARCH>::reg_byte_offsets[start_reg + i];
-                auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
+            std::copy(iter, iter + reg_width, reg_base + offset);
-                std::copy(iter, iter + reg_width, reg_base);
+        } else if(i == 32) {
-            } else {
+            auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
-                const uint64_t zero_val = 0;
+            std::copy(iter, iter + reg_width, reg_base + offset);
-                auto reg_width = arch::traits<ARCH>::reg_bit_widths[15] / 8;
+        }
-                auto iter = (uint8_t*)&zero_val;
+        iter += reg_width;
-                std::copy(iter, iter + reg_width, reg_base);
+    }
-            }
+    if(iss::arch::traits<ARCH>::FLEN > 0) {
-        } else {
+        auto fstart_reg = get_f0_offset<ARCH>();
-            auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
+        auto reg_width = arch::traits<ARCH>::FLEN / 8;
-            auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
+        for(size_t i = 0; i < 32 && iter < iter_end; ++i) {
-            std::copy(iter, iter + reg_width, reg_base);
+            unsigned offset = traits<ARCH>::reg_byte_offsets[fstart_reg + i];
-            iter += 4;
+            std::copy(iter, iter + reg_width, reg_base + offset);
-            reg_base += offset;
+            iter += reg_width;
         }
     }
     return Ok;
@@ -236,7 +249,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
 
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
-    if(reg_no < 65) {
+    if(reg_no < csr_offset) {
         // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
         // arch::traits<ARCH>::reg_e>(reg_no))/8;
         auto* reg_base = core->get_regs_base_ptr();
@@ -247,23 +260,24 @@ status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std
         std::copy(reg_base + offset, reg_base + offset + reg_width, data.begin());
         std::fill(avail.begin(), avail.end(), 0xff);
     } else {
-        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, reg_no - 65);
+        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, reg_no - csr_offset);
         data.resize(sizeof(typename traits<ARCH>::reg_t));
         avail.resize(sizeof(typename traits<ARCH>::reg_t));
         std::fill(avail.begin(), avail.end(), 0xff);
         core->read(a, data.size(), data.data());
+        std::fill(avail.begin(), avail.end(), 0xff);
     }
     return data.size() > 0 ? Ok : Err;
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t>& data) {
-    if(reg_no < 65) {
+    if(reg_no < csr_offset) {
         auto* reg_base = core->get_regs_base_ptr();
         auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
         auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
         std::copy(data.begin(), data.begin() + reg_width, reg_base + offset);
     } else {
-        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - 65);
+        typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - csr_offset);
         core->write(a, data.size(), data.data());
     }
     return Ok;
@@ -276,7 +290,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t ad
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t>& data) {
-    auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
+    auto a = map_addr({iss::access_type::DEBUG_WRITE, iss::address_type::VIRTUAL, 0, addr});
     auto f = [&]() -> status { return core->write(a, data.size(), data.data()); };
     return srv->execute_syncronized(f);
 }
@@ -369,93 +383,57 @@ status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string& out_buf) {
-    const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
+    if(!csr_xml.size()) {
-                          "<target><architecture>riscv:rv32</architecture>"
+        std::ostringstream oss;
-                          //"  <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
+        oss << "<?xml version=\"1.0\"?><!DOCTYPE feature SYSTEM \"gdb-target.dtd\"><target version=\"1.0\">\n";
-                          //"    <reg name=\"x0\"  bitsize=\"32\" group=\"general\"/>\n"
+        if(iss::arch::traits<ARCH>::XLEN == 32)
-                          //"    <reg name=\"x1\"  bitsize=\"32\" group=\"general\"/>\n"
+            oss << "<architecture>riscv:rv32</architecture>\n";
-                          //"    <reg name=\"x2\"  bitsize=\"32\" group=\"general\"/>\n"
+        else if(iss::arch::traits<ARCH>::XLEN == 64)
-                          //"    <reg name=\"x3\"  bitsize=\"32\" group=\"general\"/>\n"
+            oss << "  <architectureriscv:rv64</architecture>\n";
-                          //"    <reg name=\"x4\"  bitsize=\"32\" group=\"general\"/>\n"
+        oss << "  <feature name=\"org.gnu.gdb.riscv.cpu\">\n";
-                          //"    <reg name=\"x5\"  bitsize=\"32\" group=\"general\"/>\n"
+        auto reg_base_num = iss::arch::traits<ARCH>::X0;
-                          //"    <reg name=\"x6\"  bitsize=\"32\" group=\"general\"/>\n"
+        for(auto i = 0U; i < iss::arch::traits<ARCH>::RFS; ++i) {
-                          //"    <reg name=\"x7\"  bitsize=\"32\" group=\"general\"/>\n"
+            oss << "    <reg name=\"x" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i]
-                          //"    <reg name=\"x8\"  bitsize=\"32\" group=\"general\"/>\n"
+                << "\" type=\"int\" regnum=\"" << i << "\"/>\n";
-                          //"    <reg name=\"x9\"  bitsize=\"32\" group=\"general\"/>\n"
+        }
-                          //"    <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
+        oss << "    <reg name=\"pc\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[iss::arch::traits<ARCH>::PC]
-                          //"    <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
+            << "\" type=\"code_ptr\" regnum=\"" << 32U << "\"/>\n";
-                          //"    <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
+        oss << "  </feature>\n";
-                          //"    <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
+        if(iss::arch::traits<ARCH>::FLEN > 0) {
-                          //"    <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
+            oss << "  <feature name=\"org.gnu.gdb.riscv.fpu\">\n";
-                          //"    <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
+            auto reg_base_num = get_f0_offset<ARCH>();
-                          //"    <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
+            auto type = iss::arch::traits<ARCH>::FLEN == 32 ? "ieee_single" : "riscv_double";
-                          //"    <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
+            for(auto i = 0U; i < 32; ++i) {
-                          //"    <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
+                oss << "    <reg name=\"f" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i]
-                          //"    <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
+                    << "\" type=\"" << type << "\" regnum=\"" << i + 33 << "\"/>\n";
-                          //"    <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
+            }
-                          //"    <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
+            oss << "    <reg name=\"fcsr\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"103\" type int/>\n";
-                          //"    <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
+            oss << "    <reg name=\"fflags\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"101\" type int/>\n";
-                          //"    <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
+            oss << "    <reg name=\"frm\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"102\" type int/>\n";
-                          //"    <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
+            oss << "  </feature>\n";
-                          //"    <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
+        }
-                          //"    <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
+        oss << "  <feature name=\"org.gnu.gdb.riscv.csr\">\n";
-                          //"    <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
+        std::vector<uint8_t> data;
-                          //"    <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
+        std::vector<uint8_t> avail;
-                          //"    <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
+        data.resize(sizeof(typename traits<ARCH>::reg_t));
-                          //"    <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
+        avail.resize(sizeof(typename traits<ARCH>::reg_t));
-                          //"    <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
+        for(auto i = 0U; i < 4096; ++i) {
-                          //"  </feature>\n"
+            typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, i);
-                          "</target>"};
+            std::fill(avail.begin(), avail.end(), 0xff);
-    out_buf = res;
+            auto res = core->read(a, data.size(), data.data());
+            if(res == iss::Ok) {
+                oss << "    <reg name=\"" << get_csr_name(i) << "\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN
+                    << "\"  type=\"int\" regnum=\"" << (i + csr_offset) << "\"/>\n";
+            }
+        }
+        oss << "  </feature>\n";
+        oss << "</target>\n";
+        csr_xml = oss.str();
+    }
+    out_buf = csr_xml;
     return Ok;
 }
-
-/*
- *
-<?xml version="1.0"?>
-<!DOCTYPE target SYSTEM "gdb-target.dtd">
-<target>
-  <architecture>riscv:rv32</architecture>
-
-  <feature name="org.gnu.gdb.riscv.rv32i">
-    <reg name="x0"  bitsize="32" group="general"/>
-    <reg name="x1"  bitsize="32" group="general"/>
-    <reg name="x2"  bitsize="32" group="general"/>
-    <reg name="x3"  bitsize="32" group="general"/>
-    <reg name="x4"  bitsize="32" group="general"/>
-    <reg name="x5"  bitsize="32" group="general"/>
-    <reg name="x6"  bitsize="32" group="general"/>
-    <reg name="x7"  bitsize="32" group="general"/>
-    <reg name="x8"  bitsize="32" group="general"/>
-    <reg name="x9"  bitsize="32" group="general"/>
-    <reg name="x10" bitsize="32" group="general"/>
-    <reg name="x11" bitsize="32" group="general"/>
-    <reg name="x12" bitsize="32" group="general"/>
-    <reg name="x13" bitsize="32" group="general"/>
-    <reg name="x14" bitsize="32" group="general"/>
-    <reg name="x15" bitsize="32" group="general"/>
-    <reg name="x16" bitsize="32" group="general"/>
-    <reg name="x17" bitsize="32" group="general"/>
-    <reg name="x18" bitsize="32" group="general"/>
-    <reg name="x19" bitsize="32" group="general"/>
-    <reg name="x20" bitsize="32" group="general"/>
-    <reg name="x21" bitsize="32" group="general"/>
-    <reg name="x22" bitsize="32" group="general"/>
-    <reg name="x23" bitsize="32" group="general"/>
-    <reg name="x24" bitsize="32" group="general"/>
-    <reg name="x25" bitsize="32" group="general"/>
-    <reg name="x26" bitsize="32" group="general"/>
-    <reg name="x27" bitsize="32" group="general"/>
-    <reg name="x28" bitsize="32" group="general"/>
-    <reg name="x29" bitsize="32" group="general"/>
-    <reg name="x30" bitsize="32" group="general"/>
-    <reg name="x31" bitsize="32" group="general"/>
-  </feature>
-
-</target>
-
- */
 } // namespace debugger
 } // namespace iss
 
-#endif /* _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */
+#endif /* _ISS_ARCH_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */

src/main.cpp

@@ -141,7 +141,10 @@ int main(int argc, char* argv[]) {
             std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as<unsigned>(), &semihosting_cb);
         }
         if(!cpu) {
-            CPPLOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
+            auto list = f.get_names();
+            std::sort(std::begin(list), std::end(list));
+            CPPLOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << "\n"
+                        << "Available implementations (core|platform|backend):\n  - " << util::join(list, "\n  - ") << std::endl;
             return 127;
         }
         if(!vm) {
@@ -203,13 +206,21 @@ int main(int argc, char* argv[]) {
         if(clim.count("elf"))
             for(std::string input : clim["elf"].as<std::vector<std::string>>()) {
                 auto start_addr = vm->get_arch()->load_file(input);
-                if(start_addr.second) // FIXME: this always evaluates to true as load file always returns <sth, true>
+                if(start_addr.second)
                     start_address = start_addr.first;
+                else {
+                    LOG(ERR) << "Error occured while loading file " << input << std::endl;
+                    return 1;
+                }
             }
         for(std::string input : args) {
             auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files
-            if(start_addr.second) // FIXME: this always evaluates to true as load file always returns <sth, true>
+            if(start_addr.second)
                 start_address = start_addr.first;
+            else {
+                LOG(ERR) << "Error occured while loading file " << input << std::endl;
+                return 1;
+            }
         }
         if(clim.count("reset")) {
             auto str = clim["reset"].as<std::string>();

src/sysc/core_complex.cpp

@@ -42,7 +42,6 @@
 #include <iss/plugin/loader.h>
 #endif
 #include "sc_core_adapter_if.h"
-#include <iss/arch/tgc_mapper.h>
 #include <scc/report.h>
 #include <util/ities.h>
 #include <iostream>
@@ -125,7 +124,7 @@ using vm_ptr = std::unique_ptr<iss::vm_if>;
 
 class core_wrapper {
 public:
-    core_wrapper(core_complex* owner)
+    core_wrapper(core_complex_if* owner)
     : owner(owner) {}
 
     void reset(uint64_t addr) { vm->reset(addr); }
@@ -181,7 +180,7 @@ public:
                                              "SystemC sub-commands: break <time>, print_time"});
     }
 
-    core_complex* const owner;
+    core_complex_if* const owner;
     vm_ptr vm{nullptr};
     sc_cpu_ptr cpu{nullptr};
     iss::debugger::target_adapter_if* tgt_adapter{nullptr};
@@ -197,7 +196,6 @@ struct core_trace {
     scv_tr_handle tr_handle;
 };
 
-SC_HAS_PROCESS(core_complex); // NOLINT
 #ifndef CWR_SYSTEMC
 template <unsigned int BUSWIDTH>
 core_complex<BUSWIDTH>::core_complex(sc_module_name const& name)
@@ -209,8 +207,7 @@ core_complex<BUSWIDTH>::core_complex(sc_module_name const& name)
 }
 #endif
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::init() {
-void core_complex<BUSWIDTH>::init() {
     trc = new core_trace();
     ibus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
         auto lut_entry = fetch_lut.getEntry(start);
@@ -255,19 +252,16 @@ void core_complex<BUSWIDTH>::init() {
 #endif
 }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> core_complex<BUSWIDTH>::~core_complex() {
-core_complex<BUSWIDTH>::~core_complex() {
     delete cpu;
     delete trc;
     for(auto* p : plugin_list)
         delete p;
 }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::trace(sc_trace_file* trf) const {}
-void core_complex<BUSWIDTH>::trace(sc_trace_file* trf) const {}
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::before_end_of_elaboration() {
-void core_complex<BUSWIDTH>::before_end_of_elaboration() {
     SCCDEBUG(SCMOD) << "instantiating iss::arch::tgf with " << GET_PROP_VALUE(backend) << " backend";
     // cpu = scc::make_unique<core_wrapper>(this);
     cpu = new core_wrapper(this);
@@ -308,8 +302,7 @@ void core_complex<BUSWIDTH>::before_end_of_elaboration() {
     }
 }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::start_of_simulation() {
-void core_complex<BUSWIDTH>::start_of_simulation() {
     // quantum_keeper.reset();
     if(GET_PROP_VALUE(elf_file).size() > 0) {
         istringstream is(GET_PROP_VALUE(elf_file));
@@ -332,8 +325,7 @@ void core_complex<BUSWIDTH>::start_of_simulation() {
     }
 }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_str) {
-bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_str) {
     if(trc->m_db == nullptr)
         return false;
     if(trc->tr_handle.is_active())
@@ -347,8 +339,7 @@ bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_
     return true;
 }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::forward() {
-void core_complex<BUSWIDTH>::forward() {
 #ifndef CWR_SYSTEMC
     set_clock_period(clk_i.read());
 #else
@@ -357,30 +348,24 @@ void core_complex<BUSWIDTH>::forward() {
 #endif
 }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::set_clock_period(sc_core::sc_time period) {
-void core_complex<BUSWIDTH>::set_clock_period(sc_core::sc_time period) {
     curr_clk = period;
     if(period == SC_ZERO_TIME)
         cpu->set_interrupt_execution(true);
 }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::rst_cb() {
-void core_complex<BUSWIDTH>::rst_cb() {
     if(rst_i.read())
         cpu->set_interrupt_execution(true);
 }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
-void core_complex<BUSWIDTH>::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
-void core_complex<BUSWIDTH>::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
-void core_complex<BUSWIDTH>::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::local_irq_cb() {
-void core_complex<BUSWIDTH>::local_irq_cb() {
     for(auto i = 0U; i < local_irq_i.size(); ++i) {
         if(local_irq_i[i].event()) {
             cpu->local_irq(16 + i, local_irq_i[i].read());
@@ -388,8 +373,7 @@ void core_complex<BUSWIDTH>::local_irq_cb() {
     }
 }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::run() {
-void core_complex<BUSWIDTH>::run() {
     wait(SC_ZERO_TIME); // separate from elaboration phase
     do {
         wait(SC_ZERO_TIME);
@@ -407,8 +391,7 @@ void core_complex<BUSWIDTH>::run() {
     sc_stop();
 }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
-bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
     auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
     auto lut_entry = dmi_lut.getEntry(addr);
     if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
@@ -466,8 +449,7 @@ bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* c
     }
 }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
-bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
     auto lut_entry = write_lut.getEntry(addr);
     if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
         auto offset = addr - lut_entry.get_start_address();
@@ -515,8 +497,7 @@ bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uin
     }
 }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
-bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
     tlm::tlm_generic_payload gp;
     gp.set_command(tlm::TLM_READ_COMMAND);
     gp.set_address(addr);
@@ -526,8 +507,7 @@ bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_
     return dbus->transport_dbg(gp) == length;
 }
 
-template <unsigned int BUSWIDTH>
+template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
-bool core_complex<BUSWIDTH>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
     write_buf.resize(length);
     std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
     tlm::tlm_generic_payload gp;

src/sysc/core_complex.h

@@ -33,10 +33,10 @@
 #ifndef _SYSC_CORE_COMPLEX_H_
 #define _SYSC_CORE_COMPLEX_H_
 
+#include <scc/signal_opt_ports.h>
 #include <scc/tick2time.h>
 #include <scc/traceable.h>
 #include <scc/utilities.h>
-#include <scc/signal_opt_ports.h>
 #include <tlm/scc/initiator_mixin.h>
 #include <tlm/scc/scv/tlm_rec_initiator_socket.h>
 #ifdef CWR_SYSTEMC
@@ -71,27 +71,27 @@ struct core_complex_if {
 
     virtual ~core_complex_if() = default;
 
-    virtual bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) =0;
+    virtual bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) = 0;
 
-    virtual bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data)  =0;
+    virtual bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) = 0;
 
-    virtual bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data)  =0;
+    virtual bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) = 0;
 
-    virtual bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data)  =0;
+    virtual bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) = 0;
 
-    virtual bool disass_output(uint64_t pc, const std::string instr)  =0;
+    virtual bool disass_output(uint64_t pc, const std::string instr) = 0;
 
-    virtual unsigned get_last_bus_cycles() =0;
+    virtual unsigned get_last_bus_cycles() = 0;
 
-    virtual void sync(uint64_t) =0;
+    //! Allow quantum keeper handling
+    virtual void sync(uint64_t) = 0;
 
     virtual char const* hier_name() = 0;
 
     scc::sc_in_opt<uint64_t> mtime_i{"mtime_i"};
 };
 
-template <unsigned int BUSWIDTH = scc::LT>
+template <unsigned int BUSWIDTH = scc::LT> class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
-class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
 public:
     tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> ibus{"ibus"};
 
@@ -207,9 +207,7 @@ public:
 
     void set_clock_period(sc_core::sc_time period);
 
-    char const* hier_name() override {
+    char const* hier_name() override { return name(); }
-        return name();
-    }
 
 protected:
     void before_end_of_elaboration() override;

src/sysc/register_tgc_c.cpp

@@ -46,12 +46,12 @@ using namespace sysc;
 volatile std::array<bool, 2> tgc_init = {
     iss_factory::instance().register_creator("tgc5c|m_p|interp",
                                              [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
                                                  auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
                                                  return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
                                              }),
     iss_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
         auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
         return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
     })};
@@ -62,12 +62,12 @@ using namespace sysc;
 volatile std::array<bool, 2> tgc_init = {
     iss_factory::instance().register_creator("tgc5c|m_p|llvm",
                                              [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
                                                  auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
                                                  return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
                                              }),
     iss_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
         auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
         return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
     })};
@@ -79,12 +79,12 @@ using namespace sysc;
 volatile std::array<bool, 2> tgc_init = {
     iss_factory::instance().register_creator("tgc5c|m_p|tcc",
                                              [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
                                                  auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
                                                  return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
                                              }),
     iss_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
         auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
         return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
     })};
@@ -96,12 +96,12 @@ using namespace sysc;
 volatile std::array<bool, 2> tgc_init = {
     iss_factory::instance().register_creator("tgc5c|m_p|asmjit",
                                              [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
                                                  auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
                                                  return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
                                              }),
     iss_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
         auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
         return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
     })};

src/sysc/sc_core_adapter.h

@@ -55,8 +55,8 @@ public:
             s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2)
               << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount + this->cycle_offset << "]";
             SCCDEBUG(owner->hier_name()) << "disass: "
-                                    << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
+                                         << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t"
-                                    << std::setfill(' ') << std::left << instr << s.str();
+                                         << std::setw(40) << std::setfill(' ') << std::left << instr << s.str();
         }
     };
 
@@ -113,7 +113,7 @@ public:
 
     iss::status read_csr(unsigned addr, reg_t& val) override {
         if((addr == iss::arch::time || addr == iss::arch::timeh)) {
-            uint64_t time_val = owner->mtime_i.get_interface()? owner->mtime_i.read():0;
+            uint64_t time_val = owner->mtime_i.get_interface() ? owner->mtime_i.read() : 0;
             if(addr == iss::arch::time) {
                 val = static_cast<reg_t>(time_val);
             } else if(addr == iss::arch::timeh) {
@@ -163,7 +163,7 @@ public:
     }
 
 private:
-    sysc::tgfs::core_complex_if* const owner;
+    sysc::tgfs::core_complex_if* const owner{nullptr};
     sc_core::sc_event wfi_evt;
     uint64_t hostvar{std::numeric_limits<uint64_t>::max()};
     unsigned to_host_wr_cnt = 0;

src/vm/asmjit/vm_tgc5c.cpp

@@ -1421,23 +1421,21 @@ private:
         }
         else{
             if(rd!=0){
-                {
+                auto label_then11 = cc.newLabel();
-                auto label_then = cc.newLabel();
+                auto label_merge11 = cc.newLabel();
-                auto label_merge = cc.newLabel();
+                auto tmp_reg11 = get_reg(cc, 8, false);
-                auto tmp_reg = get_reg_for(cc, 1);
                 cmp(cc, gen_ext(cc, 
                     load_reg_from_mem(jh, traits::X0 + rs1), 32, true), (int16_t)sext<12>(imm));
-                cc.jl(label_then);
+                cc.jl(label_then11);
-                mov(cc, tmp_reg,0);
+                mov(cc, tmp_reg11,0);
-                cc.jmp(label_merge);
+                cc.jmp(label_merge11);
-                cc.bind(label_then);
+                cc.bind(label_then11);
-                mov(cc, tmp_reg,1);
+                mov(cc, tmp_reg11, 1);
-                cc.bind(label_merge);
+                cc.bind(label_merge11);
                 mov(cc, get_ptr_for(jh, traits::X0+ rd),
-                      gen_ext(cc, tmp_reg
+                      gen_ext(cc, tmp_reg11
                       , 32, false)
                 );
-                }
             }
         }
         auto returnValue = CONT;
@@ -1484,22 +1482,20 @@ private:
         }
         else{
             if(rd!=0){
-                {
+                auto label_then12 = cc.newLabel();
-                auto label_then = cc.newLabel();
+                auto label_merge12 = cc.newLabel();
-                auto label_merge = cc.newLabel();
+                auto tmp_reg12 = get_reg(cc, 8, false);
-                auto tmp_reg = get_reg_for(cc, 1);
                 cmp(cc, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm)));
-                cc.jb(label_then);
+                cc.jb(label_then12);
-                mov(cc, tmp_reg,0);
+                mov(cc, tmp_reg12,0);
-                cc.jmp(label_merge);
+                cc.jmp(label_merge12);
-                cc.bind(label_then);
+                cc.bind(label_then12);
-                mov(cc, tmp_reg,1);
+                mov(cc, tmp_reg12, 1);
-                cc.bind(label_merge);
+                cc.bind(label_merge12);
                 mov(cc, get_ptr_for(jh, traits::X0+ rd),
-                      gen_ext(cc, tmp_reg
+                      gen_ext(cc, tmp_reg12
                       , 32, false)
                 );
-                }
             }
         }
         auto returnValue = CONT;
@@ -1992,24 +1988,22 @@ private:
         }
         else{
             if(rd!=0){
-                {
+                auto label_then13 = cc.newLabel();
-                auto label_then = cc.newLabel();
+                auto label_merge13 = cc.newLabel();
-                auto label_merge = cc.newLabel();
+                auto tmp_reg13 = get_reg(cc, 8, false);
-                auto tmp_reg = get_reg_for(cc, 1);
                 cmp(cc, gen_ext(cc, 
                     load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(cc, 
                     load_reg_from_mem(jh, traits::X0 + rs2), 32, true));
-                cc.jl(label_then);
+                cc.jl(label_then13);
-                mov(cc, tmp_reg,0);
+                mov(cc, tmp_reg13,0);
-                cc.jmp(label_merge);
+                cc.jmp(label_merge13);
-                cc.bind(label_then);
+                cc.bind(label_then13);
-                mov(cc, tmp_reg,1);
+                mov(cc, tmp_reg13, 1);
-                cc.bind(label_merge);
+                cc.bind(label_merge13);
                 mov(cc, get_ptr_for(jh, traits::X0+ rd),
-                      gen_ext(cc, tmp_reg
+                      gen_ext(cc, tmp_reg13
                       , 32, false)
                 );
-                }
             }
         }
         auto returnValue = CONT;
@@ -2056,22 +2050,20 @@ private:
         }
         else{
             if(rd!=0){
-                {
+                auto label_then14 = cc.newLabel();
-                auto label_then = cc.newLabel();
+                auto label_merge14 = cc.newLabel();
-                auto label_merge = cc.newLabel();
+                auto tmp_reg14 = get_reg(cc, 8, false);
-                auto tmp_reg = get_reg_for(cc, 1);
                 cmp(cc, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2));
-                cc.jb(label_then);
+                cc.jb(label_then14);
-                mov(cc, tmp_reg,0);
+                mov(cc, tmp_reg14,0);
-                cc.jmp(label_merge);
+                cc.jmp(label_merge14);
-                cc.bind(label_then);
+                cc.bind(label_then14);
-                mov(cc, tmp_reg,1);
+                mov(cc, tmp_reg14, 1);
-                cc.bind(label_merge);
+                cc.bind(label_merge14);
                 mov(cc, get_ptr_for(jh, traits::X0+ rd),
-                      gen_ext(cc, tmp_reg
+                      gen_ext(cc, tmp_reg14
                       , 32, false)
                 );
-                }
             }
         }
         auto returnValue = CONT;
@@ -2511,10 +2503,10 @@ private:
         gen_instr_prologue(jh);
         cc.comment("//behavior:");
         /*generate behavior*/
-        InvokeNode* call_wait;
+        InvokeNode* call_wait_15;
         jh.cc.comment("//call_wait");
-        jh.cc.invoke(&call_wait, &wait, FuncSignature::build<void, int32_t>());
+        jh.cc.invoke(&call_wait_15, &wait, FuncSignature::build<void, int32_t>());
-        setArg(call_wait, 0, 1);
+        setArg(call_wait_15, 0, 1);
         auto returnValue = CONT;
         
         gen_sync(jh, POST_SYNC, 41);
@@ -4830,6 +4822,7 @@ void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
     cmp(cc, current_trap_state, 0);
     cc.jne(jh.trap_entry);
     cc.inc(get_ptr_for(jh, traits::ICOUNT));
+    cc.inc(get_ptr_for(jh, traits::CYCLE));
 }
 template <typename ARCH>
 void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
@@ -4875,6 +4868,7 @@ inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t
     auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
     mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
     mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);
+    cc.jmp(jh.trap_entry);
 }
 template <typename ARCH>
 template <typename T, typename>

src/vm/fp_functions.cpp

@@ -203,8 +203,8 @@ uint32_t fclass_s(uint32_t v1) {
     uA.f = a;
     uiA = uA.ui;
 
-    uint_fast16_t infOrNaN = expF32UI(uiA) == 0xFF;
+    bool infOrNaN = expF32UI(uiA) == 0xFF;
-    uint_fast16_t subnormalOrZero = expF32UI(uiA) == 0;
+    bool subnormalOrZero = expF32UI(uiA) == 0;
     bool sign = signF32UI(uiA);
     bool fracZero = fracF32UI(uiA) == 0;
     bool isNaN = isNaNF32UI(uiA);
@@ -217,9 +217,13 @@ uint32_t fclass_s(uint32_t v1) {
 }
 
 uint32_t fconv_d2f(uint64_t v1, uint8_t mode) {
+    bool isNan = isNaNF64UI(v1);
+    bool isSNaN = softfloat_isSigNaNF64UI(v1);
     softfloat_roundingMode = rmm_map.at(mode);
-    bool nan = (v1 & defaultNaNF64UI) == defaultNaNF64UI;
+    softfloat_exceptionFlags = 0;
-    if(nan) {
+    if(isNan) {
+        if(isSNaN)
+            softfloat_raiseFlags(softfloat_flag_invalid);
         return defaultNaNF32UI;
     } else {
         float32_t res = f64_to_f32(float64_t{v1});
@@ -228,11 +232,11 @@ uint32_t fconv_d2f(uint64_t v1, uint8_t mode) {
 }
 
 uint64_t fconv_f2d(uint32_t v1, uint8_t mode) {
-    bool nan = (v1 & defaultNaNF32UI) == defaultNaNF32UI;
+    bool infOrNaN = expF32UI(v1) == 0xFF;
-    if(nan) {
+    bool subnormalOrZero = expF32UI(v1) == 0;
+    if(infOrNaN || subnormalOrZero) {
         return defaultNaNF64UI;
     } else {
-        softfloat_roundingMode = rmm_map.at(mode);
         float64_t res = f32_to_f64(float32_t{v1});
         return res.v;
     }
@@ -312,22 +316,23 @@ uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op) {
 }
 
 uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode) {
+
     float64_t v1f{v1};
     softfloat_exceptionFlags = 0;
     float64_t r;
     switch(op) {
-    case 0: { // l->d, fp to int32
+    case 0: { // l from d
         int64_t res = f64_to_i64(v1f, rmm_map.at(mode), true);
         return (uint64_t)res;
     }
-    case 1: { // lu->s
+    case 1: { // lu from d
         uint64_t res = f64_to_ui64(v1f, rmm_map.at(mode), true);
         return res;
     }
-    case 2: // s->l
+    case 2: // d from l
         r = i64_to_f64(v1);
         return r.v;
-    case 3: // s->lu
+    case 3: // d from lu
         r = ui64_to_f64(v1);
         return r.v;
     }
@@ -335,12 +340,24 @@ uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode) {
 }
 
 uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode) {
-    // op should be {softfloat_mulAdd_subProd(2), softfloat_mulAdd_subC(1)}
+    uint64_t F64_SIGN = 1ULL << 63;
+    switch(op) {
+    case 0: // FMADD_D
+        break;
+    case 1: // FMSUB_D
+        v3 ^= F64_SIGN;
+        break;
+    case 2: // FNMADD_D
+        v1 ^= F64_SIGN;
+        v3 ^= F64_SIGN;
+        break;
+    case 3: // FNMSUB_D
+        v1 ^= F64_SIGN;
+        break;
+    }
     softfloat_roundingMode = rmm_map.at(mode);
     softfloat_exceptionFlags = 0;
-    float64_t res = softfloat_mulAddF64(v1, v2, v3, op & 0x1);
+    float64_t res = softfloat_mulAddF64(v1, v2, v3, 0);
-    if(op > 1)
-        res.v ^= 1ULL << 63;
     return res.v;
 }
 
@@ -376,8 +393,8 @@ uint64_t fclass_d(uint64_t v1) {
     uA.f = a;
     uiA = uA.ui;
 
-    uint_fast16_t infOrNaN = expF64UI(uiA) == 0x7FF;
+    bool infOrNaN = expF64UI(uiA) == 0x7FF;
-    uint_fast16_t subnormalOrZero = expF64UI(uiA) == 0;
+    bool subnormalOrZero = expF64UI(uiA) == 0;
     bool sign = signF64UI(uiA);
     bool fracZero = fracF64UI(uiA) == 0;
     bool isNaN = isNaNF64UI(uiA);

src/vm/interp/vm_tgc5c.cpp

@@ -333,10 +333,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
     while(!this->core.should_stop() &&
             !(is_icount_limit_enabled(cond) && icount >= count_limit) &&
             !(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
-        fetch_count++;
+        if(this->debugging_enabled())
+            this->tgt_adapter->check_continue(*PC);
+        pc.val=*PC;
         if(fetch_ins(pc, data)!=iss::Ok){
-            this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
+            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
-            pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
+            process_spawn_blocks();
+            if(this->sync_exec && POST_SYNC) this->do_sync(PRE_SYNC, std::numeric_limits<unsigned>::max());
+            pc.val = super::core.enter_trap(arch::traits<ARCH>::RV_CAUSE_FETCH_ACCESS<<16, pc.val, 0);
         } else {
             if (is_jump_to_self_enabled(cond) &&
                     (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
@@ -2673,11 +2677,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 icount++;
                 instret++;
             }
-            cycle++;
+            *PC = *NEXT_PC;
-            pc.val=*NEXT_PC;
-            this->core.reg.PC = this->core.reg.NEXT_PC;
             this->core.reg.trap_state =  this->core.reg.pending_trap;
         }
+        fetch_count++;
+        cycle++;
     }
     return pc;
 }

src/vm/llvm/vm_tgc5c.cpp

@@ -1490,7 +1490,7 @@ private:
                 ),
                 this->gen_const(8,1),
                 this->gen_const(8,0),
-                1), 32),
+                8), 32),
                 get_reg_ptr(rd + traits::X0), false);
             }
         }
@@ -1543,7 +1543,7 @@ private:
                 ),
                 this->gen_const(8,1),
                 this->gen_const(8,0),
-                1), 32),
+                8), 32),
                 get_reg_ptr(rd + traits::X0), false);
             }
         }
@@ -2057,7 +2057,7 @@ private:
                 ,
                 this->gen_const(8,1),
                 this->gen_const(8,0),
-                1), 32),
+                8), 32),
                 get_reg_ptr(rd + traits::X0), false);
             }
         }
@@ -2110,7 +2110,7 @@ private:
                 ,
                 this->gen_const(8,1),
                 this->gen_const(8,0),
-                1), 32),
+                8), 32),
                 get_reg_ptr(rd + traits::X0), false);
             }
         }
@@ -2553,11 +2553,10 @@ private:
         
         this->gen_instr_prologue();
         /*generate behavior*/
-        auto wait_arg0 = this->gen_const(8,1);
+        std::vector<Value*> wait_231_args{
-        std::vector<Value*> wait_args{
+            this->gen_ext(this->gen_const(8,1), 32)
-            wait_arg0
         };
-        this->builder.CreateCall(this->mod->getFunction("wait"), wait_args);
+        this->builder.CreateCall(this->mod->getFunction("wait"), wait_231_args);
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
         auto returnValue = std::make_tuple(CONT,bb);
         
@@ -2719,7 +2718,7 @@ private:
                 csr,
                 this->builder.CreateAnd(
                    xrd,
-                   this->builder.CreateNeg(xrs1))
+                   this->builder.CreateNot(xrs1))
                 );
             }
             if(rd!=0) {
@@ -4898,7 +4897,7 @@ private:
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
+        this->gen_sync(iss::PRE_SYNC, instr_descr.size());
         this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
                                    get_reg_ptr(traits::PC), true);
         this->builder.CreateStore(
@@ -4973,6 +4972,7 @@ template <typename ARCH>
 void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
     auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
     this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
+    this->builder.CreateBr(this->trap_blk);
 }
 
 template <typename ARCH>
@@ -5075,4 +5075,4 @@ volatile std::array<bool, 2> dummy = {
 };
 }
 }
-// clang-format on
+// clang-format on

src/vm/tcc/vm_tgc5c.cpp

@@ -474,15 +474,19 @@ private:
         	tu.open_if(tu.urem(
         	   new_pc,
         	   tu.constant(static_cast<uint32_t>(traits:: INSTR_ALIGNMENT),32)));
+        	{
         	this->gen_set_tval(tu, new_pc);
         	this->gen_raise_trap(tu, 0, 0);
+        	}
         	tu.open_else();
+        	{
         	if(rd!=0) {
         	    tu.store(rd + traits::X0, tu.constant((uint32_t)(PC+4),32));
         	}
         	auto PC_val_v = tu.assignment("PC_val", new_pc,32);
         	tu.store(traits::NEXT_PC, PC_val_v);
         	tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 2));
+        	}
         	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
@@ -521,6 +525,7 @@ private:
         	tu.open_if(tu.icmp(ICmpInst::ICMP_EQ,
         	   tu.load(rs1 + traits::X0, 0),
         	   tu.load(rs2 + traits::X0, 0)));
+        	{
         	auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm));
         	if(new_pc%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_set_tval(tu, new_pc);
         	this->gen_raise_trap(tu, 0, 0);
@@ -530,6 +535,7 @@ private:
         		tu.store(traits::NEXT_PC, PC_val_v);
         		tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
         	}
+        	}
         	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
@@ -568,6 +574,7 @@ private:
         	tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
         	   tu.load(rs1 + traits::X0, 0),
         	   tu.load(rs2 + traits::X0, 0)));
+        	{
         	auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm));
         	if(new_pc%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_set_tval(tu, new_pc);
         	this->gen_raise_trap(tu, 0, 0);
@@ -577,6 +584,7 @@ private:
         		tu.store(traits::NEXT_PC, PC_val_v);
         		tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
         	}
+        	}
         	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
@@ -615,6 +623,7 @@ private:
         	tu.open_if(tu.icmp(ICmpInst::ICMP_SLT,
         	   tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
         	   tu.ext(tu.load(rs2 + traits::X0, 0),32,true)));
+        	{
         	auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm));
         	if(new_pc%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_set_tval(tu, new_pc);
         	this->gen_raise_trap(tu, 0, 0);
@@ -624,6 +633,7 @@ private:
         		tu.store(traits::NEXT_PC, PC_val_v);
         		tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
         	}
+        	}
         	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
@@ -662,6 +672,7 @@ private:
         	tu.open_if(tu.icmp(ICmpInst::ICMP_SGE,
         	   tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
         	   tu.ext(tu.load(rs2 + traits::X0, 0),32,true)));
+        	{
         	auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm));
         	if(new_pc%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_set_tval(tu, new_pc);
         	this->gen_raise_trap(tu, 0, 0);
@@ -671,6 +682,7 @@ private:
         		tu.store(traits::NEXT_PC, PC_val_v);
         		tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
         	}
+        	}
         	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
@@ -709,6 +721,7 @@ private:
         	tu.open_if(tu.icmp(ICmpInst::ICMP_ULT,
         	   tu.load(rs1 + traits::X0, 0),
         	   tu.load(rs2 + traits::X0, 0)));
+        	{
         	auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm));
         	if(new_pc%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_set_tval(tu, new_pc);
         	this->gen_raise_trap(tu, 0, 0);
@@ -718,6 +731,7 @@ private:
         		tu.store(traits::NEXT_PC, PC_val_v);
         		tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
         	}
+        	}
         	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
@@ -756,6 +770,7 @@ private:
         	tu.open_if(tu.icmp(ICmpInst::ICMP_UGE,
         	   tu.load(rs1 + traits::X0, 0),
         	   tu.load(rs2 + traits::X0, 0)));
+        	{
         	auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm));
         	if(new_pc%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_set_tval(tu, new_pc);
         	this->gen_raise_trap(tu, 0, 0);
@@ -765,6 +780,7 @@ private:
         		tu.store(traits::NEXT_PC, PC_val_v);
         		tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
         	}
+        	}
         	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
@@ -2417,6 +2433,7 @@ private:
         	if(rd!=0){ tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
         	   divisor,
         	   tu.constant(0,8)));
+        	{
         	auto MMIN = ((uint32_t)1)<<(static_cast<uint32_t>(traits:: XLEN)-1);
         	tu.open_if(tu.logical_and(
         	   tu.icmp(ICmpInst::ICMP_EQ,
@@ -2425,14 +2442,21 @@ private:
         	   tu.icmp(ICmpInst::ICMP_EQ,
         	      divisor,
         	      tu.constant(- 1,8))));
+        	{
         	tu.store(rd + traits::X0, tu.constant(MMIN,32));
+        	}
         	tu.open_else();
+        	{
         	tu.store(rd + traits::X0, tu.ext((tu.sdiv(
         	   dividend,
         	   divisor)),32,false));
+        	}
         	tu.close_scope();
+        	}
         	tu.open_else();
+        	{
         	tu.store(rd + traits::X0, tu.constant((uint32_t)- 1,32));
+        	}
         	tu.close_scope();
         	}
         }
@@ -2471,15 +2495,19 @@ private:
         	tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
         	   tu.load(rs2 + traits::X0, 0),
         	   tu.constant(0,8)));
+        	{
         	if(rd!=0) {
         	    tu.store(rd + traits::X0, tu.udiv(
         	       tu.load(rs1 + traits::X0, 0),
         	       tu.load(rs2 + traits::X0, 0)));
         	}
+        	}
         	tu.open_else();
+        	{
         	if(rd!=0) {
         	    tu.store(rd + traits::X0, tu.constant((uint32_t)- 1,32));
         	}
+        	}
         	tu.close_scope();
         }
         auto returnValue = std::make_tuple(CONT);
@@ -2517,6 +2545,7 @@ private:
         	tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
         	   tu.load(rs2 + traits::X0, 0),
         	   tu.constant(0,8)));
+        	{
         	auto MMIN = (uint32_t)1<<(static_cast<uint32_t>(traits:: XLEN)-1);
         	tu.open_if(tu.logical_and(
         	   tu.icmp(ICmpInst::ICMP_EQ,
@@ -2525,20 +2554,27 @@ private:
         	   tu.icmp(ICmpInst::ICMP_EQ,
         	      tu.ext(tu.load(rs2 + traits::X0, 0),32,true),
         	      tu.constant(- 1,8))));
+        	{
         	if(rd!=0) {
         	    tu.store(rd + traits::X0, tu.constant(0,8));
         	}
+        	}
         	tu.open_else();
+        	{
         	if(rd!=0) {
         	    tu.store(rd + traits::X0, tu.ext((tu.srem(
         	       tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
         	       tu.ext(tu.load(rs2 + traits::X0, 0),32,true))),32,false));
         	}
+        	}
         	tu.close_scope();
+        	}
         	tu.open_else();
+        	{
         	if(rd!=0) {
         	    tu.store(rd + traits::X0, tu.load(rs1 + traits::X0, 0));
         	}
+        	}
         	tu.close_scope();
         }
         auto returnValue = std::make_tuple(CONT);
@@ -2576,15 +2612,19 @@ private:
         	tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
         	   tu.load(rs2 + traits::X0, 0),
         	   tu.constant(0,8)));
+        	{
         	if(rd!=0) {
         	    tu.store(rd + traits::X0, tu.urem(
         	       tu.load(rs1 + traits::X0, 0),
         	       tu.load(rs2 + traits::X0, 0)));
         	}
+        	}
         	tu.open_else();
+        	{
         	if(rd!=0) {
         	    tu.store(rd + traits::X0, tu.load(rs1 + traits::X0, 0));
         	}
+        	}
         	tu.close_scope();
         }
         auto returnValue = std::make_tuple(CONT);
@@ -3185,9 +3225,11 @@ private:
         tu.open_if(tu.icmp(ICmpInst::ICMP_EQ,
            tu.load(rs1+8 + traits::X0, 0),
            tu.constant(0,8)));
+        {
         auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<9>(imm)),32);
         tu.store(traits::NEXT_PC, PC_val_v);
         tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
+        }
         tu.close_scope();
         auto returnValue = std::make_tuple(BRANCH);
         
@@ -3220,9 +3262,11 @@ private:
         tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
            tu.load(rs1+8 + traits::X0, 0),
            tu.constant(0,8)));
+        {
         auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<9>(imm)),32);
         tu.store(traits::NEXT_PC, PC_val_v);
         tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
+        }
         tu.close_scope();
         auto returnValue = std::make_tuple(BRANCH);