fixes use of icount vs. cycle
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9de0aed84d
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64329cf0f6
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@ -278,7 +278,7 @@ public:
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void disass_output(uint64_t pc, const std::string instr) override {
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NSCLOG(INFO, LOGCAT) << fmt::format("0x{:016x} {:40} [s:0x{:x};c:{}]", pc, instr, (reg_t)state.mstatus,
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this->reg.icount + cycle_offset);
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this->reg.cycle + cycle_offset);
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};
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iss::instrumentation_if* get_instrumentation_if() override { return &instr_if; }
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@ -311,7 +311,7 @@ protected:
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uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
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uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
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uint64_t get_total_cycles() override { return arch.reg.cycle + arch.cycle_offset; }
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void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
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@ -908,7 +908,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_plain(unsigned addr, reg_t
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template <typename BASE, features_e FEAT, typename LOGCAT>
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iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_cycle(unsigned addr, reg_t& val) {
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auto cycle_val = this->reg.icount + cycle_offset;
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auto cycle_val = this->reg.cycle + cycle_offset;
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if(addr == mcycle) {
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val = static_cast<reg_t>(cycle_val);
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} else if(addr == mcycleh) {
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@ -928,7 +928,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_cycle(unsigned addr, reg_t
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mcycle_csr = (static_cast<uint64_t>(val) << 32) + (mcycle_csr & 0xffffffff);
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}
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}
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cycle_offset = mcycle_csr - this->reg.icount; // TODO: relying on wrap-around
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cycle_offset = mcycle_csr - this->reg.cycle; // TODO: relying on wrap-around
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return iss::Ok;
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}
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@ -959,7 +959,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_instret(unsigned addr, reg
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template <typename BASE, features_e FEAT, typename LOGCAT>
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iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_time(unsigned addr, reg_t& val) {
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uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
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uint64_t time_val = this->reg.cycle / (100000000 / 32768 - 1); //-> ~3052;
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if(addr == time) {
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val = static_cast<reg_t>(time_val);
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} else if(addr == timeh) {
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@ -328,7 +328,7 @@ public:
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void disass_output(uint64_t pc, const std::string instr) override {
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CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus,
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this->reg.icount + cycle_offset);
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this->reg.cycle + cycle_offset);
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};
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iss::instrumentation_if* get_instrumentation_if() override { return &instr_if; }
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@ -361,7 +361,7 @@ protected:
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uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
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uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
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uint64_t get_total_cycles() override { return arch.reg.cycle + arch.cycle_offset; }
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void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
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@ -895,7 +895,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_reg(unsigned
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}
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template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigned addr, reg_t& val) {
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auto cycle_val = this->reg.icount + cycle_offset;
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auto cycle_val = this->reg.cycle + cycle_offset;
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if(addr == mcycle) {
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val = static_cast<reg_t>(cycle_val);
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} else if(addr == mcycleh) {
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@ -916,7 +916,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_cycle(unsign
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mcycle_csr = (static_cast<uint64_t>(val) << 32) + (mcycle_csr & 0xffffffff);
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}
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}
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cycle_offset = mcycle_csr - this->reg.icount; // TODO: relying on wrap-around
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cycle_offset = mcycle_csr - this->reg.cycle; // TODO: relying on wrap-around
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return iss::Ok;
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}
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@ -944,7 +944,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_instret(unsi
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}
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template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned addr, reg_t& val) {
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uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
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uint64_t time_val = this->reg.cycle / (100000000 / 32768 - 1); //-> ~3052;
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if(addr == time) {
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val = static_cast<reg_t>(time_val);
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} else if(addr == timeh) {
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@ -305,7 +305,7 @@ public:
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void disass_output(uint64_t pc, const std::string instr) override {
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NSCLOG(INFO, LOGCAT) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus,
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this->reg.icount + cycle_offset);
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this->reg.cycle + cycle_offset);
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};
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iss::instrumentation_if* get_instrumentation_if() override { return &instr_if; }
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@ -338,7 +338,7 @@ protected:
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uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
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uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
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uint64_t get_total_cycles() override { return arch.reg.cycle + arch.cycle_offset; }
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void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
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@ -1105,7 +1105,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_plain(unsigned addr, reg_
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template <typename BASE, features_e FEAT, typename LOGCAT>
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iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read_cycle(unsigned addr, reg_t& val) {
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auto cycle_val = this->reg.icount + cycle_offset;
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auto cycle_val = this->reg.cycle + cycle_offset;
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if(addr == mcycle) {
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val = static_cast<reg_t>(cycle_val);
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} else if(addr == mcycleh) {
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@ -1125,7 +1125,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_cycle(unsigned addr, reg_
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mcycle_csr = (static_cast<uint64_t>(val) << 32) + (mcycle_csr & 0xffffffff);
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}
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}
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cycle_offset = mcycle_csr - this->reg.icount; // TODO: relying on wrap-around
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cycle_offset = mcycle_csr - this->reg.cycle; // TODO: relying on wrap-around
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return iss::Ok;
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}
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@ -1156,7 +1156,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_instret(unsigned addr, re
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template <typename BASE, features_e FEAT, typename LOGCAT>
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iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read_time(unsigned addr, reg_t& val) {
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uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
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uint64_t time_val = this->reg.cycle / (100000000 / 32768 - 1); //-> ~3052;
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if(addr == time) {
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val = static_cast<reg_t>(time_val);
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} else if(addr == timeh) {
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