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MINRES The Good Folks Series cores ISS
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Eyck Jentzsch de79adc50d updates debugger hook to stop before fetching instructions 
this relates to https://github.com/Minres/DBT-RISE-RISCV/issues/8 :
Debugger loses control when trap vector fetch fails

and https://github.com/Minres/DBT-RISE-RISCV/issues/7 : Two debugger
single-steps are required at reset vector
 		2024-08-17 12:39:54 +02:00
cmake fixes linker isseu using whole-archive 2023-07-19 08:19:38 +02:00
contrib adds newly generated instr.yaml 2024-07-18 14:31:36 +02:00
gen_input updates debugger hook to stop before fetching instructions 2024-08-17 12:39:54 +02:00
softfloat applies clang format 2024-08-01 11:02:10 +02:00
src updates debugger hook to stop before fetching instructions 2024-08-17 12:39:54 +02:00
src-gen add generated core registration 2023-07-14 12:51:51 +02:00
.clang-format applies clang-format changes 2023-10-29 17:06:56 +01:00
.cproject reorganized layout to only contain risc-v stuff 2019-06-11 16:49:37 +00:00
.gitignore updates .gitignore 2023-10-29 17:08:18 +01:00
.project removes trace compass nature 2023-07-06 10:39:59 +02:00
CMakeLists.txt moves decoder to dbt-rise-core 2024-07-25 10:13:38 +02:00
LICENSE Initial commit 2017-08-27 13:04:48 +02:00
README.md Update TGF naming convention 2020-09-11 10:45:44 +02:00

README.md

DBT-RISE-TGFS

Core of an instruction set simulator based on DBT-RISE implementing Minres The Good Folks Series cores. The project is hosted at https://git.minres.com/DBT-RISE/DBT-RISE-TGFS .

This repo contains only the code of the RISC-V ISS and can only be used with the DBT_RISE. A complete VP using this ISS can be found at https://git.minres.com/VP/Ecosystem-VP which models SiFives FE310 controlling a brushless DC (BLDC) motor.

This library provide the infrastructure to build RISC-V ISS. Currently part of the library are the following implementations adhering to version 2.2 of the 'The RISC-V Instruction Set Manual Volume I: User-Level ISA':

  • RV32I (TGF-B)
  • RV32MIC (TGF-C)

All pass the respective compliance tests. Along with those ISA implementations there is a wrapper (riscv_hart_m_p.h) implementing the Machine privileged mode as of privileged spec 1.10. The main.cpp in src allows to build a stand-alone ISS when integrated into a top-level project. For further information please have a look at https://git.minres.com/VP/RISCV-VP.

Last but not least an SystemC wrapper is provided which allows easy integration into SystemC based virtual platforms.

Since DBT-RISE uses a generative approach other needed combinations or custom extension can be generated. For further information please contact info@minres.com.