DBT-RISE
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DBT-RISE-TGC
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Merge branch 'develop'

This commit is contained in:
Eyck Jentzsch 2022-04-23 17:06:52 +02:00
parent d5fa47ef7f 477c530847
commit 1196424e39
27 changed files with 3188 additions and 4612 deletions
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1
.gitignore vendored
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@ -32,3 +32,4 @@ language.settings.xml
/dump.json
/src-gen/
/*.yaml
/*.json

3
.gitmodules vendored
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@ -1,3 +0,0 @@
[submodule "gen_input/CoreDSL-Instruction-Set-Description"]
path = gen_input/CoreDSL-Instruction-Set-Description
url = ../CoreDSL-Instruction-Set-Description.git

48
CMakeLists.txt
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@ -6,7 +6,8 @@ project(dbt-rise-tgc VERSION 1.0.0)
include(GNUInstallDirs)
find_package(elfio)
find_package(elfio QUIET)
find_package(Boost COMPONENTS coroutine)
if(WITH_LLVM)
if(DEFINED ENV{LLVM_HOME})
@ -28,16 +29,19 @@ endif()
add_subdirectory(softfloat)
# library files
FILE(GLOB TGC_SOURCES
${CMAKE_CURRENT_SOURCE_DIR}/src/iss/*.cpp
${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp
)
FILE(GLOB TGC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src/iss/*.cpp)
FILE(GLOB TGC_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp)
set(LIB_SOURCES
src/vm/fp_functions.cpp
src/plugin/instruction_count.cpp
src/plugin/cycle_estimate.cpp
${TGC_SOURCES}
${TGC_VM_SOURCES}
)
if(TARGET RapidJSON)
list(APPEND LIB_SOURCES src/plugin/cycle_estimate.cpp src/plugin/pctrace.cpp)
endif()
if(WITH_LLVM)
FILE(GLOB TGC_LLVM_SOURCES
@ -66,11 +70,11 @@ elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
endif()
target_include_directories(${PROJECT_NAME} PUBLIC incl)
target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp)
target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp Boost::coroutine)
if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-rise-core -Wl,--no-whole-archive)
else()
target_link_libraries(${PROJECT_NAME} PUBLIC dbt-core)
target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-core)
endif()
if(TARGET CONAN_PKG::elfio)
target_link_libraries(${PROJECT_NAME} PUBLIC CONAN_PKG::elfio)
@ -79,6 +83,10 @@ elseif(TARGET elfio::elfio)
else()
message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
endif()
if(TARGET RapidJSON)
target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON)
endif()
set_target_properties(${PROJECT_NAME} PROPERTIES
VERSION ${PROJECT_VERSION}
@ -105,8 +113,12 @@ project(tgc-sim)
find_package(Boost COMPONENTS program_options thread REQUIRED)
add_executable(${PROJECT_NAME} src/main.cpp)
# This sets the include directory for the reference project. This is the -I flag in gcc.
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
foreach(F IN LISTS TGC_SOURCES)
string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
endforeach()
if(WITH_LLVM)
target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
@ -142,15 +154,11 @@ if(SystemC_FOUND)
add_library(${PROJECT_NAME} src/sysc/core_complex.cpp)
target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_b.h)
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_B)
endif()
if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_c.h)
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_C)
endif()
if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_d.h)
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_D)
endif()
foreach(F IN LISTS TGC_SOURCES)
string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
endforeach()
target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
if(WITH_LLVM)
target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})

1
gen_input/.gitignore vendored
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@ -1 +1,2 @@
/src-gen/
/CoreDSL-Instruction-Set-Description

1
gen_input/CoreDSL-Instruction-Set-Description

@ -1 +0,0 @@
Subproject commit b005607fc30c4467683b6044eaca7eb378061b53

14
gen_input/TGC_B.core_desc
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@ -1,14 +0,0 @@
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGC_B provides RV32I, Zicsr, Zifencei {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000000000100000000;
unsigned MARCHID_VAL = 0x80000002;
}
}

13
gen_input/TGC_D.core_desc
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@ -1,13 +0,0 @@
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGC_D provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000100000011000100000100;
unsigned MARCHID_VAL = 0x80000004;
}
}

73
gen_input/TGC_D_XRB_MAC.core_desc
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@ -1,73 +0,0 @@
import "CoreDSL-Instruction-Set-Description/RISCVBase.core_desc"
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
InstructionSet X_RB_MAC extends RISCVBase {
architectural_state {
register unsigned<64> ACC;
}
instructions {
RESET_ACC { // v-- funct7 v-- funct3
encoding: 7'd0 :: 10'b0 :: 3'd0 :: 5'b0 :: 7'b0001011;
behavior: ACC = 0;
}
GET_ACC_LO {
encoding: 7'd1 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
behavior: if (rd != 0) X[rd] = ACC[31:0];
}
GET_ACC_HI {
encoding: 7'd2 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
behavior: if (rd != 0) X[rd] = ACC[63:32];
}
MACU_32 {
encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
behavior: {
unsigned<64> mul = X[rs1] * X[rs2];
unsigned<33> add = mul[31:0] + ACC[31:0];
ACC = add[31:0];
}
}
MACS_32 {
encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
behavior: {
signed<64> mul = ((signed) X[rs1]) * ((signed) X[rs2]);
signed<33> add = ((signed) mul[31:0]) + ((signed) ACC[31:0]);
ACC = add[31:0]; // bit range always yields unsigned type
}
}
MACU_64 {
encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
behavior: {
unsigned<64> mul = X[rs1] * X[rs2];
unsigned<65> add = mul + ACC;
ACC = add[63:0];
}
}
MACS_64 {
encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
behavior: {
signed<64> mul = ((signed) X[rs1]) * ((signed) X[rs2]);
signed<65> add = mul + ((signed) ACC);
ACC = add[63:0];
}
}
}
}
Core TGC_D_XRB_MAC provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_MAC {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
unsigned MARCHID_VAL = 0x80000004;
}
}

133
gen_input/TGC_D_XRB_NN.core_desc
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@ -1,133 +0,0 @@
import "CoreDSL-Instruction-Set-Description/RISCVBase.core_desc"
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
InstructionSet X_RB_NN extends RISCVBase {
instructions {
// signed saturate with pre-shift
SSAT {
// instruction format: R-type
// opcode space: custom-1 (inst[6:2] = 01010)
// opcode = 0b0101011, func3 = 0b000, func7 = <bit position to saturate to>
encoding: sat_bit_pos[6:0] :: rs2[4:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0101011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}, {name(sat_bit_pos)}";
behavior: {
signed<XLEN> val_s = (signed<XLEN>)X[rs1];
unsigned<XLEN> pre_shift = (unsigned<XLEN>)X[rs2];
unsigned<XLEN> sat_limit;
signed<XLEN> upper_limit;
signed<XLEN> lower_limit;
if((rd != 0) && (sat_bit_pos > 0) && (sat_bit_pos <= 32) && (pre_shift < 32)) {
sat_limit = (unsigned<XLEN>)(1 << (sat_bit_pos - 1));
upper_limit = (signed)sat_limit - 1;
lower_limit = (signed)sat_limit * (-1);
// important: arithmetical shift right
val_s = val_s >> pre_shift;
X[rd] = (val_s > upper_limit) ? (upper_limit) : ( (val_s < lower_limit) ? (lower_limit) : (val_s) );
}
}
}
// custom packed dot product with accumulation (4x8bit)
PDOT8 {
// instruction format: R-type
// opcode space: custom-1 (inst[6:2] = 01010)
// opcode = 0b0101011, func3 = 0b001, func7 = 0b0000000
encoding: 0b0000000 :: rs2[4:0] :: rs1[4:0] :: 0b001 :: rd[4:0] :: 0b0101011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: {
signed<8> op1_0 = (signed<8>)X[rs1][ 7: 0];
signed<8> op1_1 = (signed<8>)X[rs1][15: 8];
signed<8> op1_2 = (signed<8>)X[rs1][23:16];
signed<8> op1_3 = (signed<8>)X[rs1][31:24];
signed<8> op2_0 = (signed<8>)X[rs2][ 7: 0];
signed<8> op2_1 = (signed<8>)X[rs2][15: 8];
signed<8> op2_2 = (signed<8>)X[rs2][23:16];
signed<8> op2_3 = (signed<8>)X[rs2][31:24];
signed<XLEN> op3 = (signed<XLEN>)X[rd];
signed<16> mul0 = op1_0 * op2_0;
signed<16> mul1 = op1_1 * op2_1;
signed<16> mul2 = op1_2 * op2_2;
signed<16> mul3 = op1_3 * op2_3;
signed<19> sum_tmp = mul0 + mul1 + mul2 + mul3;
signed<33> result = op3 + sum_tmp;
if(rd != 0) X[rd] = result[31:0];
}
}
// standard signed multiply accumulate with 32 bit operands and 32 bit result
MAC {
// instruction format: R-type
// opcode space: custom-1 (inst[6:2] = 01010)
// opcode = 0b0101011, func3 = 0b010, func7 = 0b0000000
encoding: 0b0000000 :: rs2[4:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0101011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: {
signed<65> result = (signed)X[rs1] * (signed)X[rs2] + (signed)X[rd];
if(rd != 0) X[rd] = result[31:0];
}
}
// WARNING: The following two HW loop instructions are not fully specified or implemented. The idea is to design the HW loops identical to the RI5CY core (current naming: CV32E40P)
// See "Short Hardware Loop Setup Instructions" from RI5CY specification document from April 2019, revision 4.0: https://www.pulp-platform.org/docs/ri5cy_user_manual.pdf -> page 38, chapter 14.2
// Specific CSRs are introduced to support the HW loops (see page 17, chapter 7).
// lp.setup HW loop (Short Hardware Loop Setup Instruction)
LOOP {
// instruction format: I-type
// opcode space: custom-3 (inst[6:2] = 11110)
// opcode = 0b1111011, func3 = 0b100
// uimmL[11:0] src1 100 0000 L 111 1011 -> lp.setup L,rs1, uimmL
encoding: imm[11:0] :: rs1[4:0] :: 0b100 :: 0b0000 :: L[0:0] :: 0b1111011;
args_disass:"{name(L)}, {name(rs1)}, {imm}";
behavior: {
// L: loop level (two loop levels would be sufficient); L=0 has higher priority and is considered as the inner loop.
/*
lpstart[L] = PC + 4;
lpend[L] = PC + ((unsigned<12>)imm << 1);
lpcount[L] = rs1;
*/
}
}
// lp.setupi HW loop (Short Hardware Loop Setup Instruction with immediate value for loop count)
LOOPI {
// instruction format: I-type
// opcode space: custom-3 (inst[6:2] = 11110)
// opcode = 0b1111011, func3 = 0b101
// uimmL[11:0] uimmS[4:0] 101 0000 L 111 1011 -> lp.setupi L, uimmS, uimmL
encoding: imm2[11:0] :: imm1[4:0] :: 0b101 :: 0b0000 :: L[0:0] :: 0b1111011;
args_disass:"{name(L)}, {imm1}, {imm2}";
behavior: {
// L: loop level (two loop levels would be sufficient); L=0 has higher priority and is considered as the inner loop.
/*
lpstart[L] = PC + 4;
lpend[L] = PC + ((unsigned<5>)imm1 << 1);
lpcount[L] = (unsigned<12>)imm2;
*/
}
}
}
}
Core TGC_D_XRB_NN provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_NN {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000100100000011000100000100;
unsigned MARCHID_VAL = 0x80000004;
}
}

3
gen_input/templates/CORENAME.h.gtl
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@ -161,7 +161,7 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
inline uint32_t get_last_branch() { return reg.last_branch; }
protected:
#pragma pack(push, 1)
struct ${coreDef.name}_regs {<%
registers.each { reg -> if(reg.size>0) {%>
@ -169,7 +169,6 @@ protected:
}}%>
uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0;
uint64_t cycle = 0;
uint64_t instret = 0;
uint32_t last_branch;
} reg;

11
gen_input/templates/CORENAME_cyles.txt.gtl
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@ -1,9 +1,12 @@
{
{
"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
{
"name" : "${instr.name}",
"size" : ${instr.length},
"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
"name" : "${instr.name}",
"size" : ${instr.length},
"encoding": "${instr.encoding}",
"mask": "${instr.mask}",
"branch": ${instr.modifiesPC},
"delay" : ${instr.isConditional?"[1,1]":"1"}
}<%}%>
]
}

159
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -45,6 +45,8 @@ def nativeTypeSize(int size){
#include <iss/interp/vm_base.h>
#include <util/logging.h>
#include <sstream>
#include <boost/coroutine2/all.hpp>
#include <functional>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
@ -59,6 +61,7 @@ namespace interp {
namespace ${coreDef.name.toLowerCase()} {
using namespace iss::arch;
using namespace iss::debugger;
using namespace std::placeholders;
template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
public:
@ -91,7 +94,7 @@ protected:
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
compile_func decode_inst(code_word_t instr) ;
typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
// some compile time constants
@ -111,7 +114,7 @@ protected:
struct instruction_pattern {
uint32_t value;
uint32_t mask;
compile_func opc;
typename arch::traits<ARCH>::opcode_e id;
};
std::array<std::vector<instruction_pattern>, 4> qlut;
@ -130,6 +133,10 @@ protected:
this->core.wait_until(type);
}
using yield_t = boost::coroutines2::coroutine<void>::push_type;
using coro_t = boost::coroutines2::coroutine<void>::pull_type;
std::vector<coro_t> spawn_blocks;
template<typename T>
T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
@ -174,7 +181,18 @@ protected:
auto sign_mask = 1ULL<<(W-1);
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
}
inline void process_spawn_blocks() {
for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
if(*it){
(*it)();
++it;
} else
spawn_blocks.erase(it);
}
<%functions.each{ it.eachLine { %>
${it}<%}%>
<%}%>
private:
/****************************************************************************
* start opcode definitions
@ -183,74 +201,13 @@ private:
size_t length;
uint32_t value;
uint32_t mask;
compile_func op;
typename arch::traits<ARCH>::opcode_e op;
};
const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name} */
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
{${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
}};
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
/* instruction ${idx}: ${instr.name} */
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
// pre execution stuff
auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
auto NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
*PC=*NEXT_PC;
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
*trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, ${idx});
<%instr.fields.eachLine{%>${it}
<%}%>if(this->disass_enabled){
/* generate console output when executing the command */
<%instr.disass.eachLine{%>${it}
<%}%>
}
// used registers<%instr.usedVariables.each{ k,v->
if(v.isArray) {%>
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
<%}}%>// calculate next pc value
*NEXT_PC = *PC + ${instr.length/8};
// execute instruction
try {
<%instr.behavior.eachLine{%>${it}
<%}%>} catch(...){}
// post execution stuff
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
// trap check
if(*trap_state!=0){
super::core.enter_trap(*trap_state, pc.val, instr);
} else {
(*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
(*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
}
(*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
pc.val=*NEXT_PC;
return pc;
}
<%}%>
/****************************************************************************
* end opcode definitions
****************************************************************************/
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
this->do_sync(PRE_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
*NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
raise(0, 2);
// post execution stuff
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
// trap check
if(*trap_state!=0){
super::core.enter_trap(*trap_state, pc.val, instr);
}
pc.val=*NEXT_PC;
return pc;
}
//static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
@ -290,6 +247,7 @@ constexpr size_t bit_count(uint32_t u) {
template <typename ARCH>
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
: vm_base<ARCH>(core, core_id, cluster_id) {
unsigned id=0;
for (auto instr : instr_descr) {
auto quadrant = instr.value & 0x3;
qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
@ -310,37 +268,82 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
}
template <typename ARCH>
typename vm_impl<ARCH>::compile_func vm_impl<ARCH>::decode_inst(code_word_t instr){
typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
for(auto& e: qlut[instr&0x3]){
if(!((instr&e.mask) ^ e.value )) return e.opc;
if(!((instr&e.mask) ^ e.value )) return e.id;
}
return &this_class::illegal_intruction;
return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
}
template <typename ARCH>
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
// we fetch at max 4 byte, alignment is 2
code_word_t insn = 0;
auto *const data = (uint8_t *)&insn;
code_word_t instr = 0;
auto *const data = (uint8_t *)&instr;
auto pc=start;
auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
auto* icount = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]);
auto* instret = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]);
while(!this->core.should_stop() &&
!(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
auto res = fetch_ins(pc, data);
if(res!=iss::Ok){
if(fetch_ins(pc, data)!=iss::Ok){
this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
} else {
if (is_jump_to_self_enabled(cond) &&
(insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
auto f = decode_inst(insn);
auto old_pc = pc.val;
pc = (this->*f)(pc, insn);
(instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
auto inst_id = decode_inst_id(instr);
// pre execution stuff
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
case arch::traits<ARCH>::opcode_e::${instr.name}: {
<%instr.fields.eachLine{%>${it}
<%}%>if(this->disass_enabled){
/* generate console output when executing the command */
<%instr.disass.eachLine{%>${it}
<%}%>
}
// used registers<%instr.usedVariables.each{ k,v->
if(v.isArray) {%>
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
<%}}%>// calculate next pc value
*NEXT_PC = *PC + ${instr.length/8};
// execute instruction
try {
<%instr.behavior.eachLine{%>${it}
<%}%>} catch(...){}
}
break;<%}%>
default: {
*NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
raise(0, 2);
}
}
// post execution stuff
process_spawn_blocks();
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
// trap check
if(*trap_state!=0){
super::core.enter_trap(*trap_state, pc.val, instr);
} else {
(*icount)++;
(*instret)++;
}
(*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
pc.val=*NEXT_PC;
this->core.reg.PC = this->core.reg.NEXT_PC;
this->core.reg.trap_state = this->core.reg.pending_trap;
}
}
return pc;
}
} // namespace mnrv32
}
template <>
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {

100
incl/iss/arch/hwl.h Normal file
View File

@ -0,0 +1,100 @@
/*******************************************************************************
* Copyright (C) 2022 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Contributors:
* eyck@minres.com - initial implementation
******************************************************************************/
#ifndef _RISCV_HART_M_P_HWL_H
#define _RISCV_HART_M_P_HWL_H
#include <iss/vm_types.h>
namespace iss {
namespace arch {
template <typename BASE> class hwl : public BASE {
public:
using base_class = BASE;
using this_class = hwl<BASE>;
using reg_t = typename BASE::reg_t;
hwl();
virtual ~hwl() = default;
protected:
iss::status read_custom_csr_reg(unsigned addr, reg_t &val) override;
iss::status write_custom_csr_reg(unsigned addr, reg_t val) override;
};
template<typename BASE>
inline hwl<BASE>::hwl() {
for (unsigned addr = 0x800; addr < 0x803; ++addr){
this->register_custom_csr_rd(addr);
this->register_custom_csr_wr(addr);
}
for (unsigned addr = 0x804; addr < 0x807; ++addr){
this->register_custom_csr_rd(addr);
this->register_custom_csr_wr(addr);
}
}
template<typename BASE>
inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t &val) {
switch(addr){
case 0x800: val = this->reg.lpstart0; break;
case 0x801: val = this->reg.lpend0; break;
case 0x802: val = this->reg.lpcount0; break;
case 0x804: val = this->reg.lpstart1; break;
case 0x805: val = this->reg.lpend1; break;
case 0x806: val = this->reg.lpcount1; break;
}
return iss::Ok;
}
template<typename BASE>
inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
switch(addr){
case 0x800: this->reg.lpstart0 = val; break;
case 0x801: this->reg.lpend0 = val; break;
case 0x802: this->reg.lpcount0 = val; break;
case 0x804: this->reg.lpstart1 = val; break;
case 0x805: this->reg.lpend1 = val; break;
case 0x806: this->reg.lpcount1 = val; break;
}
return iss::Ok;
}
} // namespace arch
} // namespace iss
#endif /* _RISCV_HART_M_P_H */

55
incl/iss/arch/riscv_hart_common.h
View File

@ -43,7 +43,7 @@ namespace arch {
enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
enum features_e{FEAT_NONE, FEAT_PMP=1, FEAT_EXT_N=2, FEAT_CLIC=4, FEAT_DEBUG=8};
enum features_e{FEAT_NONE, FEAT_PMP=1, FEAT_EXT_N=2, FEAT_CLIC=4, FEAT_DEBUG=8, FEAT_TCM=16};
enum riscv_csr {
/* user-level CSR */
@ -188,7 +188,7 @@ enum {
template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3 };
enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3, PRIV_D = 4};
enum {
ISA_A = 1,
@ -214,6 +214,14 @@ struct vm_info {
bool is_active() { return levels; }
};
struct feature_config {
uint64_t clic_base{0xc0000000};
unsigned clic_num_irq{16};
unsigned clic_num_trigger{0};
uint64_t tcm_base{0x10000000};
uint64_t tcm_size{0x8000};
};
class trap_load_access_fault : public trap_access {
public:
trap_load_access_fault(uint64_t badaddr)
@ -239,6 +247,49 @@ public:
trap_store_page_fault(uint64_t badaddr)
: trap_access(15 << 16, badaddr) {}
};
inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t *const data, unsigned length) {
auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
switch (offs & 0x3) {
case 0:
for (auto i = 0U; i < length; ++i)
*(data + i) = *(reg_ptr + i);
break;
case 1:
for (auto i = 0U; i < length; ++i)
*(data + i) = *(reg_ptr + 1 + i);
break;
case 2:
for (auto i = 0U; i < length; ++i)
*(data + i) = *(reg_ptr + 2 + i);
break;
case 3:
*data = *(reg_ptr + 3);
break;
}
}
inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t *const data, unsigned length) {
auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
switch (offs & 0x3) {
case 0:
for (auto i = 0U; i < length; ++i)
*(reg_ptr + i) = *(data + i);
break;
case 1:
for (auto i = 0U; i < length; ++i)
*(reg_ptr + 1 + i) = *(data + i);
break;
case 2:
for (auto i = 0U; i < length; ++i)
*(reg_ptr + 2 + i) = *(data + i);
break;
case 3:
*(reg_ptr + 3) = *data ;
break;
}
}
}
}

198
incl/iss/arch/riscv_hart_m_p.h
View File

@ -97,8 +97,10 @@ public:
using reg_t = typename core::reg_t;
using addr_t = typename core::addr_t;
using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
using mem_read_f = iss::status(phys_addr_t addr, unsigned, uint8_t *const);
using mem_write_f = iss::status(phys_addr_t addr, unsigned, uint8_t const *const);
// primary template
template <class T, class Enable = void> struct hart_state {};
@ -201,7 +203,7 @@ public:
void disass_output(uint64_t pc, const std::string instr) override {
CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [s:0x{:x};c:{}]",
pc, instr, (reg_t)state.mstatus, this->reg.icount);
pc, instr, (reg_t)state.mstatus, this->reg.icount + cycle_offset);
};
iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
@ -218,6 +220,9 @@ public:
csr[addr & csr.page_addr_mask] = val;
}
void set_irq_num(unsigned i) {
mcause_max_irq=1<<util::ilog2(i);
}
protected:
struct riscv_instrumentation_if : public iss::instrumentation_if {
@ -230,11 +235,15 @@ protected:
*/
const std::string core_type_name() const override { return traits<BASE>::core_type; }
virtual uint64_t get_pc() { return arch.get_pc(); };
uint64_t get_pc() override { return arch.get_pc(); };
virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
uint64_t get_next_pc() override { return arch.get_next_pc(); };
virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
uint64_t get_instr_count() { return arch.reg.icount; }
uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
riscv_hart_m_p<BASE, FEAT> &arch;
};
@ -287,6 +296,8 @@ protected:
};
std::vector<clic_int_reg_t> clic_int_reg;
std::vector<uint8_t> tcm;
iss::status read_csr_reg(unsigned addr, reg_t &val);
iss::status write_csr_reg(unsigned addr, reg_t val);
iss::status read_null(unsigned addr, reg_t &val);
@ -303,7 +314,6 @@ protected:
iss::status read_ie(unsigned addr, reg_t &val);
iss::status write_ie(unsigned addr, reg_t val);
iss::status read_ip(unsigned addr, reg_t &val);
iss::status write_ip(unsigned addr, reg_t val);
iss::status read_hartid(unsigned addr, reg_t &val);
iss::status write_epc(unsigned addr, reg_t val);
iss::status write_intstatus(unsigned addr, reg_t val);
@ -314,12 +324,26 @@ protected:
iss::status read_dpc_reg(unsigned addr, reg_t &val);
iss::status write_dpc_reg(unsigned addr, reg_t val);
virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;};
virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;};
void register_custom_csr_rd(unsigned addr){
csr_rd_cb[addr] = &this_class::read_custom_csr_reg;
}
void register_custom_csr_wr(unsigned addr){
csr_wr_cb[addr] = &this_class::write_custom_csr_reg;
}
reg_t mhartid_reg{0x0};
std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
void check_interrupt();
bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
std::vector<std::tuple<uint64_t, uint64_t>> memfn_range;
std::vector<std::function<mem_read_f>> memfn_read;
std::vector<std::function<mem_write_f>> memfn_write;
void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
uint64_t clic_base_addr{0};
unsigned clic_num_irq{0};
unsigned clic_num_trigger{0};
@ -386,7 +410,7 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
csr_rd_cb[mtvec] = &this_class::read_tvec;
csr_wr_cb[mepc] = &this_class::write_epc;
csr_rd_cb[mip] = &this_class::read_ip;
csr_wr_cb[mip] = &this_class::write_ip;
csr_wr_cb[mip] = &this_class::write_null;
csr_rd_cb[mie] = &this_class::read_ie;
csr_wr_cb[mie] = &this_class::write_ie;
csr_rd_cb[mhartid] = &this_class::read_hartid;
@ -394,6 +418,46 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
csr_wr_cb[mvendorid] = &this_class::write_null;
csr_wr_cb[marchid] = &this_class::write_null;
csr_wr_cb[mimpid] = &this_class::write_null;
if(FEAT & FEAT_CLIC) {
csr_rd_cb[mtvt] = &this_class::read_csr_reg;
csr_wr_cb[mtvt] = &this_class::write_csr_reg;
csr_rd_cb[mxnti] = &this_class::read_csr_reg;
csr_wr_cb[mxnti] = &this_class::write_csr_reg;
csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
csr_wr_cb[mintstatus] = &this_class::write_null;
csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg;
csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
csr_rd_cb[mintthresh] = &this_class::read_csr_reg;
csr_wr_cb[mintthresh] = &this_class::write_intthresh;
csr_rd_cb[mclicbase] = &this_class::read_csr_reg;
csr_wr_cb[mclicbase] = &this_class::write_null;
clic_base_addr=0xC0000000;
clic_num_irq=16;
clic_int_reg.resize(clic_num_irq);
clic_cfg_reg=0x20;
clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + clic_num_irq;
mcause_max_irq=clic_num_irq+16;
insert_mem_range(clic_base_addr, 0x5000UL,
[this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
[this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);});
}
if(FEAT & FEAT_TCM) {
tcm.resize(0x8000);
std::function<mem_read_f> read_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t * const data) {
auto offset=addr.val-0x10000000;
std::copy(tcm.data() + offset, tcm.data() + offset + length, data);
return iss::Ok;
};
std::function<mem_write_f> write_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {
auto offset=addr.val-0x10000000;
std::copy(data, data + length, tcm.data() + offset);
return iss::Ok;
};
insert_mem_range(0x10000000, 0x8000UL, read_clic_cb, write_clic_cb);
}
if(FEAT & FEAT_DEBUG){
csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg;
csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg;
@ -472,6 +536,20 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
throw std::runtime_error("memory load file not found");
}
template<typename BASE, features_e FEAT>
inline void riscv_hart_m_p<BASE, FEAT>::insert_mem_range(uint64_t base, uint64_t size, std::function<mem_read_f> rd_f,
std::function<mem_write_f> wr_fn) {
std::tuple<uint64_t, uint64_t> entry{base, size};
auto it = std::upper_bound( memfn_range.begin(), memfn_range.end(), entry,
[](std::tuple<uint64_t, uint64_t> const& a, std::tuple<uint64_t, uint64_t> const& b){
return std::get<0>(a)<std::get<0>(b);
});
auto idx = std::distance(memfn_range.begin(), it);
memfn_range.insert(it, entry);
memfn_read.insert(std::begin(memfn_read)+idx, rd_f);
memfn_write.insert(std::begin(memfn_write)+idx, wr_fn);
}
template <typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space,
const uint64_t addr, const unsigned length, uint8_t *const data) {
@ -500,9 +578,20 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
fault_data=addr;
return iss::Err;
}
auto res = type==iss::address_type::PHYSICAL?
read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
auto res = iss::Err;
if(access != access_type::FETCH && memfn_range.size()){
auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
});
if(it!=std::end(memfn_range)) {
auto idx = std::distance(std::begin(memfn_range), it);
res = memfn_read[idx](phys_addr, length, data);
} else
res = read_mem( phys_addr, length, data);
} else {
res = read_mem( phys_addr, length, data);
}
if (unlikely(res != iss::Ok)){
this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
fault_data=addr;
@ -577,14 +666,25 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
return iss::Err;
}
try {
if(!(access && iss::access_type::DEBUG) && length>1 && (addr&(length-1))){
if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
this->reg.trap_state = 1<<31 | 6<<16;
fault_data=addr;
return iss::Err;
}
auto res = type==iss::address_type::PHYSICAL?
write_mem(phys_addr_t{access, space, addr}, length, data):
write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
auto res = iss::Err;
if(access != access_type::FETCH && memfn_range.size()){
auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
});
if(it!=std::end(memfn_range)) {
auto idx = std::distance(std::begin(memfn_range), it);
res = memfn_write[idx]( phys_addr, length, data);
} else
res = write_mem( phys_addr, length, data);
} else {
res = write_mem( phys_addr, length, data);
}
if (unlikely(res != iss::Ok)) {
this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
fault_data=addr;
@ -777,7 +877,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable
csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))| (mcause_max_irq-1));
return iss::Ok;
}
@ -805,14 +905,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) {
auto mask = get_irq_mask();
mask &= 0xf; // only xSIP is writable
csr[mip] = (csr[mip] & ~mask) | (val & mask);
check_interrupt();
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_epc(unsigned addr, reg_t val) {
csr[addr] = val & get_pc_mask();
return iss::Ok;
@ -857,6 +949,12 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
return iss::Ok;
}
template<typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
csr[addr]= val &0xff;
return iss::Ok;
}
template <typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
if(mem_read_cb) return mem_read_cb(paddr, length, data);
@ -960,6 +1058,42 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
return iss::Ok;
}
template<typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length, uint8_t *const data) {
if(addr==clic_base_addr) { // cliccfg
*data=clic_cfg_reg;
for(auto i=1; i<length; ++i) *(data+i)=0;
} else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+8)){ // clicinfo
read_reg_uint32(addr, clic_info_reg, data, length);
} else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0x40+clic_num_trigger*4)){ // clicinttrig
auto offset = ((addr&0x7fff)-0x40)/4;
read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
} else if(addr>=(clic_base_addr+0x1000) && (addr+length)<=(clic_base_addr+clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
auto offset = ((addr&0x7fff)-0x1000)/4;
read_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
} else {
for(auto i = 0U; i<length; ++i) *(data+i)=0;
}
return iss::Ok;
}
template<typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
if(addr==clic_base_addr) { // cliccfg
clic_cfg_reg = *data;
clic_cfg_reg&= 0x7e;
// } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+4)){ // clicinfo
// write_uint32(addr, clic_info_reg, data, length);
} else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0xC0)){ // clicinttrig
auto offset = ((addr&0x7fff)-0x40)/4;
write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
} else if(addr>=(clic_base_addr+0x1000) && (addr+length)<=(clic_base_addr+clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
auto offset = ((addr&0x7fff)-0x1000)/4;
write_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
}
return iss::Ok;
}
template <typename BASE, features_e FEAT> inline void riscv_hart_m_p<BASE, FEAT>::reset(uint64_t address) {
BASE::reset(address);
state.mstatus = hart_state_type::mstatus_reset_val;
@ -993,6 +1127,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
auto trap_id = bit_sub<0, 16>(flags);
auto cause = bit_sub<16, 15>(flags);
// calculate effective privilege level
unsigned new_priv = PRIV_M;
if (trap_id == 0) { // exception
if (cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
// store ret addr in xepc register
@ -1012,10 +1147,13 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
csr[mtval] = (instr & 0x3)==3?instr:instr&0xffff;
break;
case 3:
//TODO: implement debug mode behavior
// csr[dpc] = addr;
// csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
csr[mtval] = 0;
if((FEAT & FEAT_DEBUG) && (csr[dcsr] & 0x8000)) {
this->reg.DPC = addr;
csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
new_priv = this->reg.PRIV | PRIV_D;
} else {
csr[mtval] = addr;
}
break;
case 4:
case 6:
@ -1029,7 +1167,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt
this->reg.pending_trap = 0;
}
csr[mcause] = (trap_id << 31) + cause;
csr[mcause] = (trap_id << (traits<BASE>::XLEN-1)) + cause;
// update mstatus
// xPP field of mstatus is written with the active privilege mode at the time
// of the trap; the x PIE field of mstatus
@ -1048,7 +1186,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
this->reg.NEXT_PC = ivec & ~0x3UL;
if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
// reset trap state
this->reg.PRIV = PRIV_M;
this->reg.PRIV = new_priv;
this->reg.trap_state = 0;
std::array<char, 32> buffer;
#if defined(_MSC_VER)

62
incl/iss/arch/riscv_hart_msu_vp.h
View File

@ -293,21 +293,21 @@ public:
std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
virtual phys_addr_t virt2phys(const iss::addr_t &addr) override;
phys_addr_t virt2phys(const iss::addr_t &addr) override;
iss::status read(const address_type type, const access_type access, const uint32_t space,
const uint64_t addr, const unsigned length, uint8_t *const data) override;
iss::status write(const address_type type, const access_type access, const uint32_t space,
const uint64_t addr, const unsigned length, const uint8_t *const data) override;
virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data, fault_data); }
virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
virtual uint64_t leave_trap(uint64_t flags) override;
uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data, fault_data); }
uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
uint64_t leave_trap(uint64_t flags) override;
void wait_until(uint64_t flags) override;
void disass_output(uint64_t pc, const std::string instr) override {
CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]",
pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.ccount);
pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.ccount + cycle_offset);
};
iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
@ -340,6 +340,10 @@ protected:
virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
uint64_t get_instr_count() { return arch.reg.icount; }
uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
riscv_hart_msu_vp<BASE> &arch;
@ -396,7 +400,6 @@ private:
iss::status read_ie(unsigned addr, reg_t &val);
iss::status write_ie(unsigned addr, reg_t val);
iss::status read_ip(unsigned addr, reg_t &val);
iss::status write_ip(unsigned addr, reg_t val);
iss::status read_hartid(unsigned addr, reg_t &val);
iss::status write_epc(unsigned addr, reg_t val);
iss::status read_satp(unsigned addr, reg_t &val);
@ -404,6 +407,16 @@ private:
iss::status read_fcsr(unsigned addr, reg_t &val);
iss::status write_fcsr(unsigned addr, reg_t val);
virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;};
virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;};
void register_custom_csr_rd(unsigned addr){
csr_rd_cb[addr] = &this_class::read_custom_csr_reg;
}
void register_custom_csr_wr(unsigned addr){
csr_wr_cb[addr] = &this_class::write_custom_csr_reg;
}
reg_t mhartid_reg{0x0};
std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
@ -485,11 +498,11 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
csr_wr_cb[sepc] = &this_class::write_epc;
csr_wr_cb[uepc] = &this_class::write_epc;
csr_rd_cb[mip] = &this_class::read_ip;
csr_wr_cb[mip] = &this_class::write_ip;
csr_wr_cb[mip] = &this_class::write_null;
csr_rd_cb[sip] = &this_class::read_ip;
csr_wr_cb[sip] = &this_class::write_ip;
csr_wr_cb[sip] = &this_class::write_null;
csr_rd_cb[uip] = &this_class::read_ip;
csr_wr_cb[uip] = &this_class::write_ip;
csr_wr_cb[uip] = &this_class::write_null;
csr_rd_cb[mie] = &this_class::read_ie;
csr_wr_cb[mie] = &this_class::write_ie;
csr_rd_cb[sie] = &this_class::read_ie;
@ -945,15 +958,6 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ip(unsigned a
return iss::Ok;
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ip(unsigned addr, reg_t val) {
auto req_priv_lvl = (addr >> 8) & 0x3;
auto mask = get_irq_mask(req_priv_lvl);
mask &= ~(1 << 7); // MTIP is read only
csr[mip] = (csr[mip] & ~mask) | (val & mask);
check_interrupt();
return iss::Ok;
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_epc(unsigned addr, reg_t val) {
csr[addr] = val & get_pc_mask();
return iss::Ok;
@ -1276,7 +1280,27 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
* access, or page-fault exception occurs, mtval is written with the
* faulting effective address.
*/
csr[utval | (new_priv << 8)] = cause==2?((instr & 0x3)==3?instr:instr&0xffff):fault_data;
switch(cause){
case 0:
csr[utval | (new_priv << 8)] = static_cast<reg_t>(addr);
break;
case 2:
csr[utval | (new_priv << 8)] = (instr & 0x3)==3?instr:instr&0xffff;
break;
case 3:
//TODO: implement debug mode behavior
// csr[dpc] = addr;
// csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
csr[utval | (new_priv << 8)] = addr;
break;
case 4:
case 6:
case 7:
csr[utval | (new_priv << 8)] = fault_data;
break;
default:
csr[utval | (new_priv << 8)] = 0;
}
fault_data = 0;
} else {
if (cur_priv != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0)

229
incl/iss/arch/riscv_hart_mu_p.h
View File

@ -97,8 +97,10 @@ public:
using reg_t = typename core::reg_t;
using addr_t = typename core::addr_t;
using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
using mem_read_f = iss::status(phys_addr_t addr, unsigned, uint8_t *const);
using mem_write_f = iss::status(phys_addr_t addr, unsigned, uint8_t const *const);
// primary template
template <class T, class Enable = void> struct hart_state {};
@ -195,7 +197,7 @@ public:
return traits<BASE>::MISA_VAL&0b0100?~1:~3;
}
riscv_hart_mu_p();
riscv_hart_mu_p(feature_config cfg = feature_config{});
virtual ~riscv_hart_mu_p() = default;
void reset(uint64_t address) override;
@ -207,16 +209,16 @@ public:
iss::status write(const address_type type, const access_type access, const uint32_t space,
const uint64_t addr, const unsigned length, const uint8_t *const data) override;
virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_mu_p::enter_trap(flags, fault_data, fault_data); }
virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
virtual uint64_t leave_trap(uint64_t flags) override;
uint64_t enter_trap(uint64_t flags) override { return riscv_hart_mu_p::enter_trap(flags, fault_data, fault_data); }
uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
uint64_t leave_trap(uint64_t flags) override;
const reg_t& get_mhartid() const { return mhartid_reg; }
void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
void disass_output(uint64_t pc, const std::string instr) override {
CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]",
pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.icount);
pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.icount + cycle_offset);
};
iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
@ -233,6 +235,9 @@ public:
csr[addr & csr.page_addr_mask] = val;
}
void set_irq_num(unsigned i) {
mcause_max_irq=1<<util::ilog2(i);
}
protected:
struct riscv_instrumentation_if : public iss::instrumentation_if {
@ -249,6 +254,10 @@ protected:
virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
uint64_t get_instr_count() { return arch.reg.icount; }
uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
riscv_hart_mu_p<BASE, FEAT> &arch;
@ -302,6 +311,8 @@ protected:
};
std::vector<clic_int_reg_t> clic_int_reg;
std::vector<uint8_t> tcm;
iss::status read_csr_reg(unsigned addr, reg_t &val);
iss::status write_csr_reg(unsigned addr, reg_t val);
iss::status read_null(unsigned addr, reg_t &val);
@ -318,7 +329,6 @@ protected:
iss::status read_ie(unsigned addr, reg_t &val);
iss::status write_ie(unsigned addr, reg_t val);
iss::status read_ip(unsigned addr, reg_t &val);
iss::status write_ip(unsigned addr, reg_t val);
iss::status write_ideleg(unsigned addr, reg_t val);
iss::status write_edeleg(unsigned addr, reg_t val);
iss::status read_hartid(unsigned addr, reg_t &val);
@ -330,6 +340,17 @@ protected:
iss::status write_dcsr_reg(unsigned addr, reg_t val);
iss::status read_dpc_reg(unsigned addr, reg_t &val);
iss::status write_dpc_reg(unsigned addr, reg_t val);
iss::status write_pmpcfg_reg(unsigned addr, reg_t val);
virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;};
virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;};
void register_custom_csr_rd(unsigned addr){
csr_rd_cb[addr] = &this_class::read_custom_csr_reg;
}
void register_custom_csr_wr(unsigned addr){
csr_wr_cb[addr] = &this_class::write_custom_csr_reg;
}
reg_t mhartid_reg{0x0};
std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
@ -337,23 +358,26 @@ protected:
void check_interrupt();
bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
uint64_t clic_base_addr{0};
unsigned clic_num_irq{0};
unsigned clic_num_trigger{0};
std::vector<std::tuple<uint64_t, uint64_t>> memfn_range;
std::vector<std::function<mem_read_f>> memfn_read;
std::vector<std::function<mem_write_f>> memfn_write;
void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
feature_config cfg;
unsigned mcause_max_irq{16};
inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
};
template <typename BASE, features_e FEAT>
riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
: state()
, instr_if(*this) {
, instr_if(*this)
, cfg(cfg) {
// reset values
csr[misa] = traits<BASE>::MISA_VAL;
csr[mvendorid] = 0x669;
csr[marchid] = traits<BASE>::MARCHID_VAL;
csr[mimpid] = 1;
csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file
csr[mclicbase] = cfg.clic_base; // TODO: should be taken from YAML file
uart_buf.str("");
for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
@ -407,7 +431,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
csr_rd_cb[mtvec] = &this_class::read_tvec;
csr_wr_cb[mepc] = &this_class::write_epc;
csr_rd_cb[mip] = &this_class::read_ip;
csr_wr_cb[mip] = &this_class::write_ip;
csr_wr_cb[mip] = &this_class::write_null;
csr_rd_cb[mie] = &this_class::read_ie;
csr_wr_cb[mie] = &this_class::write_ie;
csr_rd_cb[mhartid] = &this_class::read_hartid;
@ -425,7 +449,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
}
for(size_t i=pmpcfg0; i<=pmpcfg3; ++i){
csr_rd_cb[i] = &this_class::read_csr_reg;
csr_wr_cb[i] = &this_class::write_csr_reg;
csr_wr_cb[i] = &this_class::write_pmpcfg_reg;
}
}
if(FEAT & FEAT_EXT_N){
@ -436,7 +460,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
csr_rd_cb[uie] = &this_class::read_ie;
csr_wr_cb[uie] = &this_class::write_ie;
csr_rd_cb[uip] = &this_class::read_ip;
csr_wr_cb[uip] = &this_class::write_ip;
csr_wr_cb[uip] = &this_class::write_null;
csr_wr_cb[uepc] = &this_class::write_epc;
csr_rd_cb[ustatus] = &this_class::read_status;
csr_wr_cb[ustatus] = &this_class::write_status;
@ -459,12 +483,27 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
csr_rd_cb[mclicbase] = &this_class::read_csr_reg;
csr_wr_cb[mclicbase] = &this_class::write_null;
clic_base_addr=0xC0000000;
clic_num_irq=16;
clic_int_reg.resize(clic_num_irq);
clic_int_reg.resize(cfg.clic_num_irq);
clic_cfg_reg=0x20;
clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + clic_num_irq;
mcause_max_irq=clic_num_irq+16;
clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq;
mcause_max_irq=cfg.clic_num_irq+16;
insert_mem_range(cfg.clic_base, 0x5000UL,
[this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
[this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);});
}
if(FEAT & FEAT_TCM) {
tcm.resize(cfg.tcm_size);
std::function<mem_read_f> read_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t * const data) {
auto offset=addr.val-this->cfg.tcm_base;
std::copy(tcm.data() + offset, tcm.data() + offset + length, data);
return iss::Ok;
};
std::function<mem_write_f> write_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {
auto offset=addr.val-this->cfg.tcm_base;
std::copy(data, data + length, tcm.data() + offset);
return iss::Ok;
};
insert_mem_range(cfg.tcm_base, cfg.tcm_size, read_clic_cb, write_clic_cb);
}
if(FEAT & FEAT_DEBUG){
csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg;
@ -544,6 +583,26 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
throw std::runtime_error("memory load file not found");
}
template<typename BASE, features_e FEAT>
inline void riscv_hart_mu_p<BASE, FEAT>::insert_mem_range(uint64_t base, uint64_t size, std::function<mem_read_f> rd_f,
std::function<mem_write_f> wr_fn) {
std::tuple<uint64_t, uint64_t> entry{base, size};
auto it = std::upper_bound( memfn_range.begin(), memfn_range.end(), entry,
[](std::tuple<uint64_t, uint64_t> const& a, std::tuple<uint64_t, uint64_t> const& b){
return std::get<0>(a)<std::get<0>(b);
});
auto idx = std::distance(memfn_range.begin(), it);
memfn_range.insert(it, entry);
memfn_read.insert(std::begin(memfn_read)+idx, rd_f);
memfn_write.insert(std::begin(memfn_write)+idx, wr_fn);
}
template<typename BASE, features_e FEAT>
inline iss::status riscv_hart_mu_p<BASE, FEAT>::write_pmpcfg_reg(unsigned addr, reg_t val) {
csr[addr] = val & 0x9f9f9f9f;
return iss::Ok;
}
template <typename BASE, features_e FEAT> bool riscv_hart_mu_p<BASE, FEAT>::pmp_check(const access_type type, const uint64_t addr, const unsigned len) {
constexpr auto PMP_SHIFT=2U;
constexpr auto PMP_R = 0x1U;
@ -574,7 +633,7 @@ template <typename BASE, features_e FEAT> bool riscv_hart_mu_p<BASE, FEAT>::pmp_
for (reg_t offset = 0; offset < len; offset += 1 << PMP_SHIFT) {
reg_t cur_addr = addr + offset;
auto napot_match = ((cur_addr ^ tor) & mask) == 0;
auto tor_match = base <= cur_addr && cur_addr < tor;
auto tor_match = base <= (cur_addr+len-1) && cur_addr < tor;
auto match = is_tor ? tor_match : napot_match;
any_match |= match;
all_match &= match;
@ -664,8 +723,15 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
}
auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
auto res = iss::Err;
if((FEAT & FEAT_CLIC) && access != access_type::FETCH && phys_addr.val>=clic_base_addr && (phys_addr.val+length)<=(clic_base_addr+0x5000)){ //TODO: should be a constant
res = read_clic(phys_addr.val, length, data);
if(access != access_type::FETCH && memfn_range.size()){
auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
});
if(it!=std::end(memfn_range)) {
auto idx = std::distance(std::begin(memfn_range), it);
res = memfn_read[idx](phys_addr, length, data);
} else
res = read_mem( phys_addr, length, data);
} else {
res = read_mem( phys_addr, length, data);
}
@ -757,8 +823,19 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
return iss::Err;
}
auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
auto res = ((FEAT & FEAT_CLIC) && phys_addr.val>=clic_base_addr && (phys_addr.val+length)<=(clic_base_addr+0x5000))? //TODO: should be a constant
write_clic(phys_addr.val, length, data) : write_mem( phys_addr, length, data);
auto res = iss::Err;
if(access != access_type::FETCH && memfn_range.size()){
auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
});
if(it!=std::end(memfn_range)) {
auto idx = std::distance(std::begin(memfn_range), it);
res = memfn_write[idx]( phys_addr, length, data);
} else
res = write_mem( phys_addr, length, data);
} else {
res = write_mem( phys_addr, length, data);
}
if (unlikely(res != iss::Ok)) {
this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
fault_data=addr;
@ -952,7 +1029,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1))|(mcause_max_irq-1)); //TODO: make exception code size configurable
csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1))|(mcause_max_irq-1));
return iss::Ok;
}
@ -984,14 +1061,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) {
auto mask = get_irq_mask((addr >> 8) & 0x3);
mask &= 0xf; // only xSIP is writable
csr[mip] = (csr[mip] & ~mask) | (val & mask);
check_interrupt();
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ideleg(unsigned addr, reg_t val) {
auto mask = 0b000100010001; // only U mode supported
csr[mideleg] = (csr[mideleg] & ~mask) | (val & mask);
@ -1087,8 +1156,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned l
case 0x10023000: // UART1 base, TXFIFO reg
uart_buf << (char)data[0];
if (((char)data[0]) == '\n' || data[0] == 0) {
// LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
// '"<<uart_buf.str()<<"'";
LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send '"<<uart_buf.str()<<"'";
std::cout << uart_buf.str();
uart_buf.str("");
}
@ -1157,61 +1225,19 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned l
return iss::Ok;
}
void read_uint32(uint64_t offs, uint32_t& reg, uint8_t *const data, unsigned length) {
auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
switch (offs & 0x3) {
case 0:
for (auto i = 0U; i < length; ++i)
*(data + i) = *(reg_ptr + i);
break;
case 1:
for (auto i = 0U; i < length; ++i)
*(data + i) = *(reg_ptr + 1 + i);
break;
case 2:
for (auto i = 0U; i < length; ++i)
*(data + i) = *(reg_ptr + 2 + i);
break;
case 3:
*data = *(reg_ptr + 3);
break;
}
}
void write_uint32(uint64_t offs, uint32_t& reg, const uint8_t *const data, unsigned length) {
auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
switch (offs & 0x3) {
case 0:
for (auto i = 0U; i < length; ++i)
*(reg_ptr + i) = *(data + i);
break;
case 1:
for (auto i = 0U; i < length; ++i)
*(reg_ptr + 1 + i) = *(data + i);
break;
case 2:
for (auto i = 0U; i < length; ++i)
*(reg_ptr + 2 + i) = *(data + i);
break;
case 3:
*(reg_ptr + 3) = *data ;
break;
}
}
template<typename BASE, features_e FEAT>
iss::status riscv_hart_mu_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length, uint8_t *const data) {
if(addr==clic_base_addr) { // cliccfg
if(addr==cfg.clic_base) { // cliccfg
*data=clic_cfg_reg;
for(auto i=1; i<length; ++i) *(data+i)=0;
} else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+8)){ // clicinfo
read_uint32(addr, clic_info_reg, data, length);
} else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0x40+clic_num_trigger*4)){ // clicinttrig
} else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+8)){ // clicinfo
read_reg_uint32(addr, clic_info_reg, data, length);
} else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
auto offset = ((addr&0x7fff)-0x40)/4;
read_uint32(addr, clic_inttrig_reg[offset], data, length);
} else if(addr>=(clic_base_addr+0x1000) && (addr+length)<=(clic_base_addr+clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
} else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
auto offset = ((addr&0x7fff)-0x1000)/4;
read_uint32(addr, clic_int_reg[offset].raw, data, length);
read_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
} else {
for(auto i = 0U; i<length; ++i) *(data+i)=0;
}
@ -1220,17 +1246,17 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned lengt
template<typename BASE, features_e FEAT>
iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
if(addr==clic_base_addr) { // cliccfg
if(addr==cfg.clic_base) { // cliccfg
clic_cfg_reg = *data;
clic_cfg_reg&= 0x7f;
// } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+4)){ // clicinfo
clic_cfg_reg&= 0x7e;
// } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+4)){ // clicinfo
// write_uint32(addr, clic_info_reg, data, length);
} else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0xC0)){ // clicinttrig
} else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
auto offset = ((addr&0x7fff)-0x40)/4;
write_uint32(addr, clic_inttrig_reg[offset], data, length);
} else if(addr>=(clic_base_addr+0x1000) && (addr+length)<=(clic_base_addr+clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
} else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
auto offset = ((addr&0x7fff)-0x1000)/4;
write_uint32(addr, clic_int_reg[offset].raw, data, length);
write_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
}
return iss::Ok;
}
@ -1270,7 +1296,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
auto cause = bit_sub<16, 15>(flags);
if (trap_id == 0 && cause == 11) cause = 0x8 + this->reg.PRIV; // adjust environment call cause
// calculate effective privilege level
auto new_priv = PRIV_M;
unsigned new_priv = PRIV_M;
if (trap_id == 0) { // exception
if (this->reg.PRIV != PRIV_M && ((csr[medeleg] >> cause) & 0x1) != 0)
new_priv = PRIV_U;
@ -1291,10 +1317,13 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
csr[utval | (new_priv << 8)] = (instr & 0x3)==3?instr:instr&0xffff;
break;
case 3:
//TODO: implement debug mode behavior
// csr[dpc] = addr;
// csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
csr[utval | (new_priv << 8)] = 0;
if((FEAT & FEAT_DEBUG) && (csr[dcsr] & 0x8000)) {
this->reg.DPC = addr;
csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
new_priv = this->reg.PRIV | PRIV_D;
} else {
csr[utval | (new_priv << 8)] = addr;
}
break;
case 4:
case 6:
@ -1312,7 +1341,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
this->reg.pending_trap = 0;
}
size_t adr = ucause | (new_priv << 8);
csr[adr] = (trap_id << 31) + cause;
csr[adr] = (trap_id << (traits<BASE>::XLEN-1)) + cause;
// update mstatus
// xPP field of mstatus is written with the active privilege mode at the time
// of the trap; the x PIE field of mstatus

5
incl/iss/arch/tgc_c.h
View File

@ -53,7 +53,7 @@ template <> struct traits<tgc_c> {
static constexpr std::array<const char*, 36> reg_aliases{
{"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, RFS=32, INSTR_ALIGNMENT=2, XLEN=32, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
constexpr static unsigned FP_REGS_SIZE = 0;
@ -217,7 +217,7 @@ struct tgc_c: public arch_if {
inline uint32_t get_last_branch() { return reg.last_branch; }
protected:
#pragma pack(push, 1)
struct TGC_C_regs {
uint32_t X0 = 0;
@ -258,7 +258,6 @@ protected:
uint32_t DPC = 0;
uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0;
uint64_t cycle = 0;
uint64_t instret = 0;
uint32_t last_branch;
} reg;

43
incl/iss/arch/tgc_mapper.h Normal file
View File

@ -0,0 +1,43 @@
#ifndef _ISS_ARCH_TGC_MAPPER_H
#define _ISS_ARCH_TGC_MAPPER_H
#include "riscv_hart_m_p.h"
#include "tgc_c.h"
using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
#ifdef CORE_TGC_B
#include "riscv_hart_m_p.h"
#include "tgc_b.h"
using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
#endif
#ifdef CORE_TGC_C_XRB_NN
#include "riscv_hart_m_p.h"
#include "tgc_c_xrb_nn.h"
using tgc_c_xrb_nn_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>;
#endif
#ifdef CORE_TGC_D
#include "riscv_hart_mu_p.h"
#include "tgc_d.h"
using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#endif
#ifdef CORE_TGC_D_XRB_MAC
#include "riscv_hart_mu_p.h"
#include "tgc_d_xrb_mac.h"
using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#endif
#ifdef CORE_TGC_D_XRB_NN
#include "riscv_hart_mu_p.h"
#include "tgc_d_xrb_nn.h"
using tgc_d_xrb_nn_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#endif
#ifdef CORE_TGC_E
#include "riscv_hart_mu_p.h"
#include "tgc_e.h"
using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#endif
#ifdef CORE_TGC_X
#include "riscv_hart_mu_p.h"
#include "tgc_x.h"
using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
#endif
#endif

24
incl/iss/debugger/riscv_target_adapter.h
View File

@ -214,12 +214,26 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
auto start_reg=arch::traits<ARCH>::X0;
auto *reg_base = core->get_regs_base_ptr();
auto iter = data.data();
bool e_ext = arch::traits<ARCH>::PC<32;
for (size_t reg_no = 0; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
std::copy(iter, iter + reg_width, reg_base);
iter += 4;
reg_base += offset;
if(e_ext && reg_no>15){
if(reg_no==32){
auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
std::copy(iter, iter + reg_width, reg_base);
} else {
const uint64_t zero_val=0;
auto reg_width = arch::traits<ARCH>::reg_bit_widths[15] / 8;
auto iter = (uint8_t*)&zero_val;
std::copy(iter, iter + reg_width, reg_base);
}
} else {
auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
std::copy(iter, iter + reg_width, reg_base);
iter += 4;
reg_base += offset;
}
}
return Ok;
}

12
incl/iss/plugin/cycle_estimate.h
View File

@ -37,9 +37,9 @@
#include "iss/instrumentation_if.h"
#include "iss/vm_plugin.h"
#include <json/json.h>
#include <string>
#include <unordered_map>
#include <vector>
namespace iss {
@ -49,11 +49,13 @@ class cycle_estimate: public iss::vm_plugin {
BEGIN_BF_DECL(instr_desc, uint32_t)
BF_FIELD(taken, 24, 8)
BF_FIELD(not_taken, 16, 8)
BF_FIELD(size, 0, 16)
instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken): instr_desc() {
BF_FIELD(is_branch, 8, 8)
BF_FIELD(size, 0, 8)
instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
this->size=size;
this->taken=taken;
this->not_taken=not_taken;
this->is_branch=branch;
}
END_BF_DECL();
@ -64,7 +66,7 @@ public:
cycle_estimate(const cycle_estimate &&) = delete;
cycle_estimate(std::string config_file_name);
cycle_estimate(std::string const& config_file_name);
virtual ~cycle_estimate();
@ -88,7 +90,7 @@ private:
}
};
std::unordered_map<std::pair<uint64_t, uint64_t>, uint64_t, pair_hash> blocks;
Json::Value root;
std::string config_file_name;
};
}
}

99
incl/iss/plugin/pctrace.h Normal file
View File

@ -0,0 +1,99 @@
/*******************************************************************************
* Copyright (C) 2017, 2018, MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Contributors:
* eyck@minres.com - initial API and implementation
******************************************************************************/
#ifndef _ISS_PLUGIN_COV_H_
#define _ISS_PLUGIN_COV_H_
#include <iss/vm_plugin.h>
#include "iss/instrumentation_if.h"
#include <json/json.h>
#include <string>
#include <fstream>
namespace iss {
namespace plugin {
class cov : public iss::vm_plugin {
struct instr_delay {
std::string instr_name;
size_t size;
size_t not_taken_delay;
size_t taken_delay;
};
BEGIN_BF_DECL(instr_desc, uint32_t)
BF_FIELD(taken, 24, 8)
BF_FIELD(not_taken, 16, 8)
BF_FIELD(is_branch, 8, 8)
BF_FIELD(size, 0, 8)
instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
this->size=size;
this->taken=taken;
this->not_taken=not_taken;
this->is_branch=branch;
}
END_BF_DECL();
public:
cov(const cov &) = delete;
cov(const cov &&) = delete;
cov(std::string const &);
virtual ~cov();
cov &operator=(const cov &) = delete;
cov &operator=(const cov &&) = delete;
bool registration(const char *const version, vm_if &arch) override;
sync_type get_sync() override { return POST_SYNC; };
void callback(instr_info_t, exec_info const&) override;
private:
iss::instrumentation_if *instr_if {nullptr};
std::ofstream output;
std::string filename;
std::vector<instr_desc> delays;
bool jumped, first;
};
}
}
#endif /* _ISS_PLUGIN_COV_H_ */

47
src/main.cpp
View File

@ -35,31 +35,14 @@
#include <boost/lexical_cast.hpp>
#include <boost/program_options.hpp>
#include <iss/arch/riscv_hart_m_p.h>
#include "iss/arch/riscv_hart_m_p.h"
#include "iss/arch/tgc_c.h"
using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
#ifdef CORE_TGC_B
#include "iss/arch/riscv_hart_m_p.h"
#include "iss/arch/tgc_b.h"
using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
#endif
#ifdef CORE_TGC_D
#include "iss/arch/riscv_hart_mu_p.h"
#include "iss/arch/tgc_d.h"
using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#endif
#ifdef CORE_TGC_D_XRB_MAC
#include "iss/arch/riscv_hart_mu_p.h"
#include "iss/arch/tgc_d_xrb_mac.h"
using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#endif
#include <iss/arch/tgc_mapper.h>
#ifdef WITH_LLVM
#include <iss/llvm/jit_helper.h>
#endif
#include <iss/log_categories.h>
#include <iss/plugin/cycle_estimate.h>
#include <iss/plugin/instruction_count.h>
#include <iss/plugin/pctrace.h>
#include <iss/plugin/loader.h>
#if defined(HAS_LUA)
#include <iss/plugin/lua.h>
@ -142,6 +125,12 @@ int main(int argc, char *argv[]) {
iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else
#endif
#ifdef CORE_TGC_C_XRB_NN
if (isa_opt == "tgc_c_xrb_nn") {
std::tie(cpu, vm) =
iss::create_cpu<tgc_c_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else
#endif
#ifdef CORE_TGC_D
if (isa_opt == "tgc_d") {
std::tie(cpu, vm) =
@ -153,9 +142,21 @@ int main(int argc, char *argv[]) {
std::tie(cpu, vm) =
iss::create_cpu<tgc_d_xrb_mac_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else
#endif
#ifdef CORE_TGC_D_XRB_NN
if (isa_opt == "tgc_d_xrb_nn") {
std::tie(cpu, vm) =
iss::create_cpu<tgc_d_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else
#endif
#ifdef CORE_TGC_E
if (isa_opt == "tgc_e") {
std::tie(cpu, vm) =
iss::create_cpu<tgc_e_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else
#endif
{
LOG(ERR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
LOG(ERR) << "Illegal argument value for '--isa': " << isa_opt << std::endl;
return 127;
}
if (clim.count("plugin")) {
@ -175,7 +176,11 @@ int main(int argc, char *argv[]) {
auto *ce_plugin = new iss::plugin::cycle_estimate(filename);
vm->register_plugin(*ce_plugin);
plugin_list.push_back(ce_plugin);
} else {
} else if (plugin_name == "pctrace") {
auto *plugin = new iss::plugin::cov(filename);
vm->register_plugin(*plugin);
plugin_list.push_back(plugin);
} else {
std::array<char const*, 1> a{{filename.c_str()}};
iss::plugin::loader l(plugin_name, {{"initPlugin"}});
auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());

98
src/plugin/cycle_estimate.cpp
View File

@ -36,58 +36,82 @@
#include <iss/arch_if.h>
#include <util/logging.h>
#include <rapidjson/document.h>
#include <rapidjson/istreamwrapper.h>
#include "rapidjson/writer.h"
#include "rapidjson/stringbuffer.h"
#include <rapidjson/ostreamwrapper.h>
#include <rapidjson/error/en.h>
#include <fstream>
iss::plugin::cycle_estimate::cycle_estimate(std::string config_file_name)
using namespace rapidjson;
using namespace std;
iss::plugin::cycle_estimate::cycle_estimate(string const& config_file_name)
: arch_instr(nullptr)
, config_file_name(config_file_name)
{
if (config_file_name.length() > 0) {
std::ifstream is(config_file_name);
if (is.is_open()) {
try {
is >> root;
} catch (Json::RuntimeError &e) {
LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
}
} else {
LOG(ERR) << "Could not open input file " << config_file_name;
}
}
}
iss::plugin::cycle_estimate::~cycle_estimate() {
}
bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
arch_instr = vm.get_arch()->get_instrumentation_if();
if(!arch_instr) return false;
const std::string core_name = arch_instr->core_type_name();
Json::Value &val = root[core_name];
if(!val.isNull() && val.isArray()){
delays.reserve(val.size());
for(auto it:val){
auto name = it["name"];
auto size = it["size"];
auto delay = it["delay"];
if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error");
if(delay.isUInt()){
delays.push_back(instr_desc{size.asUInt(), delay.asUInt(), 0});
} else {
delays.push_back(instr_desc{size.asUInt(), delay[0].asUInt(), delay[1].asUInt()});
}
}
} else {
LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
arch_instr = vm.get_arch()->get_instrumentation_if();
if(!arch_instr) return false;
const string core_name = arch_instr->core_type_name();
if (config_file_name.length() > 0) {
ifstream is(config_file_name);
if (is.is_open()) {
try {
IStreamWrapper isw(is);
Document d;
ParseResult ok = d.ParseStream(isw);
if(ok) {
Value& val = d[core_name.c_str()];
if(val.IsArray()){
delays.reserve(val.Size());
for (auto it = val.Begin(); it != val.End(); ++it) {
auto& name = (*it)["name"];
auto& size = (*it)["size"];
auto& delay = (*it)["delay"];
auto& branch = (*it)["branch"];
if(delay.IsArray()) {
auto dt = delay[0].Get<unsigned>();
auto dnt = delay[1].Get<unsigned>();
delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
} else if(delay.Is<unsigned>()) {
auto d = delay.Get<unsigned>();
delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
} else
throw runtime_error("JSON parse error");
}
} else {
LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
return false;
}
} else {
LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
return false;
}
} catch (runtime_error &e) {
LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
return false;
}
} else {
LOG(ERR) << "Could not open input file " << config_file_name;
return false;
}
}
return true;
return true;
}
void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const&) {
void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const& exc_info) {
assert(arch_instr && "No instrumentation interface available but callback executed");
auto entry = delays[instr_info.instr_id];
bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);
if (taken && entry.taken > 1)
auto entry = delays[instr_info.instr_id];
bool taken = exc_info.branch_taken;
if (exc_info.branch_taken && (entry.taken > 1))
arch_instr->set_curr_instr_cycles(entry.taken);
else if (entry.not_taken > 1)
arch_instr->set_curr_instr_cycles(entry.not_taken);

133
src/plugin/pctrace.cpp Normal file
View File

@ -0,0 +1,133 @@
#include <iss/arch_if.h>
#include <iss/plugin/pctrace.h>
#include <util/logging.h>
#include <rapidjson/document.h>
#include <rapidjson/istreamwrapper.h>
#include "rapidjson/writer.h"
#include "rapidjson/stringbuffer.h"
#include <rapidjson/ostreamwrapper.h>
#include <rapidjson/error/en.h>
#include <fstream>
#include <iostream>
using namespace rapidjson;
using namespace std;
iss::plugin::cov::cov(std::string const &filename)
: instr_if(nullptr)
, filename(filename)
{
output.open("output.trc");
jumped = false;
first = true;
}
iss::plugin::cov::~cov() {
output.close();
}
bool iss::plugin::cov::registration(const char *const version, vm_if& vm) {
instr_if = vm.get_arch()->get_instrumentation_if();
if(!instr_if) return false;
const string core_name = instr_if->core_type_name();
if (filename.length() > 0) {
ifstream is(filename);
if (is.is_open()) {
try {
IStreamWrapper isw(is);
Document d;
ParseResult ok = d.ParseStream(isw);
if(ok) {
Value& val = d[core_name.c_str()];
if(val.IsArray()){
delays.reserve(val.Size());
for (auto it = val.Begin(); it != val.End(); ++it) {
auto& name = (*it)["name"];
auto& size = (*it)["size"];
auto& delay = (*it)["delay"];
auto& branch = (*it)["branch"];
if(delay.IsArray()) {
auto dt = delay[0].Get<unsigned>();
auto dnt = delay[1].Get<unsigned>();
delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
} else if(delay.Is<unsigned>()) {
auto d = delay.Get<unsigned>();
delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
} else
throw runtime_error("JSON parse error");
}
} else {
LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
return false;
}
} else {
LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
return false;
}
} catch (runtime_error &e) {
LOG(ERR) << "Could not parse input file " << filename << ", reason: " << e.what();
return false;
}
} else {
LOG(ERR) << "Could not open input file " << filename;
return false;
}
}
return true;
}
inline string formatPC(uint64_t pc) {
stringstream stream;
stream << "0x" << std::hex << pc;
return stream.str();
}
void iss::plugin::cov::callback(instr_info_t iinfo, const exec_info& einfo) {
// auto delay = 0;
// auto entry = delays[iinfo.instr_id];
// bool taken = einfo.branch_taken;
// if (einfo.branch_taken)
// delay = entry.taken;
// else
// delay = entry.not_taken;
//
// if (first){
// output << formatPC(instr_if->get_pc()) << "," << delay;
// first = false;
// }
// if(instr_if->get_next_pc()-instr_if->get_pc() != delays[iinfo.instr_id].size/8){
// //The goal is to keep the output in start-target pairs, so after a jump the target address needs to get written
// //to the output. If the target happens to also be a start, we keep the pairing by adding a 0-delay entry.
// if (jumped)
// output <<"\n" <<formatPC(instr_if->get_pc()) << "," << 0;
// output <<"\n" << formatPC(instr_if->get_pc()) << "," << delay;
// jumped = true;
// }
// else{
// if (jumped){
// output <<"\n" << formatPC(instr_if->get_pc()) << "," << delay;
// jumped = false;
// }
// else if(delay!=1){
// output <<"\n" << formatPC(instr_if->get_pc()) << "," << delay;
// output <<"\n" << formatPC(instr_if->get_pc()) << "," << 0;
// }
//
// }
//source code for the full output
auto delay = 0;
auto entry = delays[iinfo.instr_id];
bool taken = einfo.branch_taken;
if (einfo.branch_taken)
delay = entry.taken;
else
delay = entry.not_taken;
output<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay << "\n";
}

47
src/sysc/core_complex.cpp
View File

@ -31,32 +31,15 @@
*******************************************************************************/
// clang-format off
#include "iss/debugger/gdb_session.h"
#include "iss/debugger/encoderdecoder.h"
#include "iss/debugger/server.h"
#include "iss/debugger/target_adapter_if.h"
#include "iss/iss.h"
#include "iss/vm_types.h"
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/encoderdecoder.h>
#include <iss/debugger/server.h>
#include <iss/debugger/target_adapter_if.h>
#include <iss/iss.h>
#include <iss/vm_types.h>
#include <iss/plugin/loader.h>
#include "sysc/core_complex.h"
#ifdef CORE_TGC_B
#include "iss/arch/riscv_hart_m_p.h"
#include "iss/arch/tgc_b.h"
using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
#endif
#include "iss/arch/riscv_hart_m_p.h"
#include "iss/arch/tgc_c.h"
using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
#ifdef CORE_TGC_D
#include "iss/arch/riscv_hart_mu_p.h"
#include "iss/arch/tgc_d.h"
using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::FEAT_PMP>;
#endif
#ifdef CORE_TGC_D_XRB_MAC
#include "iss/arch/riscv_hart_mu_p.h"
#include "iss/arch/tgc_d_xrb_mac.h"
using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, iss::arch::FEAT_PMP>;
#endif
#include <sysc/core_complex.h>
#include <iss/arch/tgc_mapper.h>
#include <scc/report.h>
#include <util/ities.h>
#include <iostream>
@ -64,6 +47,8 @@ using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_
#include <array>
#include <iss/plugin/cycle_estimate.h>
#include <iss/plugin/instruction_count.h>
#include <iss/plugin/pctrace.h>
// clang-format on
#define STR(X) #X
@ -129,7 +114,8 @@ public:
if (!owner->disass_output(pc, instr)) {
std::stringstream s;
s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
<< std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
<< std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
<< this->reg.icount + this->cycle_offset << "]";
SCCDEBUG(owner->name())<<"disass: "
<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
<< std::setfill(' ') << std::left << instr << s.str();
@ -303,8 +289,11 @@ public:
#ifdef CORE_TGC_D
CREATE_CORE(tgc_d)
#endif
#ifdef CORE_TGC_D_XRB_MACD
#ifdef CORE_TGC_D_XRB_MAC
CREATE_CORE(tgc_d_xrb_mac)
#endif
#ifdef CORE_TGC_D_XRB_NN
CREATE_CORE(tgc_d_xrb_nn)
#endif
{
LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
@ -415,6 +404,10 @@ void core_complex::before_end_of_elaboration() {
auto *plugin = new iss::plugin::cycle_estimate(filename);
cpu->vm->register_plugin(*plugin);
plugin_list.push_back(plugin);
} else if (plugin_name == "pctrace") {
auto *plugin = new iss::plugin::cov(filename);
cpu->vm->register_plugin(*plugin);
plugin_list.push_back(plugin);
} else {
std::array<char const*, 1> a{{filename.c_str()}};
iss::plugin::loader l(plugin_name, {{"initPlugin"}});

6188
src/vm/interp/vm_tgc_c.cpp
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