74 lines
2.2 KiB
Plaintext
74 lines
2.2 KiB
Plaintext
import "CoreDSL-Instruction-Set-Description/RISCVBase.core_desc"
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import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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InstructionSet X_RB_MAC extends RISCVBase {
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architectural_state {
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register unsigned<64> ACC;
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}
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instructions {
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RESET_ACC { // v-- funct7 v-- funct3
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encoding: 7'd0 :: 10'b0 :: 3'd0 :: 5'b0 :: 7'b0001011;
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behavior: ACC = 0;
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}
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GET_ACC_LO {
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encoding: 7'd1 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
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behavior: if (rd != 0) X[rd] = ACC[31:0];
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}
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GET_ACC_HI {
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encoding: 7'd2 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
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behavior: if (rd != 0) X[rd] = ACC[63:32];
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}
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MACU_32 {
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encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
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behavior: {
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unsigned<64> mul = X[rs1] * X[rs2];
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unsigned<33> add = mul[31:0] + ACC[31:0];
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ACC = add[31:0];
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}
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}
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MACS_32 {
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encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
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behavior: {
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signed<64> mul = ((signed) X[rs1]) * ((signed) X[rs2]);
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signed<33> add = ((signed) mul[31:0]) + ((signed) ACC[31:0]);
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ACC = add[31:0]; // bit range always yields unsigned type
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}
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}
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MACU_64 {
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encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
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behavior: {
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unsigned<64> mul = X[rs1] * X[rs2];
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unsigned<65> add = mul + ACC;
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ACC = add[63:0];
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}
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}
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MACS_64 {
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encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
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behavior: {
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signed<64> mul = ((signed) X[rs1]) * ((signed) X[rs2]);
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signed<65> add = mul + ((signed) ACC);
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ACC = add[63:0];
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}
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}
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}
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}
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Core TGC_D_XRB_MAC provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_MAC {
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architectural_state {
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XLEN=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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unsigned MISA_VAL = 0b01000000000000000001000100000100;
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unsigned MARCHID_VAL = 0x80000004;
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}
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}
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