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DBT-RISE
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DBT-RISE-TGC
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DBT-RISE-TGC
/
gen_input
History
Eyck Jentzsch
d31b4ef5a8
fix MISA val
2021-11-11 12:58:57 +01:00
..
CoreDSL-Instruction-Set-Description
@
b005607fc3
fix proper debug mode handling (
#267
&
#268
)
2021-11-07 17:48:44 +01:00
templates
fix proper debug mode handling (
#267
&
#268
)
2021-11-07 17:48:44 +01:00
.gitignore
reorganized layout to only contain risc-v stuff
2019-06-11 16:49:37 +00:00
TGC_B.core_desc
update core definitions to include Zicsr and Zifencei (
#276
)
2021-10-30 12:56:31 +02:00
TGC_C.core_desc
update core definitions to include Zicsr and Zifencei (
#276
)
2021-10-30 12:56:31 +02:00
TGC_D_XRB_MAC.core_desc
update core definitions to include Zicsr and Zifencei (
#276
)
2021-10-30 12:56:31 +02:00
TGC_D_XRB_NN.core_desc
fix MISA val
2021-11-11 12:58:57 +01:00
TGC_D.core_desc
rework PMP check and fix MISA for TGC_D
2021-11-09 15:55:22 +01:00
