14 lines
513 B
Plaintext
14 lines
513 B
Plaintext
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
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architectural_state {
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XLEN=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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unsigned MISA_VAL = 0b01000000000000000001000100000100;
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unsigned MARCHID_VAL = 0x80000003;
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}
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}
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