DBT-RISE/DBT-RISE-TGC
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applies clang format

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This commit is contained in:
Eyck Jentzsch 2024-09-23 10:05:33 +02:00
parent f6be8ec006
commit 62768bf81e
4 changed files with 21 additions and 27 deletions
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2
src/iss/arch/riscv_hart_common.h
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@ -355,7 +355,7 @@ struct riscv_hart_common {
unsigned char other = 0;
for(auto i = 0U; i < sym_no; ++i) {
symbols.get_symbol(i, name, value, size, bind, type, section, other);
if(type==0 && name != "") {
if(name != "") {
this->symbol_table[name] = value;
#ifndef NDEBUG
CPPLOG(DEBUG) << "Found Symbol " << name;

14
src/iss/arch/riscv_hart_m_p.h
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@ -572,12 +572,11 @@ riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p(feature_config cfg)
template <typename BASE, features_e FEAT, typename LOGCAT>
std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT, LOGCAT>::load_file(std::string name, int type) {
if(read_elf_file(name,sizeof(reg_t)==4?ELFCLASS32:ELFCLASS64,
[this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
addr, size, data);
})) {
if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFCLASS32 : ELFCLASS64,
[this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, addr, size,
data);
})) {
return std::make_pair(entry_address, true);
}
return std::make_pair(entry_address, false);
@ -1327,8 +1326,7 @@ uint64_t riscv_hart_m_p<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint64_t
#endif
if((flags & 0xffffffff) != 0xffffffff)
NSCLOG(INFO, LOGCAT) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' ("
<< cause << ")"
<< " at address " << buffer.data() << " occurred";
<< cause << ")" << " at address " << buffer.data() << " occurred";
return this->reg.NEXT_PC;
}

16
src/iss/arch/riscv_hart_msu_vp.h
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@ -555,12 +555,11 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
}
template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load_file(std::string name, int type) {
if(read_elf_file(name,sizeof(reg_t)==4?ELFCLASS32:ELFCLASS64,
[this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
addr, size, data);
})) {
if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFCLASS32 : ELFCLASS64,
[this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, addr, size,
data);
})) {
return std::make_pair(entry_address, true);
}
return std::make_pair(entry_address, false);
@ -1338,9 +1337,8 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
sprintf(buffer.data(), "0x%016lx", addr);
if((flags & 0xffffffff) != 0xffffffff)
CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' ("
<< cause << ")"
<< " at address " << buffer.data() << " occurred, changing privilege level from " << lvl[cur_priv] << " to "
<< lvl[new_priv];
<< cause << ")" << " at address " << buffer.data() << " occurred, changing privilege level from "
<< lvl[cur_priv] << " to " << lvl[new_priv];
// reset trap state
this->reg.PRIV = new_priv;
this->reg.trap_state = 0;

16
src/iss/arch/riscv_hart_mu_p.h
View File

@ -649,12 +649,11 @@ riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p(feature_config cfg)
template <typename BASE, features_e FEAT, typename LOGCAT>
std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT, LOGCAT>::load_file(std::string name, int type) {
if(read_elf_file(name,sizeof(reg_t)==4?ELFCLASS32:ELFCLASS64,
[this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
addr, size, data);
})) {
if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFCLASS32 : ELFCLASS64,
[this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, addr, size,
data);
})) {
return std::make_pair(entry_address, true);
}
return std::make_pair(entry_address, false);
@ -1566,9 +1565,8 @@ uint64_t riscv_hart_mu_p<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint64_
#endif
if((flags & 0xffffffff) != 0xffffffff)
CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' ("
<< cause << ")"
<< " at address " << buffer.data() << " occurred, changing privilege level from " << lvl[this->reg.PRIV]
<< " to " << lvl[new_priv];
<< cause << ")" << " at address " << buffer.data() << " occurred, changing privilege level from "
<< lvl[this->reg.PRIV] << " to " << lvl[new_priv];
// reset trap state
this->reg.PRIV = new_priv;
this->reg.trap_state = 0;