DBT-RISE/DBT-RISE-TGC
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adds namespaces for ELFIO

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This commit is contained in:
Eyck-Alexander Jentzsch 2024-09-23 11:51:32 +02:00
parent 62768bf81e
commit 2f3abf2f76
4 changed files with 18 additions and 14 deletions
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13
src/iss/arch/riscv_hart_common.h
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@ -319,7 +319,8 @@ struct riscv_hart_common {
uint64_t tohost = tohost_dflt;
uint64_t fromhost = fromhost_dflt;
bool read_elf_file(std::string name, uint8_t expected_elf_class, std::function<iss::status(uint64_t, uint64_t, const uint8_t* const)> cb) {
bool read_elf_file(std::string name, uint8_t expected_elf_class,
std::function<iss::status(uint64_t, uint64_t, const uint8_t* const)> cb) {
// Create elfio reader
ELFIO::elfio reader;
// Load ELF data
@ -327,12 +328,12 @@ struct riscv_hart_common {
// check elf properties
if(reader.get_class() != expected_elf_class)
return false;
if(reader.get_type() != ET_EXEC)
return false;
if(reader.get_machine() != EM_RISCV)
if(reader.get_type() != ELFIO::ET_EXEC)
return false;
if(reader.get_machine() != ELFIO::EM_RISCV)
return false;
entry_address = reader.get_entry();
for(const auto pseg : reader.segments) {
for(const auto& pseg : reader.segments) {
const auto fsize = pseg->get_file_size(); // 0x42c/0x0
const auto seg_data = pseg->get_data();
const auto type = pseg->get_type();
@ -343,7 +344,7 @@ struct riscv_hart_common {
}
}
const auto sym_sec = reader.sections[".symtab"];
if(SHT_SYMTAB == sym_sec->get_type() || SHT_DYNSYM == sym_sec->get_type()) {
if(ELFIO::SHT_SYMTAB == sym_sec->get_type() || ELFIO::SHT_DYNSYM == sym_sec->get_type()) {
ELFIO::symbol_section_accessor symbols(reader, sym_sec);
auto sym_no = symbols.get_symbols_num();
std::string name;

5
src/iss/arch/riscv_hart_m_p.h
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@ -572,7 +572,7 @@ riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p(feature_config cfg)
template <typename BASE, features_e FEAT, typename LOGCAT>
std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT, LOGCAT>::load_file(std::string name, int type) {
if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFCLASS32 : ELFCLASS64,
if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFIO::ELFCLASS32 : ELFIO::ELFCLASS64,
[this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, addr, size,
data);
@ -1326,7 +1326,8 @@ uint64_t riscv_hart_m_p<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint64_t
#endif
if((flags & 0xffffffff) != 0xffffffff)
NSCLOG(INFO, LOGCAT) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' ("
<< cause << ")" << " at address " << buffer.data() << " occurred";
<< cause << ")"
<< " at address " << buffer.data() << " occurred";
return this->reg.NEXT_PC;
}

7
src/iss/arch/riscv_hart_msu_vp.h
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@ -555,7 +555,7 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
}
template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load_file(std::string name, int type) {
if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFCLASS32 : ELFCLASS64,
if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFIO::ELFCLASS32 : ELFIO::ELFCLASS64,
[this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, addr, size,
data);
@ -1337,8 +1337,9 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
sprintf(buffer.data(), "0x%016lx", addr);
if((flags & 0xffffffff) != 0xffffffff)
CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' ("
<< cause << ")" << " at address " << buffer.data() << " occurred, changing privilege level from "
<< lvl[cur_priv] << " to " << lvl[new_priv];
<< cause << ")"
<< " at address " << buffer.data() << " occurred, changing privilege level from " << lvl[cur_priv] << " to "
<< lvl[new_priv];
// reset trap state
this->reg.PRIV = new_priv;
this->reg.trap_state = 0;

7
src/iss/arch/riscv_hart_mu_p.h
View File

@ -649,7 +649,7 @@ riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p(feature_config cfg)
template <typename BASE, features_e FEAT, typename LOGCAT>
std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT, LOGCAT>::load_file(std::string name, int type) {
if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFCLASS32 : ELFCLASS64,
if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFIO::ELFCLASS32 : ELFIO::ELFCLASS64,
[this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, addr, size,
data);
@ -1565,8 +1565,9 @@ uint64_t riscv_hart_mu_p<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint64_
#endif
if((flags & 0xffffffff) != 0xffffffff)
CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' ("
<< cause << ")" << " at address " << buffer.data() << " occurred, changing privilege level from "
<< lvl[this->reg.PRIV] << " to " << lvl[new_priv];
<< cause << ")"
<< " at address " << buffer.data() << " occurred, changing privilege level from " << lvl[this->reg.PRIV]
<< " to " << lvl[new_priv];
// reset trap state
this->reg.PRIV = new_priv;
this->reg.trap_state = 0;