 Eyck Jentzsch
|
f096b15dbd
|
factors decoder into separate component
|
2022-06-19 13:17:31 +02:00 |
|
Eyck Jentzsch
|
cb5375258a
|
removes compilatioon of unneeded files
|
2022-06-10 07:19:46 +02:00 |
|
Eyck Jentzsch
|
076b5a39ad
|
fix class naming
|
2022-06-02 08:30:49 +02:00 |
|
Eyck Jentzsch
|
f40ab41899
|
fix left-over from layout refactoring
|
2022-06-02 08:30:02 +02:00 |
|
Eyck Jentzsch
|
e8fd5143bc
|
fix build options for standalone ISS
|
2022-05-31 11:05:26 +02:00 |
|
Eyck Jentzsch
|
31fb51de95
|
update tgc_c generated code
|
2022-05-30 22:15:44 +02:00 |
|
Eyck Jentzsch
|
5d481eb79d
|
fix generation of non-exception code
|
2022-05-30 22:04:16 +02:00 |
|
Eyck Jentzsch
|
1c90fe765d
|
Merge remote-tracking branch 'origin/Trace_enhancement' into develop
|
2022-05-30 14:18:09 +02:00 |
|
Eyck Jentzsch
|
52ed8b81a6
|
fixed template to work with previous code generator
|
2022-05-30 14:08:02 +02:00 |
|
Eyck Jentzsch
|
0703a0a845
|
update tgc-mapper
|
2022-05-30 07:45:32 +02:00 |
|
Eyck Jentzsch
|
0c542d42aa
|
separate generated sources
|
2022-05-21 12:48:28 +02:00 |
|
Eyck Jentzsch
|
966d1616c5
|
change source code to unified layout
|
2022-05-21 11:55:24 +02:00 |
 Eyck-Alexander Jentzsch
|
1720bd4aaa
|
adds support for compressed instructions
|
2022-05-20 15:17:58 +02:00 |
|
Eyck Jentzsch
|
df16378605
|
update template for changed code generator
|
2022-05-18 19:10:34 +02:00 |
|
Eyck Jentzsch
|
1438f0f373
|
add backannotation to pc trace plugin
|
2022-05-17 15:29:04 +02:00 |
|
Eyck Jentzsch
|
766f3ba9ee
|
fix assertion in compressed pctrace writer
|
2022-05-13 12:38:12 +02:00 |
|
Eyck Jentzsch
|
5da4e6b424
|
fix alignment check for unaligned debugger accesses
|
2022-05-13 12:37:47 +02:00 |
|
Eyck Jentzsch
|
e382217e04
|
update vm_tgc_c due reworked CoreDSL generator
|
2022-05-11 18:52:15 +02:00 |
|
Eyck Jentzsch
|
9db4e3fd87
|
fix assertion
|
2022-05-10 16:13:21 +02:00 |
|
Eyck-Alexander Jentzsch
|
bb658be3b4
|
Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop
|
2022-05-08 15:25:56 +02:00 |
|
Eyck-Alexander Jentzsch
|
6579780dc9
|
add call column in output
|
2022-05-08 15:24:26 +02:00 |
|
Eyck Jentzsch
|
e56bc12788
|
fix non-lz4 build of plugin
|
2022-05-07 17:27:11 +02:00 |
|
Eyck Jentzsch
|
e88f309ea2
|
add lz4 compression to pctrace
|
2022-05-07 17:22:06 +02:00 |
|
Eyck Jentzsch
|
03bec27376
|
implement extended instrumentation interface
|
2022-04-26 17:14:33 +02:00 |
|
Eyck Jentzsch
|
9d9008a3a2
|
fix pointer mess
|
2022-04-26 15:35:17 +02:00 |
 Stanislaw Kaushanski
|
5f6d462973
|
check that no interrupts are pending before entering the wfi wait
|
2022-04-26 13:58:20 +02:00 |
|
Eyck Jentzsch
|
a92b84bef4
|
add code word access for ISS plugins
|
2022-04-25 14:18:19 +02:00 |
|
Eyck Jentzsch
|
477c530847
|
extend debug mode handling
|
2022-04-13 11:41:01 +02:00 |
|
Eyck Jentzsch
|
c054d75717
|
update to latest coredsl description
|
2022-04-10 18:55:44 +02:00 |
|
Eyck Jentzsch
|
15cd26f800
|
remove CoreDSL ISA repo
|
2022-04-10 12:15:40 +02:00 |
|
Eyck Jentzsch
|
9465cffe79
|
adapt to change in dbt-rise-core
|
2022-04-09 14:55:36 +02:00 |
|
Eyck Jentzsch
|
00d2d06cbd
|
adapt to privileged spec
|
2022-03-31 20:33:12 +02:00 |
|
Eyck Jentzsch
|
8e4e702cb9
|
Merge remote-tracking branch 'origin/feature/reduced_output' into develop
|
2022-03-28 14:09:06 +02:00 |
|
Eyck-Alexander Jentzsch
|
58311b37db
|
Merge branch 'feature/reduced_output' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into
feature/reduced_output
|
2022-03-28 11:16:09 +02:00 |
|
Eyck-Alexander Jentzsch
|
ad8dc09bee
|
Merge branch 'feature/reduced_output' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into feature/reduced_output
|
2022-03-28 11:15:45 +02:00 |
|
Eyck Jentzsch
|
49be143588
|
make features configurable
|
2022-03-27 17:54:08 +02:00 |
|
Eyck Jentzsch
|
0aea1d0177
|
remove mcounteren in M-mode only wrapper
|
2022-03-27 17:21:46 +02:00 |
|
Eyck Jentzsch
|
6ea7721961
|
add TCM
|
2022-03-27 15:38:18 +02:00 |
|
Eyck Jentzsch
|
b0cb997009
|
add TGC_X with DMR
|
2022-03-26 10:48:21 +01:00 |
|
Eyck Jentzsch
|
9dfca612b7
|
add hardware loop CSR access
|
2022-03-25 11:33:44 +01:00 |
|
Eyck Jentzsch
|
30ae743361
|
add pctrace plugin to iss
|
2022-03-20 17:41:54 +01:00 |
|
Eyck Jentzsch
|
d91f5f9df4
|
fix compiler warning for reduced number of registers
|
2022-03-14 15:38:05 +01:00 |
|
Stanislaw Kaushanski
|
5ec457c76b
|
build pctrace plugin only if RapidJSON target is availble
|
2022-03-08 11:23:07 +01:00 |
|
Eyck Jentzsch
|
2e670c4d03
|
change interpreter structure
|
2022-03-06 15:11:38 +01:00 |
|
Eyck Jentzsch
|
3d32c33333
|
update gitignore
|
2022-03-05 20:59:45 +01:00 |
|
Eyck Jentzsch
|
521f40a3d6
|
refactored interpreter backend structure
|
2022-03-05 20:59:17 +01:00 |
|
Eyck-Alexander Jentzsch
|
2bba5645c3
|
adds functionality to reduce the output
|
2022-02-16 10:13:29 +01:00 |
|
Eyck-Alexander Jentzsch
|
bf0a5a80de
|
adds functionality to reduce the output
|
2022-02-16 10:12:45 +01:00 |
|
Eyck Jentzsch
|
b37ef973de
|
clean up
|
2022-02-14 20:36:12 +01:00 |
|
Eyck-Alexander Jentzsch
|
4c363f4073
|
adds additional functionality by fetching delay information
|
2022-02-11 11:28:00 +01:00 |